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Merge branch 'pci/controller/qcom'
- Use correct PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2 register for v2.7.0 (Manivannan Sadhasivam) - Remove "PCIE20_" prefix from register definitions (Manivannan Sadhasivam) - Sort registers and bitfield declarations (Manivannan Sadhasivam) - Convert to GENMASK and FIELD_PREP (Manivannan Sadhasivam) - Use bulk APIs for clocks of IP 1.0.0, 2.3.2, 2.3.3 (Manivannan Sadhasivam) - Use bulk APIs for reset of IP 2.1.0, 2.3.3, 2.4.0 (Manivannan Sadhasivam) - Rename qcom_pcie_config_sid_sm8250() to be non SM8250-specific (Manivannan Sadhasivam) - Add DT "mhi" register region for supported SoCs (Manivannan Sadhasivam) - Expose link transition counts via debugfs to help debug low power issues (Manivannan Sadhasivam) - Support system suspend and resume; reduce interconnect bandwidth and turn off clock and PHY if there are no active devices (Manivannan Sadhasivam) - Enable async probe by default to reduce boot time (Manivannan Sadhasivam) - Add Manivannan Sadhasivam as qcom DT binding maintainer, replacing Stanimir Varbanov (Manivannan Sadhasivam) - Add DT binding and driver support for Qcom SDX55 SoC (Manivannan Sadhasivam) - Add DT binding and driver support for SM8550 SoC (Abel Vesa) - Document msi-map and msi-map-mask DT properties (Manivannan Sadhasivam) * pci/controller/qcom: dt-bindings: PCI: qcom: Document msi-map and msi-map-mask properties PCI: qcom: Add SM8550 PCIe support dt-bindings: PCI: qcom: Add SM8550 compatible PCI: qcom: Add support for SDX55 SoC dt-bindings: PCI: qcom-ep: Fix the unit address used in example dt-bindings: PCI: qcom: Add SDX55 SoC dt-bindings: PCI: qcom: Update maintainers entry PCI: qcom: Enable async probe by default PCI: qcom: Add support for system suspend and resume PCI: qcom: Expose link transition counts via debugfs dt-bindings: PCI: qcom: Add "mhi" register region to supported SoCs PCI: qcom: Rename qcom_pcie_config_sid_sm8250() to reflect IP version PCI: qcom: Use macros for defining total no. of clocks & supplies PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.4.0 PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.3.3 PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 2.3.3 PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 2.3.2 PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 1.0.0 PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.1.0 PCI: qcom: Use lower case for hex PCI: qcom: Add missing macros for register fields PCI: qcom: Use bitfield definitions for register fields PCI: qcom: Sort and group registers and bitfield definitions PCI: qcom: Remove PCIE20_ prefix from register definitions PCI: qcom: Fix the incorrect register usage in v2.7.0 config
This commit is contained in:
Bjorn Helgaas
@@ -166,7 +166,7 @@ examples:
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#include <dt-bindings/clock/qcom,gcc-sdx55.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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pcie_ep: pcie-ep@40000000 {
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pcie_ep: pcie-ep@1c00000 {
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compatible = "qcom,sdx55-pcie-ep";
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reg = <0x01c00000 0x3000>,
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<0x40000000 0xf1d>,
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@@ -8,7 +8,7 @@ title: Qualcomm PCI express root complex
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maintainers:
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- Bjorn Andersson <bjorn.andersson@linaro.org>
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- Stanimir Varbanov <svarbanov@mm-sol.com>
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- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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description: |
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Qualcomm PCIe root complex controller is based on the Synopsys DesignWare
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@@ -33,22 +33,24 @@ properties:
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- qcom,pcie-sc8180x
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- qcom,pcie-sc8280xp
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- qcom,pcie-sdm845
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- qcom,pcie-sdx55
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- qcom,pcie-sm8150
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- qcom,pcie-sm8250
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- qcom,pcie-sm8350
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- qcom,pcie-sm8450-pcie0
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- qcom,pcie-sm8450-pcie1
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- qcom,pcie-sm8550
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- items:
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- const: qcom,pcie-msm8998
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- const: qcom,pcie-msm8996
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reg:
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minItems: 4
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maxItems: 5
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maxItems: 6
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reg-names:
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minItems: 4
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maxItems: 5
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maxItems: 6
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interrupts:
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minItems: 1
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@@ -58,6 +60,9 @@ properties:
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minItems: 1
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maxItems: 8
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iommu-map:
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maxItems: 2
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# Common definitions for clocks, clock-names and reset.
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# Platform constraints are described later.
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clocks:
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@@ -120,14 +125,20 @@ required:
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- compatible
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- reg
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- reg-names
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- interrupts
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- interrupt-names
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- "#interrupt-cells"
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- interrupt-map-mask
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- interrupt-map
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- clocks
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- clock-names
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anyOf:
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- required:
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- interrupts
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- interrupt-names
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- "#interrupt-cells"
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- required:
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- msi-map
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- msi-map-mask
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allOf:
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- $ref: /schemas/pci/pci-bus.yaml#
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- if:
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@@ -185,13 +196,15 @@ allOf:
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properties:
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reg:
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minItems: 4
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maxItems: 4
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maxItems: 5
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reg-names:
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minItems: 4
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items:
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- const: parf # Qualcomm specific registers
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- const: dbi # DesignWare PCIe registers
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- const: elbi # External local bus interface registers
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- const: config # PCIe configuration space
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- const: mhi # MHI registers
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- if:
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properties:
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@@ -201,22 +214,26 @@ allOf:
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- qcom,pcie-sc7280
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- qcom,pcie-sc8180x
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- qcom,pcie-sc8280xp
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- qcom,pcie-sdx55
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- qcom,pcie-sm8250
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- qcom,pcie-sm8350
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- qcom,pcie-sm8450-pcie0
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- qcom,pcie-sm8450-pcie1
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- qcom,pcie-sm8550
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then:
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properties:
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reg:
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minItems: 5
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maxItems: 5
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maxItems: 6
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reg-names:
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minItems: 5
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items:
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- const: parf # Qualcomm specific registers
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- const: dbi # DesignWare PCIe registers
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- const: elbi # External local bus interface registers
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- const: atu # ATU address space
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- const: config # PCIe configuration space
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- const: mhi # MHI registers
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- if:
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properties:
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@@ -639,6 +656,37 @@ allOf:
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items:
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- const: pci # PCIe core reset
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,pcie-sm8550
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then:
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properties:
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clocks:
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minItems: 7
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maxItems: 8
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clock-names:
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minItems: 7
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items:
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- const: aux # Auxiliary clock
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- const: cfg # Configuration clock
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- const: bus_master # Master AXI clock
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- const: bus_slave # Slave AXI clock
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- const: slave_q2a # Slave Q2A clock
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- const: ddrss_sf_tbu # PCIe SF TBU clock
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- const: noc_aggr # Aggre NoC PCIe AXI clock
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- const: cnoc_sf_axi # Config NoC PCIe1 AXI clock
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resets:
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minItems: 1
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maxItems: 2
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reset-names:
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minItems: 1
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items:
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- const: pci # PCIe core reset
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- const: link_down # PCIe link down reset
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- if:
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properties:
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compatible:
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@@ -669,6 +717,32 @@ allOf:
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items:
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- const: pci # PCIe core reset
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,pcie-sdx55
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then:
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properties:
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clocks:
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minItems: 7
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maxItems: 7
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clock-names:
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items:
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- const: pipe # PIPE clock
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- const: aux # Auxiliary clock
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- const: cfg # Configuration clock
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- const: bus_master # Master AXI clock
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- const: bus_slave # Slave AXI clock
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- const: slave_q2a # Slave Q2A clock
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- const: sleep # PCIe Sleep clock
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resets:
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maxItems: 1
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reset-names:
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items:
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- const: pci # PCIe core reset
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- if:
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properties:
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compatible:
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@@ -724,6 +798,7 @@ allOf:
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- qcom,pcie-sm8350
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- qcom,pcie-sm8450-pcie0
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- qcom,pcie-sm8450-pcie1
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- qcom,pcie-sm8550
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then:
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oneOf:
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- properties:
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