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dt-bindings: display: samsung,exynos7-decon: convert to dtschema
Convert the Exynos7 DECON display controller bindings to DT schema format. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220208171823.226211-6-krzysztof.kozlowski@canonical.com
This commit is contained in:
Krzysztof Kozlowski
committed by
Rob Herring
Rob Herring
parent
f16fe2d3b4
commit
5c45a11b61
@@ -1,65 +0,0 @@
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Device-Tree bindings for Samsung Exynos7 SoC display controller (DECON)
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DECON (Display and Enhancement Controller) is the Display Controller for the
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Exynos7 series of SoCs which transfers the image data from a video memory
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buffer to an external LCD interface.
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Required properties:
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- compatible: value should be "samsung,exynos7-decon";
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- reg: physical base address and length of the DECON registers set.
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- interrupts: should contain a list of all DECON IP block interrupts in the
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order: FIFO Level, VSYNC, LCD_SYSTEM. The interrupt specifier
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format depends on the interrupt controller used.
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- interrupt-names: should contain the interrupt names: "fifo", "vsync",
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"lcd_sys", in the same order as they were listed in the interrupts
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property.
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- pinctrl-0: pin control group to be used for this controller.
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- pinctrl-names: must contain a "default" entry.
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- clocks: must include clock specifiers corresponding to entries in the
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clock-names property.
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- clock-names: list of clock names sorted in the same order as the clocks
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property. Must contain "pclk_decon0", "aclk_decon0",
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"decon0_eclk", "decon0_vclk".
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- i80-if-timings: timing configuration for lcd i80 interface support.
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Optional Properties:
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- power-domains: a phandle to DECON power domain node.
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- display-timings: timing settings for DECON, as described in document [1].
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Can be used in case timings cannot be provided otherwise
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or to override timings provided by the panel.
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[1]: Documentation/devicetree/bindings/display/panel/display-timing.txt
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Example:
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SoC specific DT entry:
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decon@13930000 {
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compatible = "samsung,exynos7-decon";
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interrupt-parent = <&combiner>;
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reg = <0x13930000 0x1000>;
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interrupt-names = "lcd_sys", "vsync", "fifo";
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interrupts = <0 188 0>, <0 189 0>, <0 190 0>;
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clocks = <&clock_disp PCLK_DECON_INT>,
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<&clock_disp ACLK_DECON_INT>,
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<&clock_disp SCLK_DECON_INT_ECLK>,
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<&clock_disp SCLK_DECON_INT_EXTCLKPLL>;
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clock-names = "pclk_decon0", "aclk_decon0", "decon0_eclk",
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"decon0_vclk";
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status = "disabled";
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};
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Board specific DT entry:
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decon@13930000 {
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pinctrl-0 = <&lcd_clk &pwm1_out>;
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pinctrl-names = "default";
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status = "okay";
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};
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@@ -0,0 +1,120 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/samsung/samsung,exynos7-decon.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Samsung Exynos7 SoC Display and Enhancement Controller (DECON)
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maintainers:
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- Inki Dae <inki.dae@samsung.com>
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- Joonyoung Shim <jy0922.shim@samsung.com>
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- Seung-Woo Kim <sw0312.kim@samsung.com>
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- Kyungmin Park <kyungmin.park@samsung.com>
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- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
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description: |
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DECON (Display and Enhancement Controller) is the Display Controller for the
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Exynos7 series of SoCs which transfers the image data from a video memory
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buffer to an external LCD interface.
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properties:
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compatible:
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const: samsung,exynos7-decon
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clocks:
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minItems: 4
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maxItems: 4
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clock-names:
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items:
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- const: pclk_decon0
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- const: aclk_decon0
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- const: decon0_eclk
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- const: decon0_vclk
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display-timings:
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$ref: ../panel/display-timings.yaml#
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i80-if-timings:
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type: object
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description: timing configuration for lcd i80 interface support
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properties:
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cs-setup:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Clock cycles for the active period of address signal is enabled until
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chip select is enabled.
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default: 0
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wr-active:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Clock cycles for the active period of CS is enabled.
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default: 1
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wr-hold:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Clock cycles for the active period of CS is disabled until write
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signal is disabled.
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default: 0
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wr-setup:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Clock cycles for the active period of CS signal is enabled until
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write signal is enabled.
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default: 0
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interrupts:
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items:
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- description: FIFO level
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- description: VSYNC
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- description: LCD system
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interrupt-names:
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items:
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- const: fifo
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- const: vsync
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- const: lcd_sys
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power-domains:
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maxItems: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- clocks
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- clock-names
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- interrupts
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- interrupt-names
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- reg
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/exynos7-clk.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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display-controller@13930000 {
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compatible = "samsung,exynos7-decon";
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reg = <0x13930000 0x1000>;
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interrupt-names = "fifo", "vsync", "lcd_sys";
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interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock_disp 100>, /* PCLK_DECON_INT */
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<&clock_disp 101>, /* ACLK_DECON_INT */
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<&clock_disp 102>, /* SCLK_DECON_INT_ECLK */
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<&clock_disp 103>; /* SCLK_DECON_INT_EXTCLKPLL */
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clock-names = "pclk_decon0",
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"aclk_decon0",
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"decon0_eclk",
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"decon0_vclk";
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pinctrl-0 = <&lcd_clk &pwm1_out>;
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pinctrl-names = "default";
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};
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