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pinctrl: rockchip: Reset the pin count when recalculating SoC data

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rockchip_pinctrl_get_soc_data() mutates the static per-SoC data. The
iomux and drive offsets are recalculated idempotently, since a rerun
anchors at the values calculated before, but the total pin count only
accumulates: each run adds every bank's pins again. When the probe is
deferred and runs a second time, nr_pins doubles and every bank's
pin_base shifts, so later pin lookups resolve to the wrong bank and
the wrong registers.

Reset the pin count at the start of the calculation, so that a rerun
produces the same values.

This is verified on a Luckfox Pico Mini B (RV1103, with the pending
RV1106 series applied) by forcing the probe to defer once: without
this patch the second probe calculates nr_pins=304 instead of 152 and
no GPIO bank comes up; with it the recalculation matches the first
run and all banks work.

Fixes: d3e5116119 ("pinctrl: add pinctrl driver for Rockchip SoCs")
Link: https://sashiko.dev/#/patchset/20260729132736.3807082-1-sjg@chromium.org?part=4
Assisted-by: Claude:claude-opus-5
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Linus Walleij <linusw@kernel.org>
This commit is contained in:
Simon Glass
2026-08-03 08:10:23 -06:00
committed by Linus Walleij
parent 27e5b8efc2
commit 5b695c191c
1 changed files with 10 additions and 0 deletions
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10
drivers/pinctrl/pinctrl-rockchip.c
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@@ -4437,6 +4437,16 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
pmu_offs = ctrl->pmu_mux_offset;
drv_pmu_offs = ctrl->pmu_drv_offset;
drv_grf_offs = ctrl->grf_drv_offset;
/*
* This function mutates the static per-SoC data. Most of it is
* idempotent: recalculated iomux and drv offsets anchor at the
* values calculated by a previous run. The pin count is not, so
* reset it here; otherwise it accumulates when the probe runs
* again after a probe deferral, shifting every bank's pin_base.
*/
ctrl->nr_pins = 0;
bank = ctrl->pin_banks;
for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
int bank_pins = 0;