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drm/i915/dram: Use REG_GENMASK() & co. for the SKL+ DIMM regs

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Modernize the SKL/ICL DIMM registers with REG_GENMASK() & co.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/20251029204215.12292-2-ville.syrjala@linux.intel.com
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
This commit is contained in:
Ville Syrjälä
2025-10-29 22:42:13 +02:00
parent 1a7fad2aea
commit 5b23aa423a
2 changed files with 29 additions and 34 deletions
Download Patch File Download Diff File Expand all files Collapse all files

51
drivers/gpu/drm/i915/intel_mchbar_regs.h
View File

@@ -130,11 +130,11 @@
#define DG1_DRAM_T_RAS_MASK REG_GENMASK(8, 1)
#define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000)
#define SKL_DRAM_DDR_TYPE_MASK (0x3 << 0)
#define SKL_DRAM_DDR_TYPE_DDR4 (0 << 0)
#define SKL_DRAM_DDR_TYPE_DDR3 (1 << 0)
#define SKL_DRAM_DDR_TYPE_LPDDR3 (2 << 0)
#define SKL_DRAM_DDR_TYPE_LPDDR4 (3 << 0)
#define SKL_DRAM_DDR_TYPE_MASK REG_GENMASK(1, 0)
#define SKL_DRAM_DDR_TYPE_DDR4 REG_FIELD_PREP(SKL_DRAM_DDR_TYPE_MASK, 0)
#define SKL_DRAM_DDR_TYPE_DDR3 REG_FIELD_PREP(SKL_DRAM_DDR_TYPE_MASK, 1)
#define SKL_DRAM_DDR_TYPE_LPDDR3 REG_FIELD_PREP(SKL_DRAM_DDR_TYPE_MASK, 2)
#define SKL_DRAM_DDR_TYPE_LPDDR4 REG_FIELD_PREP(SKL_DRAM_DDR_TYPE_MASK, 3)
/* snb MCH registers for reading the DRAM channel configuration */
#define MAD_DIMM_C0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
@@ -161,29 +161,24 @@
#define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
#define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)
#define SKL_DRAM_S_SHIFT 16
#define SKL_DRAM_SIZE_MASK 0x3F
#define SKL_DRAM_WIDTH_MASK (0x3 << 8)
#define SKL_DRAM_WIDTH_SHIFT 8
#define SKL_DRAM_WIDTH_X8 (0x0 << 8)
#define SKL_DRAM_WIDTH_X16 (0x1 << 8)
#define SKL_DRAM_WIDTH_X32 (0x2 << 8)
#define SKL_DRAM_RANK_MASK (0x1 << 10)
#define SKL_DRAM_RANK_SHIFT 10
#define SKL_DRAM_RANK_1 (0x0 << 10)
#define SKL_DRAM_RANK_2 (0x1 << 10)
#define SKL_DRAM_RANK_MASK (0x1 << 10)
#define ICL_DRAM_SIZE_MASK 0x7F
#define ICL_DRAM_WIDTH_MASK (0x3 << 7)
#define ICL_DRAM_WIDTH_SHIFT 7
#define ICL_DRAM_WIDTH_X8 (0x0 << 7)
#define ICL_DRAM_WIDTH_X16 (0x1 << 7)
#define ICL_DRAM_WIDTH_X32 (0x2 << 7)
#define ICL_DRAM_RANK_MASK (0x3 << 9)
#define ICL_DRAM_RANK_SHIFT 9
#define ICL_DRAM_RANK_1 (0x0 << 9)
#define ICL_DRAM_RANK_2 (0x1 << 9)
#define ICL_DRAM_RANK_3 (0x2 << 9)
#define ICL_DRAM_RANK_4 (0x3 << 9)
#define SKL_DRAM_SIZE_MASK REG_GENMASK(5, 0)
#define SKL_DRAM_WIDTH_MASK REG_GENMASK(9, 8)
#define SKL_DRAM_WIDTH_X8 REG_FIELD_PREP(SKL_DRAM_WIDTH_MASK, 0)
#define SKL_DRAM_WIDTH_X16 REG_FIELD_PREP(SKL_DRAM_WIDTH_MASK, 1)
#define SKL_DRAM_WIDTH_X32 REG_FIELD_PREP(SKL_DRAM_WIDTH_MASK, 2)
#define SKL_DRAM_RANK_MASK REG_GENMASK(10, 10)
#define SKL_DRAM_RANK_1 REG_FIELD_PREP(SKL_DRAM_RANK_MASK, 0)
#define SKL_DRAM_RANK_2 REG_FIELD_PREP(SKL_DRAM_RANK_MASK, 1)
#define ICL_DRAM_SIZE_MASK REG_GENMASK(6, 0)
#define ICL_DRAM_WIDTH_MASK REG_GENMASK(8, 7)
#define ICL_DRAM_WIDTH_X8 REG_FIELD_PREP(ICL_DRAM_WIDTH_MASK, 0)
#define ICL_DRAM_WIDTH_X16 REG_FIELD_PREP(ICL_DRAM_WIDTH_MASK, 1)
#define ICL_DRAM_WIDTH_X32 REG_FIELD_PREP(ICL_DRAM_WIDTH_MASK, 2)
#define ICL_DRAM_RANK_MASK REG_GENMASK(10, 9)
#define ICL_DRAM_RANK_1 REG_FIELD_PREP(ICL_DRAM_RANK_MASK, 0)
#define ICL_DRAM_RANK_2 REG_FIELD_PREP(ICL_DRAM_RANK_MASK, 1)
#define ICL_DRAM_RANK_3 REG_FIELD_PREP(ICL_DRAM_RANK_MASK, 2)
#define ICL_DRAM_RANK_4 REG_FIELD_PREP(ICL_DRAM_RANK_MASK, 3)
#define SA_PERF_STATUS_0_0_0_MCHBAR_PC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5918)
#define DG1_QCLK_RATIO_MASK REG_GENMASK(9, 2)

12
drivers/gpu/drm/i915/soc/intel_dram.c
View File

@@ -269,7 +269,7 @@ static int intel_dimm_num_devices(const struct dram_dimm_info *dimm)
/* Returns total Gb for the whole DIMM */
static int skl_get_dimm_size(u16 val)
{
return (val & SKL_DRAM_SIZE_MASK) * 8;
return REG_FIELD_GET(SKL_DRAM_SIZE_MASK, val) * 8;
}
static int skl_get_dimm_width(u16 val)
@@ -281,7 +281,7 @@ static int skl_get_dimm_width(u16 val)
case SKL_DRAM_WIDTH_X8:
case SKL_DRAM_WIDTH_X16:
case SKL_DRAM_WIDTH_X32:
val = (val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT;
val = REG_FIELD_GET(SKL_DRAM_WIDTH_MASK, val);
return 8 << val;
default:
MISSING_CASE(val);
@@ -294,7 +294,7 @@ static int skl_get_dimm_ranks(u16 val)
if (skl_get_dimm_size(val) == 0)
return 0;
val = (val & SKL_DRAM_RANK_MASK) >> SKL_DRAM_RANK_SHIFT;
val = REG_FIELD_GET(SKL_DRAM_RANK_MASK, val);
return val + 1;
}
@@ -302,7 +302,7 @@ static int skl_get_dimm_ranks(u16 val)
/* Returns total Gb for the whole DIMM */
static int icl_get_dimm_size(u16 val)
{
return (val & ICL_DRAM_SIZE_MASK) * 8 / 2;
return REG_FIELD_GET(ICL_DRAM_SIZE_MASK, val) * 8 / 2;
}
static int icl_get_dimm_width(u16 val)
@@ -314,7 +314,7 @@ static int icl_get_dimm_width(u16 val)
case ICL_DRAM_WIDTH_X8:
case ICL_DRAM_WIDTH_X16:
case ICL_DRAM_WIDTH_X32:
val = (val & ICL_DRAM_WIDTH_MASK) >> ICL_DRAM_WIDTH_SHIFT;
val = REG_FIELD_GET(ICL_DRAM_WIDTH_MASK, val);
return 8 << val;
default:
MISSING_CASE(val);
@@ -327,7 +327,7 @@ static int icl_get_dimm_ranks(u16 val)
if (icl_get_dimm_size(val) == 0)
return 0;
val = (val & ICL_DRAM_RANK_MASK) >> ICL_DRAM_RANK_SHIFT;
val = REG_FIELD_GET(ICL_DRAM_RANK_MASK, val);
return val + 1;
}