mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-12-27 12:21:22 -05:00
Merge tag 'qcom-arm64-for-6.18-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
More Qualocmm Arm64 DeviceTree updates for v6.18 Introduce the Hamoa IoT SOM and the Hamoa EVK board, the HP Omnibook X14, the Particle Tachyon board, and the Samsung Galaxy S22. On IPQ5018 another set of UART and I2C controllers are added. On Lemans SDHCI and the camera subsystem is introduced, the USB controllers are updated to the new flattened binding. The Lemans EVK gains Ethernet definition, more QUP controllers and their GPI DMA engines are defined. PCIe, SDHCI, remoteproc and iris video accelerator are added as well. On the Monaco platform GPU and GMU are introduced, the USB controller nodes are updated to the new flattened binding. The GPU is enabled on the EVK and the Ride boards. SDCC and MDSS resets are defined on MSM8916, MSM8939 also gets the MDSS reset. On QCM2290 the camera clock interface is added. On the QCS615 tsens and related thermal-zones are introduced. On SDM845 the OnePlus 6 gains notifications LED, and the sensor core (SLPI) is enabled on the Samsung Galaxy S9. WiFi and Bluetooth is enabled on the SM8750 MTP. The IRIS video accelerator is introduce for X Elite and enabled on a variety of laptops. DisplayPort controllers on a variety of boards are updated to describe additional pixel clocks, used for MST. * tag 'qcom-arm64-for-6.18-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (57 commits) arm64: dts: qcom: Add MST pixel streams for displayport arm64: dts: qcom: sm6350: correct DP compatibility strings arm64: dts: qcom: monaco-evk: Enable Adreno 623 GPU arm64: dts: qcom: qcs8300-ride: Enable Adreno 623 GPU arm64: dts: qcom: qcs8300: Add gpu and gmu nodes dt-bindings: arm: qcom: sort sm8450 boards arm64: dts: qcom: Add base HAMOA-IOT-EVK board arm64: dts: qcom: Add HAMOA-IOT-SOM platform dt-bindings: arm: qcom: Document HAMOA-IOT-EVK board arm64: dts: qcom: sm8750-mtp: Add WiFi and Bluetooth arm64: dts: qcom: msm8953-xiaomi-daisy: fix cd-gpios arm64: dts: qcom: ipq5018: add QUP1 UART2 node arm64: dts: qcom: lemans: Flatten usb controller nodes arm64: dts: qcom: qcs615: Enable TSENS support for QCS615 SoC arm64: dts: qcom: sdm845-enchilada: Add notification LED arm64: dts: qcom: apq8016-sbc: Drop redundant HDMI bridge status arm64: dts: qcom: apq8016-sbc: Correct HDMI bridge #sound-dai-cells arm64: dts: qcom: lemans: Add PCIe lane equalization preset properties arm64: dts: qcom: sm8450: enable camera clock controller by default arm64: dts: qcom: qcm2290: Add CCI node ... Link: https://lore.kernel.org/r/20250921022346.598294-1-andersson@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
@@ -337,6 +337,7 @@ properties:
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- items:
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- enum:
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- fairphone,fp5
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- particle,tachyon
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- qcom,qcm6490-idp
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- qcom,qcs6490-rb3gen2
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- shift,otter
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@@ -1010,9 +1011,9 @@ properties:
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- enum:
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- qcom,sm8450-hdk
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- qcom,sm8450-qrd
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- samsung,r0q
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- sony,pdx223
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- sony,pdx224
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- samsung,r0q
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- const: qcom,sm8450
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- items:
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@@ -1074,9 +1075,16 @@ properties:
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- qcom,x1e80100-qcp
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- const: qcom,x1e80100
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- items:
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- enum:
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- qcom,hamoa-iot-evk
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- const: qcom,hamoa-iot-som
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- const: qcom,x1e80100
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- items:
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- enum:
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- asus,zenbook-a14-ux3407qa
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- hp,omnibook-x14-fe1
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- lenovo,thinkbook-16
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- qcom,x1p42100-crd
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- const: qcom,x1p42100
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@@ -1187,6 +1187,8 @@ patternProperties:
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description: Parade Technologies Inc.
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"^parallax,.*":
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description: Parallax Inc.
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"^particle,.*":
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description: Particle Industries, Inc.
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"^pda,.*":
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description: Precision Design Associates, Inc.
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"^pegatron,.*":
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@@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8039-t2.dtb
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dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb
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dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
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dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb
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dtb-$(CONFIG_ARCH_QCOM) += hamoa-iot-evk.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq5018-rdp432-c2.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq5018-tplink-archer-ax55-v1.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp441.dtb
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@@ -30,6 +31,10 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp449.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp453.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp454.dtb
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dtb-$(CONFIG_ARCH_QCOM) += lemans-evk.dtb
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lemans-evk-camera-csi1-imx577-dtbs := lemans-evk.dtb lemans-evk-camera-csi1-imx577.dtbo
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dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-camera-csi1-imx577.dtb
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dtb-$(CONFIG_ARCH_QCOM) += monaco-evk.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8216-samsung-fortuna3g.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb
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@@ -116,6 +121,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-poplar.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8998-xiaomi-sagit.dtb
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dtb-$(CONFIG_ARCH_QCOM) += qcm6490-fairphone-fp5.dtb
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dtb-$(CONFIG_ARCH_QCOM) += qcm6490-idp.dtb
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dtb-$(CONFIG_ARCH_QCOM) += qcm6490-particle-tachyon.dtb
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dtb-$(CONFIG_ARCH_QCOM) += qcm6490-shift-otter.dtb
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dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb
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dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb
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@@ -289,6 +295,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx214.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx215.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sm8450-hdk.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sm8450-qrd.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sm8450-samsung-r0q.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx223.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx224.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sm8550-hdk.dtb
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@@ -339,5 +346,7 @@ x1p42100-asus-zenbook-a14-el2-dtbs := x1p42100-asus-zenbook-a14.dtb x1-el2.dtbo
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dtb-$(CONFIG_ARCH_QCOM) += x1p42100-asus-zenbook-a14.dtb x1p42100-asus-zenbook-a14-el2.dtb
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x1p42100-crd-el2-dtbs := x1p42100-crd.dtb x1-el2.dtbo
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dtb-$(CONFIG_ARCH_QCOM) += x1p42100-crd.dtb x1p42100-crd-el2.dtb
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x1p42100-hp-omnibook-x14-el2-dtbs := x1p42100-hp-omnibook-x14.dtb x1-el2.dtbo
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dtb-$(CONFIG_ARCH_QCOM) += x1p42100-hp-omnibook-x14.dtb x1p42100-hp-omnibook-x14-el2.dtb
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x1p42100-lenovo-thinkbook-16-el2-dtbs := x1p42100-lenovo-thinkbook-16.dtb x1-el2.dtbo
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dtb-$(CONFIG_ARCH_QCOM) += x1p42100-lenovo-thinkbook-16.dtb x1p42100-lenovo-thinkbook-16-el2.dtb
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@@ -157,8 +157,6 @@ &blsp_i2c4 {
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status = "okay";
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adv_bridge: bridge@39 {
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status = "okay";
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compatible = "adi,adv7533";
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reg = <0x39>;
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@@ -181,7 +179,7 @@ adv_bridge: bridge@39 {
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pinctrl-names = "default","sleep";
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pinctrl-0 = <&adv7533_int_active &adv7533_switch_active>;
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pinctrl-1 = <&adv7533_int_suspend &adv7533_switch_suspend>;
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#sound-dai-cells = <1>;
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#sound-dai-cells = <0>;
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ports {
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#address-cells = <1>;
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@@ -346,7 +344,7 @@ cpu {
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sound-dai = <&lpass MI2S_QUATERNARY>;
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};
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codec {
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sound-dai = <&adv_bridge 0>;
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sound-dai = <&adv_bridge>;
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};
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};
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1222
arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts
Normal file
1222
arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts
Normal file
File diff suppressed because it is too large
Load Diff
619
arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi
Normal file
619
arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi
Normal file
@@ -0,0 +1,619 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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#include "x1e80100.dtsi"
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#include "x1e80100-pmics.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
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/ {
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reserved-memory {
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linux,cma {
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compatible = "shared-dma-pool";
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size = <0x0 0x8000000>;
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reusable;
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linux,cma-default;
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};
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};
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};
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&apps_rsc {
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/* PMC8380C_B */
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regulators-0 {
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compatible = "qcom,pm8550-rpmh-regulators";
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qcom,pmic-id = "b";
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vdd-bob1-supply = <&vph_pwr>;
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vdd-bob2-supply = <&vph_pwr>;
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vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>;
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vdd-l2-l13-l14-supply = <&vreg_bob1>;
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vdd-l5-l16-supply = <&vreg_bob1>;
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vdd-l6-l7-supply = <&vreg_bob2>;
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vdd-l8-l9-supply = <&vreg_bob1>;
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vdd-l12-supply = <&vreg_s5j_1p2>;
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vdd-l15-supply = <&vreg_s4c_1p8>;
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vdd-l17-supply = <&vreg_bob2>;
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vreg_bob1: bob1 {
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regulator-name = "vreg_bob1";
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regulator-min-microvolt = <3008000>;
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regulator-max-microvolt = <3960000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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};
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vreg_bob2: bob2 {
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regulator-name = "vreg_bob2";
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regulator-min-microvolt = <2504000>;
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regulator-max-microvolt = <3008000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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};
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vreg_l1b_1p8: ldo1 {
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regulator-name = "vreg_l1b_1p8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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};
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vreg_l2b_3p0: ldo2 {
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regulator-name = "vreg_l2b_3p0";
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regulator-min-microvolt = <3072000>;
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regulator-max-microvolt = <3100000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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};
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vreg_l4b_1p8: ldo4 {
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regulator-name = "vreg_l4b_1p8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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};
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vreg_l5b_3p0: ldo5 {
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regulator-name = "vreg_l5b_3p0";
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3000000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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};
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vreg_l6b_1p8: ldo6 {
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regulator-name = "vreg_l6b_1p8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <2960000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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};
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vreg_l7b_2p8: ldo7 {
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regulator-name = "vreg_l7b_2p8";
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <2800000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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};
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vreg_l8b_3p0: ldo8 {
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regulator-name = "vreg_l8b_3p0";
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regulator-min-microvolt = <3072000>;
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regulator-max-microvolt = <3072000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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};
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vreg_l9b_2p9: ldo9 {
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regulator-name = "vreg_l9b_2p9";
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regulator-min-microvolt = <2960000>;
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regulator-max-microvolt = <2960000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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};
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|
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vreg_l10b_1p8: ldo10 {
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regulator-name = "vreg_l10b_1p8";
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regulator-min-microvolt = <1800000>;
|
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regulator-max-microvolt = <1800000>;
|
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
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};
|
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|
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vreg_l12b_1p2: ldo12 {
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regulator-name = "vreg_l12b_1p2";
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regulator-min-microvolt = <1200000>;
|
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regulator-max-microvolt = <1200000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
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regulator-always-on;
|
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};
|
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|
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vreg_l13b_3p0: ldo13 {
|
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regulator-name = "vreg_l13b_3p0";
|
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regulator-min-microvolt = <3072000>;
|
||||
regulator-max-microvolt = <3100000>;
|
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
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|
||||
vreg_l14b_3p0: ldo14 {
|
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regulator-name = "vreg_l14b_3p0";
|
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regulator-min-microvolt = <3072000>;
|
||||
regulator-max-microvolt = <3072000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l15b_1p8: ldo15 {
|
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regulator-name = "vreg_l15b_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vreg_l16b_2p9: ldo16 {
|
||||
regulator-name = "vreg_l16b_2p9";
|
||||
regulator-min-microvolt = <2912000>;
|
||||
regulator-max-microvolt = <2912000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l17b_2p5: ldo17 {
|
||||
regulator-name = "vreg_l17b_2p5";
|
||||
regulator-min-microvolt = <2504000>;
|
||||
regulator-max-microvolt = <2504000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
|
||||
/* PMC8380VE_C */
|
||||
regulators-1 {
|
||||
compatible = "qcom,pm8550ve-rpmh-regulators";
|
||||
qcom,pmic-id = "c";
|
||||
|
||||
vdd-l1-supply = <&vreg_s5j_1p2>;
|
||||
vdd-l2-supply = <&vreg_s1f_0p7>;
|
||||
vdd-l3-supply = <&vreg_s1f_0p7>;
|
||||
vdd-s4-supply = <&vph_pwr>;
|
||||
|
||||
vreg_s4c_1p8: smps4 {
|
||||
regulator-name = "vreg_s4c_1p8";
|
||||
regulator-min-microvolt = <1856000>;
|
||||
regulator-max-microvolt = <2000000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l1c_1p2: ldo1 {
|
||||
regulator-name = "vreg_l1c_1p2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l2c_0p8: ldo2 {
|
||||
regulator-name = "vreg_l2c_0p8";
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <920000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l3c_0p8: ldo3 {
|
||||
regulator-name = "vreg_l3c_0p8";
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <920000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
|
||||
/* PMC8380_D */
|
||||
regulators-2 {
|
||||
compatible = "qcom,pmc8380-rpmh-regulators";
|
||||
qcom,pmic-id = "d";
|
||||
|
||||
vdd-l1-supply = <&vreg_s1f_0p7>;
|
||||
vdd-l2-supply = <&vreg_s1f_0p7>;
|
||||
vdd-l3-supply = <&vreg_s4c_1p8>;
|
||||
vdd-s1-supply = <&vph_pwr>;
|
||||
|
||||
vreg_l1d_0p8: ldo1 {
|
||||
regulator-name = "vreg_l1d_0p8";
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <920000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l2d_0p9: ldo2 {
|
||||
regulator-name = "vreg_l2d_0p9";
|
||||
regulator-min-microvolt = <912000>;
|
||||
regulator-max-microvolt = <920000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l3d_1p8: ldo3 {
|
||||
regulator-name = "vreg_l3d_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
|
||||
/* PMC8380_E */
|
||||
regulators-3 {
|
||||
compatible = "qcom,pmc8380-rpmh-regulators";
|
||||
qcom,pmic-id = "e";
|
||||
|
||||
vdd-l2-supply = <&vreg_s1f_0p7>;
|
||||
vdd-l3-supply = <&vreg_s5j_1p2>;
|
||||
|
||||
vreg_l2e_0p8: ldo2 {
|
||||
regulator-name = "vreg_l2e_0p8";
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <920000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l3e_1p2: ldo3 {
|
||||
regulator-name = "vreg_l3e_1p2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
|
||||
/* PMC8380_F */
|
||||
regulators-4 {
|
||||
compatible = "qcom,pmc8380-rpmh-regulators";
|
||||
qcom,pmic-id = "f";
|
||||
|
||||
vdd-l1-supply = <&vreg_s5j_1p2>;
|
||||
vdd-l2-supply = <&vreg_s5j_1p2>;
|
||||
vdd-l3-supply = <&vreg_s5j_1p2>;
|
||||
vdd-s1-supply = <&vph_pwr>;
|
||||
|
||||
vreg_s1f_0p7: smps1 {
|
||||
regulator-name = "vreg_s1f_0p7";
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l1f_1p0: ldo1 {
|
||||
regulator-name = "vreg_l1f_1p0";
|
||||
regulator-min-microvolt = <1024000>;
|
||||
regulator-max-microvolt = <1024000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l2f_1p0: ldo2 {
|
||||
regulator-name = "vreg_l2f_1p0";
|
||||
regulator-min-microvolt = <1024000>;
|
||||
regulator-max-microvolt = <1024000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l3f_1p0: ldo3 {
|
||||
regulator-name = "vreg_l3f_1p0";
|
||||
regulator-min-microvolt = <1024000>;
|
||||
regulator-max-microvolt = <1024000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
|
||||
/* PMC8380VE_I */
|
||||
regulators-6 {
|
||||
compatible = "qcom,pm8550ve-rpmh-regulators";
|
||||
qcom,pmic-id = "i";
|
||||
|
||||
vdd-l1-supply = <&vreg_s4c_1p8>;
|
||||
vdd-l2-supply = <&vreg_s5j_1p2>;
|
||||
vdd-l3-supply = <&vreg_s1f_0p7>;
|
||||
vdd-s1-supply = <&vph_pwr>;
|
||||
vdd-s2-supply = <&vph_pwr>;
|
||||
|
||||
vreg_s1i_0p9: smps1 {
|
||||
regulator-name = "vreg_s1i_0p9";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <920000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_s2i_1p0: smps2 {
|
||||
regulator-name = "vreg_s2i_1p0";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l1i_1p8: ldo1 {
|
||||
regulator-name = "vreg_l1i_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l2i_1p2: ldo2 {
|
||||
regulator-name = "vreg_l2i_1p2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l3i_0p8: ldo3 {
|
||||
regulator-name = "vreg_l3i_0p8";
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <920000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
|
||||
/* PMC8380VE_J */
|
||||
regulators-7 {
|
||||
compatible = "qcom,pm8550ve-rpmh-regulators";
|
||||
qcom,pmic-id = "j";
|
||||
|
||||
vdd-l1-supply = <&vreg_s1f_0p7>;
|
||||
vdd-l2-supply = <&vreg_s5j_1p2>;
|
||||
vdd-l3-supply = <&vreg_s1f_0p7>;
|
||||
vdd-s5-supply = <&vph_pwr>;
|
||||
|
||||
vreg_s5j_1p2: smps5 {
|
||||
regulator-name = "vreg_s5j_1p2";
|
||||
regulator-min-microvolt = <1256000>;
|
||||
regulator-max-microvolt = <1304000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l1j_0p8: ldo1 {
|
||||
regulator-name = "vreg_l1j_0p8";
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <920000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l2j_1p2: ldo2 {
|
||||
regulator-name = "vreg_l2j_1p2";
|
||||
regulator-min-microvolt = <1256000>;
|
||||
regulator-max-microvolt = <1256000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l3j_0p8: ldo3 {
|
||||
regulator-name = "vreg_l3j_0p8";
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <920000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&iris {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu_zap_shader {
|
||||
firmware-name = "qcom/x1e80100/gen70500_zap.mbn";
|
||||
};
|
||||
|
||||
&pcie4 {
|
||||
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
|
||||
|
||||
pinctrl-0 = <&pcie4_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie4_phy {
|
||||
vdda-phy-supply = <&vreg_l3i_0p8>;
|
||||
vdda-pll-supply = <&vreg_l3e_1p2>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie6a {
|
||||
perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
|
||||
|
||||
pinctrl-0 = <&pcie6a_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie6a_phy {
|
||||
vdda-phy-supply = <&vreg_l1d_0p8>;
|
||||
vdda-pll-supply = <&vreg_l2j_1p2>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qupv3_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qupv3_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qupv3_2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&remoteproc_adsp {
|
||||
firmware-name = "qcom/x1e80100/adsp.mbn",
|
||||
"qcom/x1e80100/adsp_dtb.mbn";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&remoteproc_cdsp {
|
||||
firmware-name = "qcom/x1e80100/cdsp.mbn",
|
||||
"qcom/x1e80100/cdsp_dtb.mbn";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
gpio-reserved-ranges = <34 2>, /* TPM LP & INT */
|
||||
<44 4>; /* SPI (TPM) */
|
||||
|
||||
pcie4_default: pcie4-default-state {
|
||||
clkreq-n-pins {
|
||||
pins = "gpio147";
|
||||
function = "pcie4_clk";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
perst-n-pins {
|
||||
pins = "gpio146";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
wake-n-pins {
|
||||
pins = "gpio148";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pcie6a_default: pcie6a-default-state {
|
||||
clkreq-n-pins {
|
||||
pins = "gpio153";
|
||||
function = "pcie6a_clk";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
perst-n-pins {
|
||||
pins = "gpio152";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
wake-n-pins {
|
||||
pins = "gpio154";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usb_1_ss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1_ss0_dwc3 {
|
||||
dr_mode = "otg";
|
||||
usb-role-switch;
|
||||
};
|
||||
|
||||
&usb_1_ss0_hsphy {
|
||||
vdd-supply = <&vreg_l3j_0p8>;
|
||||
vdda12-supply = <&vreg_l2j_1p2>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1_ss0_qmpphy {
|
||||
vdda-phy-supply = <&vreg_l2j_1p2>;
|
||||
vdda-pll-supply = <&vreg_l1j_0p8>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1_ss1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1_ss1_dwc3 {
|
||||
dr_mode = "otg";
|
||||
usb-role-switch;
|
||||
};
|
||||
|
||||
&usb_1_ss1_hsphy {
|
||||
vdd-supply = <&vreg_l3j_0p8>;
|
||||
vdda12-supply = <&vreg_l2j_1p2>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1_ss1_qmpphy {
|
||||
vdda-phy-supply = <&vreg_l2j_1p2>;
|
||||
vdda-pll-supply = <&vreg_l2d_0p9>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1_ss2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1_ss2_dwc3 {
|
||||
dr_mode = "otg";
|
||||
usb-role-switch;
|
||||
};
|
||||
|
||||
&usb_1_ss2_hsphy {
|
||||
vdd-supply = <&vreg_l3j_0p8>;
|
||||
vdda12-supply = <&vreg_l2j_1p2>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1_ss2_qmpphy {
|
||||
vdda-phy-supply = <&vreg_l2j_1p2>;
|
||||
vdda-pll-supply = <&vreg_l2d_0p9>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_2_dwc3 {
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&usb_2_hsphy {
|
||||
vdd-supply = <&vreg_l2e_0p8>;
|
||||
vdda12-supply = <&vreg_l3e_1p2>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_mp {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_mp_hsphy0 {
|
||||
vdd-supply = <&vreg_l2e_0p8>;
|
||||
vdda12-supply = <&vreg_l3e_1p2>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_mp_hsphy1 {
|
||||
vdd-supply = <&vreg_l2e_0p8>;
|
||||
vdda12-supply = <&vreg_l3e_1p2>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_mp_qmpphy0 {
|
||||
vdda-phy-supply = <&vreg_l3e_1p2>;
|
||||
vdda-pll-supply = <&vreg_l3c_0p8>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_mp_qmpphy1 {
|
||||
vdda-phy-supply = <&vreg_l3e_1p2>;
|
||||
vdda-pll-supply = <&vreg_l3c_0p8>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
@@ -490,6 +490,16 @@ blsp1_uart1: serial@78af000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp1_uart2: serial@78b0000 {
|
||||
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
||||
reg = <0x078b0000 0x200>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
|
||||
<&gcc GCC_BLSP1_AHB_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp1_spi1: spi@78b5000 {
|
||||
compatible = "qcom,spi-qup-v2.2.1";
|
||||
#address-cells = <1>;
|
||||
@@ -504,6 +514,21 @@ blsp1_spi1: spi@78b5000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp1_i2c3: i2c@78b7000 {
|
||||
compatible = "qcom,i2c-qup-v2.2.1";
|
||||
reg = <0x078b7000 0x600>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
|
||||
<&gcc GCC_BLSP1_AHB_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
clock-frequency = <400000>;
|
||||
dmas = <&blsp_dma 9>, <&blsp_dma 8>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qpic_bam: dma-controller@7984000 {
|
||||
compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
|
||||
reg = <0x07984000 0x1c000>;
|
||||
|
||||
97
arch/arm64/boot/dts/qcom/lemans-evk-camera-csi1-imx577.dtso
Normal file
97
arch/arm64/boot/dts/qcom/lemans-evk-camera-csi1-imx577.dtso
Normal file
@@ -0,0 +1,97 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/clock/qcom,sa8775p-camcc.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
&{/} {
|
||||
vreg_cam1_1p8: regulator-cam1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vreg_cam1";
|
||||
startup-delay-us = <10000>;
|
||||
enable-active-high;
|
||||
gpio = <&pmm8654au_0_gpios 8 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
&camss {
|
||||
vdda-pll-supply = <&vreg_l1c>;
|
||||
vdda-phy-supply = <&vreg_l4a>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
csiphy1_ep: endpoint {
|
||||
clock-lanes = <7>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
remote-endpoint = <&imx577_ep1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cci1 {
|
||||
pinctrl-0 = <&cci1_0_default>;
|
||||
pinctrl-1 = <&cci1_0_sleep>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cci1_i2c0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
camera@1a {
|
||||
compatible = "sony,imx577";
|
||||
reg = <0x1a>;
|
||||
|
||||
reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-0 = <&cam1_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
clocks = <&camcc CAM_CC_MCLK1_CLK>;
|
||||
assigned-clocks = <&camcc CAM_CC_MCLK1_CLK>;
|
||||
assigned-clock-rates = <24000000>;
|
||||
|
||||
dovdd-supply = <&vreg_s4a>;
|
||||
avdd-supply = <&vreg_cam1_1p8>;
|
||||
|
||||
port {
|
||||
imx577_ep1: endpoint {
|
||||
clock-lanes = <7>;
|
||||
link-frequencies = /bits/ 64 <600000000>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
remote-endpoint = <&csiphy1_ep>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
cam1_default: cam1-default-state {
|
||||
mclk-pins {
|
||||
pins = "gpio73";
|
||||
function = "cam_mclk";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
rst-pins {
|
||||
pins = "gpio133";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -17,6 +17,8 @@ / {
|
||||
compatible = "qcom,lemans-evk", "qcom,qcs9100", "qcom,sa8775p";
|
||||
|
||||
aliases {
|
||||
ethernet0 = ðernet0;
|
||||
mmc1 = &sdhc;
|
||||
serial0 = &uart10;
|
||||
};
|
||||
|
||||
@@ -98,6 +100,28 @@ platform {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vmmc_sdc: regulator-vmmc-sdc {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "vmmc_sdc";
|
||||
regulator-min-microvolt = <2950000>;
|
||||
regulator-max-microvolt = <2950000>;
|
||||
};
|
||||
|
||||
vreg_sdc: regulator-vreg-sdc {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "vreg_sdc";
|
||||
regulator-type = "voltage";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2950000>;
|
||||
|
||||
gpios = <&expander1 7 GPIO_ACTIVE_HIGH>;
|
||||
states = <1800000 1>, <2950000 0>;
|
||||
|
||||
startup-delay-us = <100>;
|
||||
};
|
||||
};
|
||||
|
||||
&apps_rsc {
|
||||
@@ -329,6 +353,160 @@ vreg_l8e: ldo8 {
|
||||
};
|
||||
};
|
||||
|
||||
ðernet0 {
|
||||
phy-handle = <&hsgmii_phy0>;
|
||||
phy-mode = "2500base-x";
|
||||
|
||||
pinctrl-0 = <ðernet0_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
snps,mtl-rx-config = <&mtl_rx_setup>;
|
||||
snps,mtl-tx-config = <&mtl_tx_setup>;
|
||||
|
||||
nvmem-cells = <&mac_addr0>;
|
||||
nvmem-cell-names = "mac-address";
|
||||
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
compatible = "snps,dwmac-mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
hsgmii_phy0: ethernet-phy@1c {
|
||||
compatible = "ethernet-phy-id004d.d101";
|
||||
reg = <0x1c>;
|
||||
reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>;
|
||||
reset-assert-us = <11000>;
|
||||
reset-deassert-us = <70000>;
|
||||
};
|
||||
};
|
||||
|
||||
mtl_rx_setup: rx-queues-config {
|
||||
snps,rx-queues-to-use = <4>;
|
||||
snps,rx-sched-sp;
|
||||
|
||||
queue0 {
|
||||
snps,dcb-algorithm;
|
||||
snps,map-to-dma-channel = <0x0>;
|
||||
snps,route-up;
|
||||
snps,priority = <0x1>;
|
||||
};
|
||||
|
||||
queue1 {
|
||||
snps,dcb-algorithm;
|
||||
snps,map-to-dma-channel = <0x1>;
|
||||
snps,route-ptp;
|
||||
};
|
||||
|
||||
queue2 {
|
||||
snps,avb-algorithm;
|
||||
snps,map-to-dma-channel = <0x2>;
|
||||
snps,route-avcp;
|
||||
};
|
||||
|
||||
queue3 {
|
||||
snps,avb-algorithm;
|
||||
snps,map-to-dma-channel = <0x3>;
|
||||
snps,priority = <0xc>;
|
||||
};
|
||||
};
|
||||
|
||||
mtl_tx_setup: tx-queues-config {
|
||||
snps,tx-queues-to-use = <4>;
|
||||
|
||||
queue0 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
|
||||
queue1 {
|
||||
snps,dcb-algorithm;
|
||||
};
|
||||
|
||||
queue2 {
|
||||
snps,avb-algorithm;
|
||||
snps,send_slope = <0x1000>;
|
||||
snps,idle_slope = <0x1000>;
|
||||
snps,high_credit = <0x3e800>;
|
||||
snps,low_credit = <0xffc18000>;
|
||||
};
|
||||
|
||||
queue3 {
|
||||
snps,avb-algorithm;
|
||||
snps,send_slope = <0x1000>;
|
||||
snps,idle_slope = <0x1000>;
|
||||
snps,high_credit = <0x3e800>;
|
||||
snps,low_credit = <0xffc18000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpi_dma0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpi_dma1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpi_dma2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c18 {
|
||||
status = "okay";
|
||||
|
||||
expander0: gpio@38 {
|
||||
compatible = "ti,tca9538";
|
||||
reg = <0x38>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
expander1: gpio@39 {
|
||||
compatible = "ti,tca9538";
|
||||
reg = <0x39>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
expander2: gpio@3a {
|
||||
compatible = "ti,tca9538";
|
||||
reg = <0x3a>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
expander3: gpio@3b {
|
||||
compatible = "ti,tca9538";
|
||||
reg = <0x3b>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "giantec,gt24c256c", "atmel,24c256";
|
||||
reg = <0x50>;
|
||||
pagesize = <64>;
|
||||
|
||||
nvmem-layout {
|
||||
compatible = "fixed-layout";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
mac_addr0: mac-addr@0 {
|
||||
reg = <0x0 0x6>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&iris {
|
||||
firmware-name = "qcom/vpu/vpu30_p4_s6_16mb.mbn";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss0 {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -375,14 +553,178 @@ &mdss0_dp1_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
pinctrl-0 = <&pcie0_default_state>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0_phy {
|
||||
vdda-phy-supply = <&vreg_l5a>;
|
||||
vdda-pll-supply = <&vreg_l1c>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie1 {
|
||||
perst-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
pinctrl-0 = <&pcie1_default_state>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie1_phy {
|
||||
vdda-phy-supply = <&vreg_l5a>;
|
||||
vdda-pll-supply = <&vreg_l1c>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qupv3_id_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qupv3_id_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qupv3_id_2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&remoteproc_adsp {
|
||||
firmware-name = "qcom/sa8775p/adsp.mbn";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&remoteproc_cdsp0 {
|
||||
firmware-name = "qcom/sa8775p/cdsp0.mbn";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&remoteproc_cdsp1 {
|
||||
firmware-name = "qcom/sa8775p/cdsp1.mbn";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&remoteproc_gpdsp0 {
|
||||
firmware-name = "qcom/sa8775p/gpdsp0.mbn";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&remoteproc_gpdsp1 {
|
||||
firmware-name = "qcom/sa8775p/gpdsp1.mbn";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhc {
|
||||
vmmc-supply = <&vmmc_sdc>;
|
||||
vqmmc-supply = <&vreg_sdc>;
|
||||
|
||||
pinctrl-0 = <&sdc_default>, <&sd_cd>;
|
||||
pinctrl-1 = <&sdc_sleep>, <&sd_cd>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&tlmm 36 GPIO_ACTIVE_LOW>;
|
||||
no-mmc;
|
||||
no-sdio;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&serdes0 {
|
||||
phy-supply = <&vreg_l5a>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sleep_clk {
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
ethernet0_default: ethernet0-default-state {
|
||||
ethernet0_mdc: ethernet0-mdc-pins {
|
||||
pins = "gpio8";
|
||||
function = "emac0_mdc";
|
||||
drive-strength = <16>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
ethernet0_mdio: ethernet0-mdio-pins {
|
||||
pins = "gpio9";
|
||||
function = "emac0_mdio";
|
||||
drive-strength = <16>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pcie0_default_state: pcie0-default-state {
|
||||
clkreq-pins {
|
||||
pins = "gpio1";
|
||||
function = "pcie0_clkreq";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
perst-pins {
|
||||
pins = "gpio2";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
wake-pins {
|
||||
pins = "gpio0";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pcie1_default_state: pcie1-default-state {
|
||||
clkreq-pins {
|
||||
pins = "gpio3";
|
||||
function = "pcie1_clkreq";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
perst-pins {
|
||||
pins = "gpio4";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
wake-pins {
|
||||
pins = "gpio5";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
sd_cd: sd-cd-state {
|
||||
pins = "gpio36";
|
||||
function = "gpio";
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
&uart10 {
|
||||
compatible = "qcom,geni-debug-uart";
|
||||
pinctrl-0 = <&qup_uart10_default>;
|
||||
@@ -408,6 +750,27 @@ &ufs_mem_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_0 {
|
||||
dr_mode = "peripheral";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_0_hsphy {
|
||||
vdda-pll-supply = <&vreg_l7a>;
|
||||
vdda18-supply = <&vreg_l6c>;
|
||||
vdda33-supply = <&vreg_l9a>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_0_qmpphy {
|
||||
vdda-phy-supply = <&vreg_l1c>;
|
||||
vdda-pll-supply = <&vreg_l7a>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&xo_board_clk {
|
||||
clock-frequency = <38400000>;
|
||||
};
|
||||
|
||||
@@ -997,14 +997,11 @@ &ufs_mem_phy {
|
||||
&usb_0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb0_en_state>;
|
||||
dr_mode = "peripheral";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_0_dwc3 {
|
||||
dr_mode = "peripheral";
|
||||
};
|
||||
|
||||
&usb_0_hsphy {
|
||||
vdda-pll-supply = <&vreg_l7a>;
|
||||
vdda18-supply = <&vreg_l6c>;
|
||||
@@ -1023,14 +1020,11 @@ &usb_0_qmpphy {
|
||||
&usb_1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb1_en_state>;
|
||||
dr_mode = "host";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1_dwc3 {
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&usb_1_hsphy {
|
||||
vdda-pll-supply = <&vreg_l7a>;
|
||||
vdda18-supply = <&vreg_l6c>;
|
||||
@@ -1049,14 +1043,11 @@ &usb_1_qmpphy {
|
||||
&usb_2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb2_en_state>;
|
||||
dr_mode = "host";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_2_dwc3 {
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&usb_2_hsphy {
|
||||
vdda-pll-supply = <&vreg_l7a>;
|
||||
vdda18-supply = <&vreg_l6c>;
|
||||
|
||||
@@ -12,6 +12,7 @@
|
||||
#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
|
||||
#include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
|
||||
#include <dt-bindings/clock/qcom,sa8775p-videocc.h>
|
||||
#include <dt-bindings/clock/qcom,sa8775p-camcc.h>
|
||||
#include <dt-bindings/dma/qcom-gpi.h>
|
||||
#include <dt-bindings/interconnect/qcom,osm-l3.h>
|
||||
#include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
|
||||
@@ -3835,6 +3836,58 @@ apss_tpdm2_out: endpoint {
|
||||
};
|
||||
};
|
||||
|
||||
sdhc: mmc@87c4000 {
|
||||
compatible = "qcom,sa8775p-sdhci", "qcom,sdhci-msm-v5";
|
||||
reg = <0x0 0x087c4000 0x0 0x1000>;
|
||||
|
||||
interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "hc_irq",
|
||||
"pwr_irq";
|
||||
|
||||
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
|
||||
<&gcc GCC_SDCC1_APPS_CLK>;
|
||||
clock-names = "iface",
|
||||
"core";
|
||||
|
||||
interconnects = <&aggre1_noc MASTER_SDC QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
||||
&config_noc SLAVE_SDC1 QCOM_ICC_TAG_ACTIVE_ONLY>;
|
||||
interconnect-names = "sdhc-ddr",
|
||||
"cpu-sdhc";
|
||||
|
||||
iommus = <&apps_smmu 0x0 0x0>;
|
||||
dma-coherent;
|
||||
|
||||
operating-points-v2 = <&sdhc_opp_table>;
|
||||
power-domains = <&rpmhpd SA8775P_CX>;
|
||||
resets = <&gcc GCC_SDCC1_BCR>;
|
||||
|
||||
qcom,dll-config = <0x0007642c>;
|
||||
qcom,ddr-config = <0x80040868>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
sdhc_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-100000000 {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
opp-peak-kBps = <1800000 400000>;
|
||||
opp-avg-kBps = <100000 0>;
|
||||
};
|
||||
|
||||
opp-384000000 {
|
||||
opp-hz = /bits/ 64 <384000000>;
|
||||
required-opps = <&rpmhpd_opp_nom>;
|
||||
opp-peak-kBps = <5400000 1600000>;
|
||||
opp-avg-kBps = <390000 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
usb_0_hsphy: phy@88e4000 {
|
||||
compatible = "qcom,sa8775p-usb-hs-phy",
|
||||
"qcom,usb-snps-hs-5nm-phy";
|
||||
@@ -3872,12 +3925,9 @@ usb_0_qmpphy: phy@88e8000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_0: usb@a6f8800 {
|
||||
compatible = "qcom,sa8775p-dwc3", "qcom,dwc3";
|
||||
reg = <0 0x0a6f8800 0 0x400>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
usb_0: usb@a600000 {
|
||||
compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3";
|
||||
reg = <0 0x0a600000 0 0xfc100>;
|
||||
|
||||
clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
|
||||
<&gcc GCC_USB30_PRIM_MASTER_CLK>,
|
||||
@@ -3890,12 +3940,14 @@ usb_0: usb@a6f8800 {
|
||||
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
|
||||
assigned-clock-rates = <19200000>, <200000000>;
|
||||
|
||||
interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
|
||||
interrupts-extended = <&intc GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 14 IRQ_TYPE_EDGE_BOTH>,
|
||||
<&pdc 15 IRQ_TYPE_EDGE_BOTH>,
|
||||
<&pdc 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "pwr_event",
|
||||
interrupt-names = "dwc_usb3",
|
||||
"pwr_event",
|
||||
"hs_phy_irq",
|
||||
"dp_hs_phy_irq",
|
||||
"dm_hs_phy_irq",
|
||||
@@ -3912,18 +3964,13 @@ usb_0: usb@a6f8800 {
|
||||
|
||||
wakeup-source;
|
||||
|
||||
status = "disabled";
|
||||
iommus = <&apps_smmu 0x080 0x0>;
|
||||
phys = <&usb_0_hsphy>, <&usb_0_qmpphy>;
|
||||
phy-names = "usb2-phy", "usb3-phy";
|
||||
snps,dis-u1-entry-quirk;
|
||||
snps,dis-u2-entry-quirk;
|
||||
|
||||
usb_0_dwc3: usb@a600000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0 0x0a600000 0 0xe000>;
|
||||
interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
|
||||
iommus = <&apps_smmu 0x080 0x0>;
|
||||
phys = <&usb_0_hsphy>, <&usb_0_qmpphy>;
|
||||
phy-names = "usb2-phy", "usb3-phy";
|
||||
snps,dis-u1-entry-quirk;
|
||||
snps,dis-u2-entry-quirk;
|
||||
};
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_1_hsphy: phy@88e6000 {
|
||||
@@ -3963,12 +4010,9 @@ usb_1_qmpphy: phy@88ea000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_1: usb@a8f8800 {
|
||||
compatible = "qcom,sa8775p-dwc3", "qcom,dwc3";
|
||||
reg = <0 0x0a8f8800 0 0x400>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
usb_1: usb@a800000 {
|
||||
compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3";
|
||||
reg = <0 0x0a800000 0 0xfc100>;
|
||||
|
||||
clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
|
||||
<&gcc GCC_USB30_SEC_MASTER_CLK>,
|
||||
@@ -3981,12 +4025,14 @@ usb_1: usb@a8f8800 {
|
||||
<&gcc GCC_USB30_SEC_MASTER_CLK>;
|
||||
assigned-clock-rates = <19200000>, <200000000>;
|
||||
|
||||
interrupts-extended = <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
|
||||
interrupts-extended = <&intc GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&intc GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 8 IRQ_TYPE_EDGE_BOTH>,
|
||||
<&pdc 7 IRQ_TYPE_EDGE_BOTH>,
|
||||
<&pdc 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "pwr_event",
|
||||
interrupt-names = "dwc_usb3",
|
||||
"pwr_event",
|
||||
"hs_phy_irq",
|
||||
"dp_hs_phy_irq",
|
||||
"dm_hs_phy_irq",
|
||||
@@ -4003,18 +4049,13 @@ usb_1: usb@a8f8800 {
|
||||
|
||||
wakeup-source;
|
||||
|
||||
status = "disabled";
|
||||
iommus = <&apps_smmu 0x0a0 0x0>;
|
||||
phys = <&usb_1_hsphy>, <&usb_1_qmpphy>;
|
||||
phy-names = "usb2-phy", "usb3-phy";
|
||||
snps,dis-u1-entry-quirk;
|
||||
snps,dis-u2-entry-quirk;
|
||||
|
||||
usb_1_dwc3: usb@a800000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0 0x0a800000 0 0xe000>;
|
||||
interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
|
||||
iommus = <&apps_smmu 0x0a0 0x0>;
|
||||
phys = <&usb_1_hsphy>, <&usb_1_qmpphy>;
|
||||
phy-names = "usb2-phy", "usb3-phy";
|
||||
snps,dis-u1-entry-quirk;
|
||||
snps,dis-u2-entry-quirk;
|
||||
};
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_2_hsphy: phy@88e7000 {
|
||||
@@ -4030,12 +4071,9 @@ usb_2_hsphy: phy@88e7000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_2: usb@a4f8800 {
|
||||
compatible = "qcom,sa8775p-dwc3", "qcom,dwc3";
|
||||
reg = <0 0x0a4f8800 0 0x400>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
usb_2: usb@a400000 {
|
||||
compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3";
|
||||
reg = <0 0x0a400000 0 0xfc100>;
|
||||
|
||||
clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
|
||||
<&gcc GCC_USB20_MASTER_CLK>,
|
||||
@@ -4048,11 +4086,13 @@ usb_2: usb@a4f8800 {
|
||||
<&gcc GCC_USB20_MASTER_CLK>;
|
||||
assigned-clock-rates = <19200000>, <200000000>;
|
||||
|
||||
interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
|
||||
interrupts-extended = <&intc GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 10 IRQ_TYPE_EDGE_BOTH>,
|
||||
<&pdc 9 IRQ_TYPE_EDGE_BOTH>;
|
||||
interrupt-names = "pwr_event",
|
||||
interrupt-names = "dwc_usb3",
|
||||
"pwr_event",
|
||||
"hs_phy_irq",
|
||||
"dp_hs_phy_irq",
|
||||
"dm_hs_phy_irq";
|
||||
@@ -4068,18 +4108,13 @@ usb_2: usb@a4f8800 {
|
||||
|
||||
wakeup-source;
|
||||
|
||||
status = "disabled";
|
||||
iommus = <&apps_smmu 0x020 0x0>;
|
||||
phys = <&usb_2_hsphy>;
|
||||
phy-names = "usb2-phy";
|
||||
snps,dis-u1-entry-quirk;
|
||||
snps,dis-u2-entry-quirk;
|
||||
|
||||
usb_2_dwc3: usb@a400000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0 0x0a400000 0 0xe000>;
|
||||
interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
|
||||
iommus = <&apps_smmu 0x020 0x0>;
|
||||
phys = <&usb_2_hsphy>;
|
||||
phy-names = "usb2-phy";
|
||||
snps,dis-u1-entry-quirk;
|
||||
snps,dis-u2-entry-quirk;
|
||||
};
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tcsr_mutex: hwlock@1f40000 {
|
||||
@@ -4358,6 +4393,346 @@ videocc: clock-controller@abf0000 {
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
cci0: cci@ac13000 {
|
||||
compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci";
|
||||
reg = <0x0 0x0ac13000 0x0 0x1000>;
|
||||
|
||||
interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
|
||||
|
||||
power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
|
||||
|
||||
clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
|
||||
<&camcc CAM_CC_CPAS_AHB_CLK>,
|
||||
<&camcc CAM_CC_CCI_0_CLK>;
|
||||
clock-names = "camnoc_axi",
|
||||
"cpas_ahb",
|
||||
"cci";
|
||||
|
||||
pinctrl-0 = <&cci0_0_default &cci0_1_default>;
|
||||
pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
cci0_i2c0: i2c-bus@0 {
|
||||
reg = <0>;
|
||||
clock-frequency = <1000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
cci0_i2c1: i2c-bus@1 {
|
||||
reg = <1>;
|
||||
clock-frequency = <1000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
cci1: cci@ac14000 {
|
||||
compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci";
|
||||
reg = <0x0 0x0ac14000 0x0 0x1000>;
|
||||
|
||||
interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
|
||||
|
||||
power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
|
||||
|
||||
clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
|
||||
<&camcc CAM_CC_CPAS_AHB_CLK>,
|
||||
<&camcc CAM_CC_CCI_1_CLK>;
|
||||
clock-names = "camnoc_axi",
|
||||
"cpas_ahb",
|
||||
"cci";
|
||||
|
||||
pinctrl-0 = <&cci1_0_default &cci1_1_default>;
|
||||
pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
cci1_i2c0: i2c-bus@0 {
|
||||
reg = <0>;
|
||||
clock-frequency = <1000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
cci1_i2c1: i2c-bus@1 {
|
||||
reg = <1>;
|
||||
clock-frequency = <1000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
cci2: cci@ac15000 {
|
||||
compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci";
|
||||
reg = <0x0 0x0ac15000 0x0 0x1000>;
|
||||
|
||||
interrupts = <GIC_SPI 651 IRQ_TYPE_EDGE_RISING>;
|
||||
|
||||
power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
|
||||
|
||||
clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
|
||||
<&camcc CAM_CC_CPAS_AHB_CLK>,
|
||||
<&camcc CAM_CC_CCI_2_CLK>;
|
||||
clock-names = "camnoc_axi",
|
||||
"cpas_ahb",
|
||||
"cci";
|
||||
|
||||
pinctrl-0 = <&cci2_0_default &cci2_1_default>;
|
||||
pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
cci2_i2c0: i2c-bus@0 {
|
||||
reg = <0>;
|
||||
clock-frequency = <1000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
cci2_i2c1: i2c-bus@1 {
|
||||
reg = <1>;
|
||||
clock-frequency = <1000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
cci3: cci@ac16000 {
|
||||
compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci";
|
||||
reg = <0x0 0x0ac16000 0x0 0x1000>;
|
||||
|
||||
interrupts = <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>;
|
||||
|
||||
power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
|
||||
|
||||
clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
|
||||
<&camcc CAM_CC_CPAS_AHB_CLK>,
|
||||
<&camcc CAM_CC_CCI_3_CLK>;
|
||||
clock-names = "camnoc_axi",
|
||||
"cpas_ahb",
|
||||
"cci";
|
||||
|
||||
pinctrl-0 = <&cci3_0_default &cci3_1_default>;
|
||||
pinctrl-1 = <&cci3_0_sleep &cci3_1_sleep>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
cci3_i2c0: i2c-bus@0 {
|
||||
reg = <0>;
|
||||
clock-frequency = <1000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
cci3_i2c1: i2c-bus@1 {
|
||||
reg = <1>;
|
||||
clock-frequency = <1000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
camss: isp@ac78000 {
|
||||
compatible = "qcom,sa8775p-camss";
|
||||
|
||||
reg = <0x0 0xac78000 0x0 0x1000>,
|
||||
<0x0 0xac7a000 0x0 0x0f00>,
|
||||
<0x0 0xac7c000 0x0 0x0f00>,
|
||||
<0x0 0xac84000 0x0 0x0f00>,
|
||||
<0x0 0xac88000 0x0 0x0f00>,
|
||||
<0x0 0xac8c000 0x0 0x0f00>,
|
||||
<0x0 0xac90000 0x0 0x0f00>,
|
||||
<0x0 0xac94000 0x0 0x0f00>,
|
||||
<0x0 0xac9c000 0x0 0x2000>,
|
||||
<0x0 0xac9e000 0x0 0x2000>,
|
||||
<0x0 0xaca0000 0x0 0x2000>,
|
||||
<0x0 0xaca2000 0x0 0x2000>,
|
||||
<0x0 0xacac000 0x0 0x0400>,
|
||||
<0x0 0xacad000 0x0 0x0400>,
|
||||
<0x0 0xacae000 0x0 0x0400>,
|
||||
<0x0 0xac4d000 0x0 0xd000>,
|
||||
<0x0 0xac5a000 0x0 0xd000>,
|
||||
<0x0 0xac85000 0x0 0x0d00>,
|
||||
<0x0 0xac89000 0x0 0x0d00>,
|
||||
<0x0 0xac8d000 0x0 0x0d00>,
|
||||
<0x0 0xac91000 0x0 0x0d00>,
|
||||
<0x0 0xac95000 0x0 0x0d00>;
|
||||
reg-names = "csid_wrapper",
|
||||
"csid0",
|
||||
"csid1",
|
||||
"csid_lite0",
|
||||
"csid_lite1",
|
||||
"csid_lite2",
|
||||
"csid_lite3",
|
||||
"csid_lite4",
|
||||
"csiphy0",
|
||||
"csiphy1",
|
||||
"csiphy2",
|
||||
"csiphy3",
|
||||
"tpg0",
|
||||
"tpg1",
|
||||
"tpg2",
|
||||
"vfe0",
|
||||
"vfe1",
|
||||
"vfe_lite0",
|
||||
"vfe_lite1",
|
||||
"vfe_lite2",
|
||||
"vfe_lite3",
|
||||
"vfe_lite4";
|
||||
|
||||
clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
|
||||
<&camcc CAM_CC_CORE_AHB_CLK>,
|
||||
<&camcc CAM_CC_CPAS_AHB_CLK>,
|
||||
<&camcc CAM_CC_CPAS_FAST_AHB_CLK>,
|
||||
<&camcc CAM_CC_CPAS_IFE_LITE_CLK>,
|
||||
<&camcc CAM_CC_CPAS_IFE_0_CLK>,
|
||||
<&camcc CAM_CC_CPAS_IFE_1_CLK>,
|
||||
<&camcc CAM_CC_CSID_CLK>,
|
||||
<&camcc CAM_CC_CSIPHY0_CLK>,
|
||||
<&camcc CAM_CC_CSI0PHYTIMER_CLK>,
|
||||
<&camcc CAM_CC_CSIPHY1_CLK>,
|
||||
<&camcc CAM_CC_CSI1PHYTIMER_CLK>,
|
||||
<&camcc CAM_CC_CSIPHY2_CLK>,
|
||||
<&camcc CAM_CC_CSI2PHYTIMER_CLK>,
|
||||
<&camcc CAM_CC_CSIPHY3_CLK>,
|
||||
<&camcc CAM_CC_CSI3PHYTIMER_CLK>,
|
||||
<&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
|
||||
<&gcc GCC_CAMERA_HF_AXI_CLK>,
|
||||
<&gcc GCC_CAMERA_SF_AXI_CLK>,
|
||||
<&camcc CAM_CC_ICP_AHB_CLK>,
|
||||
<&camcc CAM_CC_IFE_0_CLK>,
|
||||
<&camcc CAM_CC_IFE_0_FAST_AHB_CLK>,
|
||||
<&camcc CAM_CC_IFE_1_CLK>,
|
||||
<&camcc CAM_CC_IFE_1_FAST_AHB_CLK>,
|
||||
<&camcc CAM_CC_IFE_LITE_CLK>,
|
||||
<&camcc CAM_CC_IFE_LITE_AHB_CLK>,
|
||||
<&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
|
||||
<&camcc CAM_CC_IFE_LITE_CSID_CLK>;
|
||||
clock-names = "camnoc_axi",
|
||||
"core_ahb",
|
||||
"cpas_ahb",
|
||||
"cpas_fast_ahb_clk",
|
||||
"cpas_vfe_lite",
|
||||
"cpas_vfe0",
|
||||
"cpas_vfe1",
|
||||
"csid",
|
||||
"csiphy0",
|
||||
"csiphy0_timer",
|
||||
"csiphy1",
|
||||
"csiphy1_timer",
|
||||
"csiphy2",
|
||||
"csiphy2_timer",
|
||||
"csiphy3",
|
||||
"csiphy3_timer",
|
||||
"csiphy_rx",
|
||||
"gcc_axi_hf",
|
||||
"gcc_axi_sf",
|
||||
"icp_ahb",
|
||||
"vfe0",
|
||||
"vfe0_fast_ahb",
|
||||
"vfe1",
|
||||
"vfe1_fast_ahb",
|
||||
"vfe_lite",
|
||||
"vfe_lite_ahb",
|
||||
"vfe_lite_cphy_rx",
|
||||
"vfe_lite_csid";
|
||||
|
||||
interrupts = <GIC_SPI 565 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 564 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 759 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 758 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 604 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 545 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 546 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 547 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 360 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 761 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 760 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 605 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "csid0",
|
||||
"csid1",
|
||||
"csid_lite0",
|
||||
"csid_lite1",
|
||||
"csid_lite2",
|
||||
"csid_lite3",
|
||||
"csid_lite4",
|
||||
"csiphy0",
|
||||
"csiphy1",
|
||||
"csiphy2",
|
||||
"csiphy3",
|
||||
"tpg0",
|
||||
"tpg1",
|
||||
"tpg2",
|
||||
"vfe0",
|
||||
"vfe1",
|
||||
"vfe_lite0",
|
||||
"vfe_lite1",
|
||||
"vfe_lite2",
|
||||
"vfe_lite3",
|
||||
"vfe_lite4";
|
||||
|
||||
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
||||
&config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
|
||||
<&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "ahb",
|
||||
"hf_0";
|
||||
|
||||
iommus = <&apps_smmu 0x3400 0x20>;
|
||||
|
||||
power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
|
||||
power-domain-names = "top";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
camcc: clock-controller@ade0000 {
|
||||
compatible = "qcom,sa8775p-camcc";
|
||||
reg = <0x0 0x0ade0000 0x0 0x20000>;
|
||||
@@ -4695,7 +5070,11 @@ mdss0_dp0: displayport-controller@af54000 {
|
||||
<0x0 0x0af54200 0x0 0x0c0>,
|
||||
<0x0 0x0af55000 0x0 0x770>,
|
||||
<0x0 0x0af56000 0x0 0x09c>,
|
||||
<0x0 0x0af57000 0x0 0x09c>;
|
||||
<0x0 0x0af57000 0x0 0x09c>,
|
||||
<0x0 0x0af58000 0x0 0x09c>,
|
||||
<0x0 0x0af59000 0x0 0x09c>,
|
||||
<0x0 0x0af5a000 0x0 0x23c>,
|
||||
<0x0 0x0af5b000 0x0 0x23c>;
|
||||
|
||||
interrupt-parent = <&mdss0>;
|
||||
interrupts = <12>;
|
||||
@@ -4704,15 +5083,28 @@ mdss0_dp0: displayport-controller@af54000 {
|
||||
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
|
||||
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>,
|
||||
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
|
||||
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
|
||||
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
|
||||
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>,
|
||||
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>,
|
||||
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>;
|
||||
clock-names = "core_iface",
|
||||
"core_aux",
|
||||
"ctrl_link",
|
||||
"ctrl_link_iface",
|
||||
"stream_pixel";
|
||||
"stream_pixel",
|
||||
"stream_1_pixel",
|
||||
"stream_2_pixel",
|
||||
"stream_3_pixel";
|
||||
assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
|
||||
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
|
||||
assigned-clock-parents = <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>;
|
||||
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
|
||||
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>,
|
||||
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>,
|
||||
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>;
|
||||
assigned-clock-parents = <&mdss0_dp0_phy 0>,
|
||||
<&mdss0_dp0_phy 1>,
|
||||
<&mdss0_dp0_phy 1>,
|
||||
<&mdss0_dp0_phy 1>,
|
||||
<&mdss0_dp0_phy 1>;
|
||||
phys = <&mdss0_dp0_phy>;
|
||||
phy-names = "dp";
|
||||
|
||||
@@ -4774,7 +5166,11 @@ mdss0_dp1: displayport-controller@af5c000 {
|
||||
<0x0 0x0af5c200 0x0 0x0c0>,
|
||||
<0x0 0x0af5d000 0x0 0x770>,
|
||||
<0x0 0x0af5e000 0x0 0x09c>,
|
||||
<0x0 0x0af5f000 0x0 0x09c>;
|
||||
<0x0 0x0af5f000 0x0 0x09c>,
|
||||
<0x0 0x0af60000 0x0 0x09c>,
|
||||
<0x0 0x0af61000 0x0 0x09c>,
|
||||
<0x0 0x0af62000 0x0 0x23c>,
|
||||
<0x0 0x0af63000 0x0 0x23c>;
|
||||
|
||||
interrupt-parent = <&mdss0>;
|
||||
interrupts = <13>;
|
||||
@@ -4783,15 +5179,20 @@ mdss0_dp1: displayport-controller@af5c000 {
|
||||
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
|
||||
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>,
|
||||
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
|
||||
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
|
||||
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
|
||||
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK>;
|
||||
clock-names = "core_iface",
|
||||
"core_aux",
|
||||
"ctrl_link",
|
||||
"ctrl_link_iface",
|
||||
"stream_pixel";
|
||||
"stream_pixel",
|
||||
"stream_1_pixel";
|
||||
assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
|
||||
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
|
||||
assigned-clock-parents = <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>;
|
||||
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
|
||||
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
|
||||
assigned-clock-parents = <&mdss0_dp1_phy 0>,
|
||||
<&mdss0_dp1_phy 1>,
|
||||
<&mdss0_dp1_phy 1>;
|
||||
phys = <&mdss0_dp1_phy>;
|
||||
phy-names = "dp";
|
||||
|
||||
@@ -5031,6 +5432,118 @@ hs2_mi2s_active: hs2-mi2s-active-state {
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
cci0_0_default: cci0-0-default-state {
|
||||
pins = "gpio60", "gpio61";
|
||||
function = "cci_i2c";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up = <2200>;
|
||||
};
|
||||
|
||||
cci0_0_sleep: cci0-0-sleep-state {
|
||||
pins = "gpio60", "gpio61";
|
||||
function = "cci_i2c";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
cci0_1_default: cci0-1-default-state {
|
||||
pins = "gpio52", "gpio53";
|
||||
function = "cci_i2c";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up = <2200>;
|
||||
};
|
||||
|
||||
cci0_1_sleep: cci0-1-sleep-state {
|
||||
pins = "gpio52", "gpio53";
|
||||
function = "cci_i2c";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
cci1_0_default: cci1-0-default-state {
|
||||
pins = "gpio62", "gpio63";
|
||||
function = "cci_i2c";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up = <2200>;
|
||||
};
|
||||
|
||||
cci1_0_sleep: cci1-0-sleep-state {
|
||||
pins = "gpio62", "gpio63";
|
||||
function = "cci_i2c";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
cci1_1_default: cci1-1-default-state {
|
||||
pins = "gpio54", "gpio55";
|
||||
function = "cci_i2c";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up = <2200>;
|
||||
};
|
||||
|
||||
cci1_1_sleep: cci1-1-sleep-state {
|
||||
pins = "gpio54", "gpio55";
|
||||
function = "cci_i2c";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
cci2_0_default: cci2-0-default-state {
|
||||
pins = "gpio64", "gpio65";
|
||||
function = "cci_i2c";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up = <2200>;
|
||||
};
|
||||
|
||||
cci2_0_sleep: cci2-0-sleep-state {
|
||||
pins = "gpio64", "gpio65";
|
||||
function = "cci_i2c";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
cci2_1_default: cci2-1-default-state {
|
||||
pins = "gpio56", "gpio57";
|
||||
function = "cci_i2c";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up = <2200>;
|
||||
};
|
||||
|
||||
cci2_1_sleep: cci2-1-sleep-state {
|
||||
pins = "gpio56", "gpio57";
|
||||
function = "cci_i2c";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
cci3_0_default: cci3-0-default-state {
|
||||
pins = "gpio66", "gpio67";
|
||||
function = "cci_i2c";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up = <2200>;
|
||||
};
|
||||
|
||||
cci3_0_sleep: cci3-0-sleep-state {
|
||||
pins = "gpio66", "gpio67";
|
||||
function = "cci_i2c";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
cci3_1_default: cci3-1-default-state {
|
||||
pins = "gpio58", "gpio59";
|
||||
function = "cci_i2c";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up = <2200>;
|
||||
};
|
||||
|
||||
cci3_1_sleep: cci3-1-sleep-state {
|
||||
pins = "gpio58", "gpio59";
|
||||
function = "cci_i2c";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
qup_i2c0_default: qup-i2c0-state {
|
||||
pins = "gpio20", "gpio21";
|
||||
function = "qup0_se0";
|
||||
@@ -5658,6 +6171,46 @@ qup_uart21_rx: qup-uart21-rx-pins {
|
||||
function = "qup3_se0";
|
||||
};
|
||||
};
|
||||
|
||||
sdc_default: sdc-default-state {
|
||||
clk-pins {
|
||||
pins = "sdc1_clk";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
cmd-pins {
|
||||
pins = "sdc1_cmd";
|
||||
drive-strength = <10>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
data-pins {
|
||||
pins = "sdc1_data";
|
||||
drive-strength = <10>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
sdc_sleep: sdc-sleep-state {
|
||||
clk-pins {
|
||||
pins = "sdc1_clk";
|
||||
drive-strength = <2>;
|
||||
bias-bus-hold;
|
||||
};
|
||||
|
||||
cmd-pins {
|
||||
pins = "sdc1_cmd";
|
||||
drive-strength = <2>;
|
||||
bias-bus-hold;
|
||||
};
|
||||
|
||||
data-pins {
|
||||
pins = "sdc1_data";
|
||||
drive-strength = <2>;
|
||||
bias-bus-hold;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sram: sram@146d8000 {
|
||||
@@ -7782,6 +8335,9 @@ pcie0: pcie@1c00000 {
|
||||
phys = <&pcie0_phy>;
|
||||
phy-names = "pciephy";
|
||||
|
||||
eq-presets-8gts = /bits/ 16 <0x5555 0x5555>;
|
||||
eq-presets-16gts = /bits/ 8 <0x55 0x55>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
pcieport0: pcie@0 {
|
||||
@@ -7952,6 +8508,9 @@ pcie1: pcie@1c10000 {
|
||||
phys = <&pcie1_phy>;
|
||||
phy-names = "pciephy";
|
||||
|
||||
eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>;
|
||||
eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
pcie@0 {
|
||||
|
||||
@@ -309,6 +309,14 @@ &gpi_dma1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu_zap_shader {
|
||||
firmware-name = "qcom/qcs8300/a623_zap.mbn";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-0 = <&qup_i2c1_default>;
|
||||
pinctrl-names = "default";
|
||||
@@ -478,11 +486,9 @@ &ufs_mem_phy {
|
||||
};
|
||||
|
||||
&usb_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1_dwc3 {
|
||||
dr_mode = "peripheral";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1_hsphy {
|
||||
|
||||
@@ -1562,6 +1562,8 @@ mdss: display-subsystem@1a00000 {
|
||||
|
||||
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
resets = <&gcc GCC_MDSS_BCR>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
@@ -2125,6 +2127,7 @@ sdhc_1: mmc@7824900 {
|
||||
<&gcc GCC_SDCC1_APPS_CLK>,
|
||||
<&xo_board>;
|
||||
clock-names = "iface", "core", "xo";
|
||||
resets = <&gcc GCC_SDCC1_BCR>;
|
||||
pinctrl-0 = <&sdc1_default>;
|
||||
pinctrl-1 = <&sdc1_sleep>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
@@ -2146,6 +2149,7 @@ sdhc_2: mmc@7864900 {
|
||||
<&gcc GCC_SDCC2_APPS_CLK>,
|
||||
<&xo_board>;
|
||||
clock-names = "iface", "core", "xo";
|
||||
resets = <&gcc GCC_SDCC2_BCR>;
|
||||
pinctrl-0 = <&sdc2_default>;
|
||||
pinctrl-1 = <&sdc2_sleep>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
|
||||
@@ -1249,6 +1249,8 @@ mdss: display-subsystem@1a00000 {
|
||||
|
||||
power-domains = <&gcc MDSS_GDSC>;
|
||||
|
||||
resets = <&gcc GCC_MDSS_BCR>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
@@ -296,7 +296,7 @@ &sdhc_2 {
|
||||
vmmc-supply = <&pm8953_l11>;
|
||||
vqmmc-supply = <&pm8953_l12>;
|
||||
|
||||
cd-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>;
|
||||
cd-gpios = <&tlmm 133 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
|
||||
|
||||
@@ -566,6 +566,20 @@ qup_uart4_default: qup-uart4-default-state {
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
cci0_default: cci0-default-state {
|
||||
pins = "gpio22", "gpio23";
|
||||
function = "cci_i2c";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
cci1_default: cci1-default-state {
|
||||
pins = "gpio29", "gpio30";
|
||||
function = "cci_i2c";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
sdc1_state_on: sdc1-on-state {
|
||||
clk-pins {
|
||||
pins = "sdc1_clk";
|
||||
@@ -1635,6 +1649,42 @@ adreno_smmu: iommu@59a0000 {
|
||||
#iommu-cells = <2>;
|
||||
};
|
||||
|
||||
cci: cci@5c1b000 {
|
||||
compatible = "qcom,qcm2290-cci", "qcom,msm8996-cci";
|
||||
reg = <0x0 0x5c1b000 0x0 0x1000>;
|
||||
|
||||
interrupts = <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>;
|
||||
|
||||
clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, <&gcc GCC_CAMSS_CCI_0_CLK>;
|
||||
clock-names = "ahb", "cci";
|
||||
assigned-clocks = <&gcc GCC_CAMSS_CCI_0_CLK>;
|
||||
assigned-clock-rates = <37500000>;
|
||||
|
||||
power-domains = <&gcc GCC_CAMSS_TOP_GDSC>;
|
||||
|
||||
pinctrl-0 = <&cci0_default &cci1_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
cci_i2c0: i2c-bus@0 {
|
||||
reg = <0>;
|
||||
clock-frequency = <400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
cci_i2c1: i2c-bus@1 {
|
||||
reg = <1>;
|
||||
clock-frequency = <400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
camss: camss@5c6e000 {
|
||||
compatible = "qcom,qcm2290-camss";
|
||||
|
||||
|
||||
864
arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts
Normal file
864
arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts
Normal file
@@ -0,0 +1,864 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
|
||||
* Copyright (c) 2023, Luca Weiss <luca.weiss@fairphone.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
|
||||
#include <dt-bindings/iio/qcom,spmi-adc7-pm7325.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
|
||||
#include "sc7280.dtsi"
|
||||
#include "pm8350c.dtsi"
|
||||
#include "pmk8350.dtsi"
|
||||
|
||||
/delete-node/ &ipa_fw_mem;
|
||||
/delete-node/ &rmtfs_mem;
|
||||
/delete-node/ &xbl_mem;
|
||||
/delete-node/ &adsp_mem;
|
||||
/delete-node/ &cdsp_mem;
|
||||
/delete-node/ &wpss_mem;
|
||||
|
||||
/ {
|
||||
model = "Particle Tachyon";
|
||||
compatible = "particle,tachyon", "qcom,qcm6490";
|
||||
chassis-type = "embedded";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart5;
|
||||
serial1 = &uart12;
|
||||
serial2 = &uart7;
|
||||
serial3 = &uart8;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
pinctrl-0 = <&activity_led_state>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
led-activity {
|
||||
function = LED_FUNCTION_ACTIVITY;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
gpios = <&tlmm 14 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "on";
|
||||
panic-indicator;
|
||||
};
|
||||
};
|
||||
|
||||
pmic-glink {
|
||||
compatible = "qcom,qcm6490-pmic-glink", "qcom,pmic-glink";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
orientation-gpios = <&tlmm 140 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
connector@0 {
|
||||
compatible = "usb-c-connector";
|
||||
reg = <0>;
|
||||
power-role = "dual";
|
||||
data-role = "dual";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
pmic_glink_hs_in: endpoint {
|
||||
remote-endpoint = <&usb_1_dwc3_hs>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
pmic_glink_ss_in: endpoint {
|
||||
remote-endpoint = <&usb_dp_qmpphy_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
|
||||
pmic_glink_sbu_in: endpoint {
|
||||
remote-endpoint = <&usbdp_sbu_mux>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vreg_power_5v: regulator-power-5v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "power_5v";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&tlmm 13 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vph_pwr: regulator-vph-pwr {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vph_pwr";
|
||||
regulator-min-microvolt = <3700000>;
|
||||
regulator-max-microvolt = <3700000>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
xbl_mem: xbl@80700000 {
|
||||
reg = <0x0 0x80700000 0x0 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
tz_stat_mem: tz-stat@c0000000 {
|
||||
reg = <0x0 0xc0000000 0x0 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
tags_mem: tags@c0100000 {
|
||||
reg = <0x0 0xc0100000 0x0 0x1200000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
qtee_mem: qtee@c1300000 {
|
||||
reg = <0x0 0xc1300000 0x0 0x500000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
trusted_apps_mem: trusted-apps@c1800000 {
|
||||
reg = <0x0 0xc1800000 0x0 0x1c00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
debug_vm_mem: debug-vm@d0600000 {
|
||||
reg = <0x0 0xd0600000 0x0 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
adsp_mem: adsp@86100000 {
|
||||
reg = <0x0 0x86700000 0x0 0x2800000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
cdsp_mem: cdsp@88900000 {
|
||||
reg = <0x0 0x88f00000 0x0 0x1e00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
wpss_mem: wpss@9ae00000 {
|
||||
reg = <0x0 0x9ae00000 0x0 0x1900000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mpss_mem: mpss@8b800000 {
|
||||
reg = <0x0 0x8b800000 0x0 0xf600000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
ipa_fw_mem: ipa-fw@8b300000 {
|
||||
reg = <0x0 0x8b700000 0x0 0x10000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
ipa_gsi_mem: ipa-gsi@8b310000 {
|
||||
reg = <0x0 0x8b710000 0x0 0xa000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
rmtfs_mem: memory@f8500000 {
|
||||
compatible = "qcom,rmtfs-mem";
|
||||
reg = <0x0 0xf8500000 0x0 0x600000>;
|
||||
no-map;
|
||||
|
||||
qcom,client-id = <1>;
|
||||
qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>, <QCOM_SCM_VMID_NAV>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
usbdp-sbu-mux {
|
||||
compatible = "pericom,pi3usb102", "gpio-sbu-mux";
|
||||
|
||||
enable-gpios = <&tlmm 108 GPIO_ACTIVE_HIGH>;
|
||||
select-gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
pinctrl-0 = <&usbdp_sbu_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
mode-switch;
|
||||
orientation-switch;
|
||||
|
||||
port {
|
||||
usbdp_sbu_mux: endpoint {
|
||||
remote-endpoint = <&pmic_glink_sbu_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&apps_rsc {
|
||||
regulators-0 {
|
||||
compatible = "qcom,pm7325-rpmh-regulators";
|
||||
qcom,pmic-id = "b";
|
||||
|
||||
vdd-s1-supply = <&vph_pwr>;
|
||||
vdd-s2-supply = <&vph_pwr>;
|
||||
vdd-s3-supply = <&vph_pwr>;
|
||||
vdd-s4-supply = <&vph_pwr>;
|
||||
vdd-s5-supply = <&vph_pwr>;
|
||||
vdd-s6-supply = <&vph_pwr>;
|
||||
vdd-s7-supply = <&vph_pwr>;
|
||||
vdd-s8-supply = <&vph_pwr>;
|
||||
vdd-l1-l4-l12-l15-supply = <&vreg_s7b_0p972>;
|
||||
vdd-l2-l7-supply = <&vreg_bob_3p296>;
|
||||
vdd-l6-l9-l10-supply = <&vreg_s8b_1p272>;
|
||||
vdd-l8-supply = <&vreg_s7b_0p972>;
|
||||
vdd-l11-l17-l18-l19-supply = <&vreg_s1b_1p872>;
|
||||
vdd-l13-supply = <&vreg_s7b_0p972>;
|
||||
vdd-l14-l16-supply = <&vreg_s8b_1p272>;
|
||||
|
||||
vreg_s1b_1p872: smps1 {
|
||||
regulator-name = "vreg_s1b_1p872";
|
||||
regulator-min-microvolt = <1840000>;
|
||||
regulator-max-microvolt = <2040000>;
|
||||
};
|
||||
|
||||
vreg_s7b_0p972: smps7 {
|
||||
regulator-name = "vreg_s7b_0p972";
|
||||
regulator-min-microvolt = <535000>;
|
||||
regulator-max-microvolt = <1120000>;
|
||||
};
|
||||
|
||||
vreg_s8b_1p272: smps8 {
|
||||
regulator-name = "vreg_s8b_1p272";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_RET>;
|
||||
};
|
||||
|
||||
vreg_l1b_0p912: ldo1 {
|
||||
regulator-name = "vreg_l1b_0p912";
|
||||
regulator-min-microvolt = <825000>;
|
||||
regulator-max-microvolt = <925000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l2b_3p072: ldo2 {
|
||||
regulator-name = "vreg_l2b_3p072";
|
||||
regulator-min-microvolt = <2700000>;
|
||||
regulator-max-microvolt = <3544000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l3b_0p504: ldo3 {
|
||||
regulator-name = "vreg_l3b_0p504";
|
||||
regulator-min-microvolt = <312000>;
|
||||
regulator-max-microvolt = <910000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l6b_1p2: ldo6 {
|
||||
regulator-name = "vreg_l6b_1p2";
|
||||
regulator-min-microvolt = <1140000>;
|
||||
regulator-max-microvolt = <1260000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l7b_2p952: ldo7 {
|
||||
regulator-name = "vreg_l7b_2p952";
|
||||
regulator-min-microvolt = <2952000>;
|
||||
regulator-max-microvolt = <2952000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l8b_0p904: ldo8 {
|
||||
regulator-name = "vreg_l8b_0p904";
|
||||
regulator-min-microvolt = <870000>;
|
||||
regulator-max-microvolt = <970000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l9b_1p2: ldo9 {
|
||||
regulator-name = "vreg_l9b_1p2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
regulator-allow-set-load;
|
||||
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l11b_1p504: ldo11 {
|
||||
regulator-name = "vreg_l11b_1p504";
|
||||
regulator-min-microvolt = <1504000>;
|
||||
regulator-max-microvolt = <2000000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l12b_0p751: ldo12 {
|
||||
regulator-name = "vreg_l12b_0p751";
|
||||
regulator-min-microvolt = <751000>;
|
||||
regulator-max-microvolt = <824000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l13b_0p53: ldo13 {
|
||||
regulator-name = "vreg_l13b_0p53";
|
||||
regulator-min-microvolt = <530000>;
|
||||
regulator-max-microvolt = <824000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l14b_1p08: ldo14 {
|
||||
regulator-name = "vreg_l14b_1p08";
|
||||
regulator-min-microvolt = <1080000>;
|
||||
regulator-max-microvolt = <1304000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l15b_0p765: ldo15 {
|
||||
regulator-name = "vreg_l15b_0p765";
|
||||
regulator-min-microvolt = <765000>;
|
||||
regulator-max-microvolt = <1020000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l16b_1p1: ldo16 {
|
||||
regulator-name = "vreg_l16b_1p1";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l17b_1p7: ldo17 {
|
||||
regulator-name = "vreg_l17b_1p7";
|
||||
regulator-min-microvolt = <1700000>;
|
||||
regulator-max-microvolt = <1900000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l18b_1p8: ldo18 {
|
||||
regulator-name = "vreg_l18b_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2000000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l19b_1p8: ldo19 {
|
||||
regulator-name = "vreg_l19b_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2000000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators-1 {
|
||||
compatible = "qcom,pm8350c-rpmh-regulators";
|
||||
qcom,pmic-id = "c";
|
||||
|
||||
vdd-s1-supply = <&vph_pwr>;
|
||||
vdd-s2-supply = <&vph_pwr>;
|
||||
vdd-s3-supply = <&vph_pwr>;
|
||||
vdd-s4-supply = <&vph_pwr>;
|
||||
vdd-s5-supply = <&vph_pwr>;
|
||||
vdd-s6-supply = <&vph_pwr>;
|
||||
vdd-s7-supply = <&vph_pwr>;
|
||||
vdd-s8-supply = <&vph_pwr>;
|
||||
vdd-s9-supply = <&vph_pwr>;
|
||||
vdd-s10-supply = <&vph_pwr>;
|
||||
vdd-l1-l12-supply = <&vreg_s1b_1p872>;
|
||||
vdd-l2-l8-supply = <&vreg_s1b_1p872>;
|
||||
vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob_3p296>;
|
||||
vdd-l6-l9-l11-supply = <&vreg_bob_3p296>;
|
||||
vdd-l10-supply = <&vreg_s7b_0p972>;
|
||||
vdd-bob-supply = <&vph_pwr>;
|
||||
|
||||
vreg_s1c_2p19: smps1 {
|
||||
regulator-name = "vreg_s1c_2p19";
|
||||
regulator-min-microvolt = <2190000>;
|
||||
regulator-max-microvolt = <2210000>;
|
||||
};
|
||||
|
||||
vreg_s9c_1p084: smps9 {
|
||||
regulator-name = "vreg_s9c_1p084";
|
||||
regulator-min-microvolt = <1084000>;
|
||||
regulator-max-microvolt = <1170000>;
|
||||
};
|
||||
|
||||
vreg_l1c_1p8: ldo1 {
|
||||
regulator-name = "vreg_l1c_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1980000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l2c_1p62: ldo2 {
|
||||
regulator-name = "vreg_l2c_1p62";
|
||||
regulator-min-microvolt = <1620000>;
|
||||
regulator-max-microvolt = <1980000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l3c_2p8: ldo3 {
|
||||
regulator-name = "vreg_l3c_2p8";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <3540000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l4c_1p62: ldo4 {
|
||||
regulator-name = "vreg_l4c_1p62";
|
||||
regulator-min-microvolt = <1620000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l5c_1p62: ldo5 {
|
||||
regulator-name = "vreg_l5c_1p62";
|
||||
regulator-min-microvolt = <1620000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l6c_2p96: ldo6 {
|
||||
regulator-name = "vreg_l6c_2p96";
|
||||
regulator-min-microvolt = <1650000>;
|
||||
regulator-max-microvolt = <3544000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l7c_3p0: ldo7 {
|
||||
regulator-name = "vreg_l7c_3p0";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3544000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l8c_1p62: ldo8 {
|
||||
regulator-name = "vreg_l8c_1p62";
|
||||
regulator-min-microvolt = <1620000>;
|
||||
regulator-max-microvolt = <2000000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l9c_2p96: ldo9 {
|
||||
regulator-name = "vreg_l9c_2p96";
|
||||
regulator-min-microvolt = <2960000>;
|
||||
regulator-max-microvolt = <3544000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l10c_0p88: ldo10 {
|
||||
regulator-name = "vreg_l10c_0p88";
|
||||
regulator-min-microvolt = <720000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l11c_2p8: ldo11 {
|
||||
regulator-name = "vreg_l11c_2p8";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <3544000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l12c_1p65: ldo12 {
|
||||
regulator-name = "vreg_l12c_1p65";
|
||||
regulator-min-microvolt = <1650000>;
|
||||
regulator-max-microvolt = <2000000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l13c_2p7: ldo13 {
|
||||
regulator-name = "vreg_l13c_2p7";
|
||||
regulator-min-microvolt = <2700000>;
|
||||
regulator-max-microvolt = <3544000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_bob_3p296: bob {
|
||||
regulator-name = "vreg_bob_3p296";
|
||||
regulator-min-microvolt = <3008000>;
|
||||
regulator-max-microvolt = <3960000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <100000>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ipa {
|
||||
firmware-name = "qcom/qcm6490/particle/tachyon/ipa_fws.mbn";
|
||||
qcom,gsi-loader = "self";
|
||||
memory-region = <&ipa_fw_mem>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gcc {
|
||||
protected-clocks = <GCC_CFG_NOC_LPASS_CLK>,
|
||||
<GCC_MSS_CFG_AHB_CLK>,
|
||||
<GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC>,
|
||||
<GCC_MSS_OFFLINE_AXI_CLK>,
|
||||
<GCC_MSS_Q6SS_BOOT_CLK_SRC>,
|
||||
<GCC_MSS_Q6_MEMNOC_AXI_CLK>,
|
||||
<GCC_MSS_SNOC_AXI_CLK>,
|
||||
<GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
|
||||
<GCC_QSPI_CORE_CLK>,
|
||||
<GCC_QSPI_CORE_CLK_SRC>,
|
||||
<GCC_SEC_CTRL_CLK_SRC>,
|
||||
<GCC_WPSS_AHB_BDG_MST_CLK>,
|
||||
<GCC_WPSS_AHB_CLK>,
|
||||
<GCC_WPSS_RSCP_CLK>;
|
||||
};
|
||||
|
||||
&gpu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu_zap_shader {
|
||||
firmware-name = "qcom/qcm6490/particle/tachyon/a660_zap.mbn";
|
||||
};
|
||||
|
||||
&mdss {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss_dp {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss_dp_out {
|
||||
data-lanes = <0 1>;
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
pinctrl-0 = <&pcie0_reset_n>, <&pcie0_wake_n>, <&pcie0_clkreq_n>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0_phy {
|
||||
vdda-phy-supply = <&vreg_l10c_0p88>;
|
||||
vdda-pll-supply = <&vreg_l6b_1p2>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie1 {
|
||||
perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
|
||||
|
||||
pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>, <&pcie1_clkreq_n>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
vddpe-3v3-supply = <&vreg_power_5v>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie1_phy {
|
||||
vdda-phy-supply = <&vreg_l10c_0p88>;
|
||||
vdda-pll-supply = <&vreg_l6b_1p2>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pmk8350_adc_tm {
|
||||
status = "okay";
|
||||
|
||||
xo-therm@0 {
|
||||
reg = <0>;
|
||||
io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>;
|
||||
qcom,ratiometric;
|
||||
qcom,hw-settle-time-us = <200>;
|
||||
};
|
||||
};
|
||||
|
||||
&pmk8350_rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pmk8350_vadc {
|
||||
status = "okay";
|
||||
|
||||
channel@44 {
|
||||
reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>;
|
||||
qcom,ratiometric;
|
||||
qcom,hw-settle-time = <200>;
|
||||
qcom,pre-scaling = <1 1>;
|
||||
label = "pmk8350_xo_therm";
|
||||
};
|
||||
};
|
||||
|
||||
&pon_pwrkey {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qupv3_id_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qupv3_id_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&remoteproc_adsp {
|
||||
firmware-name = "qcom/qcm6490/particle/tachyon/adsp.mbn";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&remoteproc_cdsp {
|
||||
firmware-name = "qcom/qcm6490/particle/tachyon/cdsp.mbn";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&remoteproc_mpss {
|
||||
firmware-name = "qcom/qcm6490/particle/tachyon/modem.mbn";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdc2_clk {
|
||||
bias-disable;
|
||||
drive-strength = <16>;
|
||||
};
|
||||
|
||||
&sdc2_cmd {
|
||||
bias-pull-up;
|
||||
drive-strength = <10>;
|
||||
};
|
||||
|
||||
&sdc2_data {
|
||||
bias-pull-up;
|
||||
drive-strength = <10>;
|
||||
};
|
||||
|
||||
&sdhc_2 {
|
||||
vmmc-supply = <&vreg_l9c_2p96>;
|
||||
vqmmc-supply = <&vreg_l6c_2p96>;
|
||||
|
||||
cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
activity_led_state: activity-led-state {
|
||||
pins = "gpio14";
|
||||
function = "gpio";
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
bt_en_state: bt-default-state {
|
||||
pins = "gpio84";
|
||||
function = "gpio";
|
||||
drive-strength = <16>;
|
||||
output-low;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
pcie0_reset_n: pcie0-reset-n-state {
|
||||
pins = "gpio87";
|
||||
function = "gpio";
|
||||
drive-strength = <16>;
|
||||
output-low;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pcie0_wake_n: pcie0-wake-n-state {
|
||||
pins = "gpio89";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
pcie1_reset_n: pcie1-reset-n-state {
|
||||
pins = "gpio2";
|
||||
function = "gpio";
|
||||
drive-strength = <16>;
|
||||
output-low;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pcie1_wake_n: pcie1-wake-n-state {
|
||||
pins = "gpio3";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
qup_uart7_sleep_cts: qup-uart7-sleep-cts-state {
|
||||
pins = "gpio28";
|
||||
function = "gpio";
|
||||
/*
|
||||
* Configure a bias-bus-hold on CTS to lower power
|
||||
* usage when Bluetooth is turned off. Bus hold will
|
||||
* maintain a low power state regardless of whether
|
||||
* the Bluetooth module drives the pin in either
|
||||
* direction or leaves the pin fully unpowered.
|
||||
*/
|
||||
bias-bus-hold;
|
||||
};
|
||||
|
||||
qup_uart7_sleep_rts: qup-uart7-sleep-rts-state {
|
||||
pins = "gpio29";
|
||||
function = "gpio";
|
||||
/*
|
||||
* Configure pull-down on RTS. As RTS is active low
|
||||
* signal, pull it low to indicate the BT SoC that it
|
||||
* can wakeup the system anytime from suspend state by
|
||||
* pulling RX low (by sending wakeup bytes).
|
||||
*/
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
qup_uart7_sleep_tx: qup-uart7-sleep-tx-state {
|
||||
pins = "gpio30";
|
||||
function = "gpio";
|
||||
/*
|
||||
* Configure pull-up on TX when it isn't actively driven
|
||||
* to prevent BT SoC from receiving garbage during sleep.
|
||||
*/
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
qup_uart7_sleep_rx: qup-uart7-sleep-rx-state {
|
||||
pins = "gpio31";
|
||||
function = "gpio";
|
||||
/*
|
||||
* Configure a pull-up on RX. This is needed to avoid
|
||||
* garbage data when the TX pin of the Bluetooth module
|
||||
* is floating which may cause spurious wakeups.
|
||||
*/
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
usbdp_sbu_default: usbdp-sbu-state {
|
||||
oe-n-pins {
|
||||
pins = "gpio108";
|
||||
function = "gpio";
|
||||
bias-disable;
|
||||
drive-strength = <16>;
|
||||
output-high;
|
||||
};
|
||||
|
||||
sel-pins {
|
||||
pins = "gpio42";
|
||||
function = "gpio";
|
||||
bias-disable;
|
||||
drive-strength = <16>;
|
||||
};
|
||||
};
|
||||
|
||||
wlan_en_state: wlan-default-state {
|
||||
pins = "gpio85";
|
||||
function = "gpio";
|
||||
drive-strength = <16>;
|
||||
output-low;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
&uart5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart7 {
|
||||
/delete-property/ interrupts;
|
||||
interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&tlmm 31 IRQ_TYPE_EDGE_FALLING>;
|
||||
|
||||
pinctrl-1 = <&qup_uart7_sleep_cts>,
|
||||
<&qup_uart7_sleep_rts>,
|
||||
<&qup_uart7_sleep_tx>,
|
||||
<&qup_uart7_sleep_rx>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart8 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart12 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ufs_mem_hc {
|
||||
reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
|
||||
vcc-supply = <&vreg_l7b_2p952>;
|
||||
vcc-max-microamp = <800000>;
|
||||
vccq-supply = <&vreg_l9b_1p2>;
|
||||
vccq-max-microamp = <900000>;
|
||||
vccq2-supply = <&vreg_l9b_1p2>;
|
||||
vccq2-max-microamp = <900000>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ufs_mem_phy {
|
||||
vdda-phy-supply = <&vreg_l10c_0p88>;
|
||||
vdda-pll-supply = <&vreg_l6b_1p2>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1 {
|
||||
dr_mode = "otg";
|
||||
usb-role-switch;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1_dwc3_hs {
|
||||
remote-endpoint = <&pmic_glink_hs_in>;
|
||||
};
|
||||
|
||||
&usb_1_hsphy {
|
||||
vdda-pll-supply = <&vreg_l10c_0p88>;
|
||||
vdda33-supply = <&vreg_l2b_3p072>;
|
||||
vdda18-supply = <&vreg_l1c_1p8>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1_qmpphy {
|
||||
vdda-phy-supply = <&vreg_l6b_1p2>;
|
||||
vdda-pll-supply = <&vreg_l1b_0p912>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_2 {
|
||||
dr_mode = "host";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_2_hsphy {
|
||||
vdda-pll-supply = <&vreg_l10c_0p88>;
|
||||
vdda18-supply = <&vreg_l1c_1p8>;
|
||||
vdda33-supply = <&vreg_l2b_3p072>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_dp_qmpphy_out {
|
||||
remote-endpoint = <&pmic_glink_ss_in>;
|
||||
};
|
||||
@@ -296,6 +296,14 @@ queue3 {
|
||||
};
|
||||
};
|
||||
|
||||
&gpu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu_zap_shader {
|
||||
firmware-name = "qcom/qcs8300/a623_zap.mbn";
|
||||
};
|
||||
|
||||
&pmm8650au_1_gpios {
|
||||
usb2_en: usb2-en-state {
|
||||
pins = "gpio7";
|
||||
@@ -414,17 +422,13 @@ &usb_qmpphy {
|
||||
};
|
||||
|
||||
&usb_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1_dwc3 {
|
||||
dr_mode = "peripheral";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_2 {
|
||||
dr_mode = "host";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_2_dwc3 {
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
@@ -924,9 +924,14 @@ ipcc: mailbox@408000 {
|
||||
|
||||
qfprom: efuse@784000 {
|
||||
compatible = "qcom,qcs8300-qfprom", "qcom,qfprom";
|
||||
reg = <0x0 0x00784000 0x0 0x1200>;
|
||||
reg = <0x0 0x00784000 0x0 0x2410>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
gpu_speed_bin: gpu_speed_bin@240c {
|
||||
reg = <0x240c 0x1>;
|
||||
bits = <0 8>;
|
||||
};
|
||||
};
|
||||
|
||||
gpi_dma0: dma-controller@900000 {
|
||||
@@ -4289,6 +4294,104 @@ serdes0: phy@8909000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpu: gpu@3d00000 {
|
||||
compatible = "qcom,adreno-623.0", "qcom,adreno";
|
||||
reg = <0x0 0x03d00000 0x0 0x40000>,
|
||||
<0x0 0x03d9e000 0x0 0x1000>,
|
||||
<0x0 0x03d61000 0x0 0x800>;
|
||||
reg-names = "kgsl_3d0_reg_memory",
|
||||
"cx_mem",
|
||||
"cx_dbgc";
|
||||
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
|
||||
iommus = <&adreno_smmu 0 0xc00>,
|
||||
<&adreno_smmu 1 0xc00>;
|
||||
operating-points-v2 = <&gpu_opp_table>;
|
||||
qcom,gmu = <&gmu>;
|
||||
interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "gfx-mem";
|
||||
#cooling-cells = <2>;
|
||||
|
||||
nvmem-cells = <&gpu_speed_bin>;
|
||||
nvmem-cell-names = "speed_bin";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
gpu_zap_shader: zap-shader {
|
||||
memory-region = <&gpu_microcode_mem>;
|
||||
};
|
||||
|
||||
gpu_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-877000000 {
|
||||
opp-hz = /bits/ 64 <877000000>;
|
||||
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
||||
opp-peak-kBps = <12484375>;
|
||||
opp-supported-hw = <0x1>;
|
||||
};
|
||||
|
||||
opp-780000000 {
|
||||
opp-hz = /bits/ 64 <780000000>;
|
||||
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
opp-peak-kBps = <10687500>;
|
||||
opp-supported-hw = <0x1>;
|
||||
};
|
||||
|
||||
opp-599000000 {
|
||||
opp-hz = /bits/ 64 <599000000>;
|
||||
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
|
||||
opp-peak-kBps = <8171875>;
|
||||
opp-supported-hw = <0x3>;
|
||||
};
|
||||
|
||||
opp-479000000 {
|
||||
opp-hz = /bits/ 64 <479000000>;
|
||||
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
||||
opp-peak-kBps = <5285156>;
|
||||
opp-supported-hw = <0x3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gmu: gmu@3d6a000 {
|
||||
compatible = "qcom,adreno-gmu-623.0", "qcom,adreno-gmu";
|
||||
reg = <0x0 0x03d6a000 0x0 0x34000>,
|
||||
<0x0 0x03de0000 0x0 0x10000>,
|
||||
<0x0 0x0b290000 0x0 0x10000>;
|
||||
reg-names = "gmu", "rscc", "gmu_pdc";
|
||||
interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "hfi", "gmu";
|
||||
clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
|
||||
<&gpucc GPU_CC_CXO_CLK>,
|
||||
<&gcc GCC_DDRSS_GPU_AXI_CLK>,
|
||||
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
||||
<&gpucc GPU_CC_AHB_CLK>,
|
||||
<&gpucc GPU_CC_HUB_CX_INT_CLK>;
|
||||
clock-names = "gmu",
|
||||
"cxo",
|
||||
"axi",
|
||||
"memnoc",
|
||||
"ahb",
|
||||
"hub";
|
||||
power-domains = <&gpucc GPU_CC_CX_GDSC>,
|
||||
<&gpucc GPU_CC_GX_GDSC>;
|
||||
power-domain-names = "cx",
|
||||
"gx";
|
||||
iommus = <&adreno_smmu 5 0xc00>;
|
||||
operating-points-v2 = <&gmu_opp_table>;
|
||||
|
||||
gmu_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-500000000 {
|
||||
opp-hz = /bits/ 64 <500000000>;
|
||||
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpucc: clock-controller@3d90000 {
|
||||
compatible = "qcom,qcs8300-gpucc";
|
||||
reg = <0x0 0x03d90000 0x0 0xa000>;
|
||||
@@ -4467,9 +4570,9 @@ llcc: system-cache-controller@9200000 {
|
||||
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
usb_1: usb@a6f8800 {
|
||||
compatible = "qcom,qcs8300-dwc3", "qcom,dwc3";
|
||||
reg = <0x0 0x0a6f8800 0x0 0x400>;
|
||||
usb_1: usb@a600000 {
|
||||
compatible = "qcom,qcs8300-dwc3", "qcom,snps-dwc3";
|
||||
reg = <0x0 0x0a600000 0x0 0xfc100>;
|
||||
|
||||
clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
|
||||
<&gcc GCC_USB30_PRIM_MASTER_CLK>,
|
||||
@@ -4486,12 +4589,14 @@ usb_1: usb@a6f8800 {
|
||||
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
|
||||
assigned-clock-rates = <19200000>, <200000000>;
|
||||
|
||||
interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
|
||||
interrupts-extended = <&intc GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 14 IRQ_TYPE_EDGE_BOTH>,
|
||||
<&pdc 15 IRQ_TYPE_EDGE_BOTH>,
|
||||
<&pdc 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "pwr_event",
|
||||
interrupt-names = "dwc_usb3",
|
||||
"pwr_event",
|
||||
"hs_phy_irq",
|
||||
"dp_hs_phy_irq",
|
||||
"dm_hs_phy_irq",
|
||||
@@ -4507,32 +4612,23 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
|
||||
&config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "usb-ddr", "apps-usb";
|
||||
|
||||
iommus = <&apps_smmu 0x80 0x0>;
|
||||
phys = <&usb_1_hsphy>, <&usb_qmpphy>;
|
||||
phy-names = "usb2-phy", "usb3-phy";
|
||||
snps,dis_enblslpm_quirk;
|
||||
snps,dis-u1-entry-quirk;
|
||||
snps,dis-u2-entry-quirk;
|
||||
snps,dis_u2_susphy_quirk;
|
||||
snps,dis_u3_susphy_quirk;
|
||||
|
||||
wakeup-source;
|
||||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
usb_1_dwc3: usb@a600000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x0 0x0a600000 0x0 0xe000>;
|
||||
interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
|
||||
iommus = <&apps_smmu 0x80 0x0>;
|
||||
phys = <&usb_1_hsphy>, <&usb_qmpphy>;
|
||||
phy-names = "usb2-phy", "usb3-phy";
|
||||
snps,dis_enblslpm_quirk;
|
||||
snps,dis-u1-entry-quirk;
|
||||
snps,dis-u2-entry-quirk;
|
||||
snps,dis_u2_susphy_quirk;
|
||||
snps,dis_u3_susphy_quirk;
|
||||
};
|
||||
};
|
||||
|
||||
usb_2: usb@a4f8800 {
|
||||
compatible = "qcom,qcs8300-dwc3", "qcom,dwc3";
|
||||
reg = <0x0 0x0a4f8800 0x0 0x400>;
|
||||
usb_2: usb@a400000 {
|
||||
compatible = "qcom,qcs8300-dwc3", "qcom,snps-dwc3";
|
||||
reg = <0x0 0x0a400000 0x0 0xfc100>;
|
||||
|
||||
clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
|
||||
<&gcc GCC_USB20_MASTER_CLK>,
|
||||
@@ -4549,11 +4645,13 @@ usb_2: usb@a4f8800 {
|
||||
<&gcc GCC_USB20_MASTER_CLK>;
|
||||
assigned-clock-rates = <19200000>, <120000000>;
|
||||
|
||||
interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
|
||||
interrupts-extended = <&intc GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 10 IRQ_TYPE_EDGE_BOTH>,
|
||||
<&pdc 9 IRQ_TYPE_EDGE_BOTH>;
|
||||
interrupt-names = "pwr_event",
|
||||
interrupt-names = "dwc_usb3",
|
||||
"pwr_event",
|
||||
"hs_phy_irq",
|
||||
"dp_hs_phy_irq",
|
||||
"dm_hs_phy_irq";
|
||||
@@ -4569,32 +4667,22 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
|
||||
&config_noc SLAVE_USB2 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "usb-ddr", "apps-usb";
|
||||
|
||||
iommus = <&apps_smmu 0x20 0x0>;
|
||||
|
||||
phys = <&usb_2_hsphy>;
|
||||
phy-names = "usb2-phy";
|
||||
maximum-speed = "high-speed";
|
||||
|
||||
snps,dis-u1-entry-quirk;
|
||||
snps,dis-u2-entry-quirk;
|
||||
snps,dis_u2_susphy_quirk;
|
||||
snps,dis_u3_susphy_quirk;
|
||||
snps,dis_enblslpm_quirk;
|
||||
|
||||
qcom,select-utmi-as-pipe-clk;
|
||||
wakeup-source;
|
||||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
usb_2_dwc3: usb@a400000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x0 0x0a400000 0x0 0xe000>;
|
||||
|
||||
interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
|
||||
iommus = <&apps_smmu 0x20 0x0>;
|
||||
|
||||
phys = <&usb_2_hsphy>;
|
||||
phy-names = "usb2-phy";
|
||||
maximum-speed = "high-speed";
|
||||
|
||||
snps,dis-u1-entry-quirk;
|
||||
snps,dis-u2-entry-quirk;
|
||||
snps,dis_u2_susphy_quirk;
|
||||
snps,dis_u3_susphy_quirk;
|
||||
snps,dis_enblslpm_quirk;
|
||||
};
|
||||
};
|
||||
|
||||
iris: video-codec@aa00000 {
|
||||
|
||||
@@ -2144,16 +2144,20 @@ mdss_dp0: displayport-controller@ae90000 {
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
|
||||
clock-names = "core_iface",
|
||||
"core_aux",
|
||||
"ctrl_link",
|
||||
"ctrl_link_iface",
|
||||
"stream_pixel";
|
||||
"stream_pixel",
|
||||
"stream_1_pixel";
|
||||
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
|
||||
assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
|
||||
<&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
|
||||
<&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
|
||||
|
||||
phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
|
||||
|
||||
@@ -5144,7 +5144,8 @@ mdss_edp: edp@aea0000 {
|
||||
reg = <0 0x0aea0000 0 0x200>,
|
||||
<0 0x0aea0200 0 0x200>,
|
||||
<0 0x0aea0400 0 0xc00>,
|
||||
<0 0x0aea1000 0 0x400>;
|
||||
<0 0x0aea1000 0 0x400>,
|
||||
<0 0x0aea1400 0 0x400>;
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <14>;
|
||||
|
||||
@@ -3256,16 +3256,20 @@ mdss_dp0: displayport-controller@ae90000 {
|
||||
<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
|
||||
clock-names = "core_iface",
|
||||
"core_aux",
|
||||
"ctrl_link",
|
||||
"ctrl_link_iface",
|
||||
"stream_pixel";
|
||||
"stream_pixel",
|
||||
"stream_1_pixel";
|
||||
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
|
||||
assigned-clock-parents = <&usb_prim_qmpphy QMP_USB43DP_DP_LINK_CLK>,
|
||||
<&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
|
||||
<&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
|
||||
|
||||
phys = <&usb_prim_qmpphy QMP_USB43DP_DP_PHY>;
|
||||
@@ -3334,16 +3338,20 @@ mdss_dp1: displayport-controller@ae98000 {
|
||||
<&dispcc DISP_CC_MDSS_DP_AUX1_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DP_LINK1_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DP_LINK1_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>;
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
|
||||
clock-names = "core_iface",
|
||||
"core_aux",
|
||||
"ctrl_link",
|
||||
"ctrl_link_iface",
|
||||
"stream_pixel";
|
||||
"stream_pixel",
|
||||
"stream_1_pixel";
|
||||
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>;
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
|
||||
assigned-clock-parents = <&usb_sec_qmpphy QMP_USB43DP_DP_LINK_CLK>,
|
||||
<&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
|
||||
<&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
|
||||
|
||||
phys = <&usb_sec_qmpphy QMP_USB43DP_DP_PHY>;
|
||||
@@ -3404,7 +3412,8 @@ mdss_edp: displayport-controller@ae9a000 {
|
||||
reg = <0 0xae9a000 0 0x200>,
|
||||
<0 0xae9a200 0 0x200>,
|
||||
<0 0xae9a400 0 0x600>,
|
||||
<0 0xae9aa00 0 0x400>;
|
||||
<0 0xae9aa00 0 0x400>,
|
||||
<0 0xae9b000 0 0x400>;
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <14>;
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
|
||||
@@ -4706,15 +4706,19 @@ mdss0_dp0: displayport-controller@ae90000 {
|
||||
<&dispcc0 DISP_CC_MDSS_DPTX0_AUX_CLK>,
|
||||
<&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK>,
|
||||
<&dispcc0 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
|
||||
<&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
|
||||
<&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
|
||||
<&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
|
||||
clock-names = "core_iface", "core_aux",
|
||||
"ctrl_link",
|
||||
"ctrl_link_iface",
|
||||
"stream_pixel";
|
||||
"stream_pixel",
|
||||
"stream_1_pixel";
|
||||
|
||||
assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
|
||||
<&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
|
||||
<&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
|
||||
<&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
|
||||
assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
|
||||
<&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
|
||||
<&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
|
||||
|
||||
phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>;
|
||||
@@ -4785,14 +4789,18 @@ mdss0_dp1: displayport-controller@ae98000 {
|
||||
<&dispcc0 DISP_CC_MDSS_DPTX1_AUX_CLK>,
|
||||
<&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK>,
|
||||
<&dispcc0 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
|
||||
<&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
|
||||
<&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
|
||||
<&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL1_CLK>;
|
||||
clock-names = "core_iface", "core_aux",
|
||||
"ctrl_link",
|
||||
"ctrl_link_iface", "stream_pixel";
|
||||
"ctrl_link_iface", "stream_pixel",
|
||||
"stream_1_pixel";
|
||||
|
||||
assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
|
||||
<&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
|
||||
<&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
|
||||
<&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
|
||||
assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
|
||||
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
|
||||
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
|
||||
|
||||
phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
|
||||
@@ -4862,10 +4870,12 @@ mdss0_dp2: displayport-controller@ae9a000 {
|
||||
<&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>,
|
||||
<&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>,
|
||||
<&dispcc0 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
|
||||
<&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
|
||||
<&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>,
|
||||
<&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL1_CLK>;
|
||||
clock-names = "core_iface", "core_aux",
|
||||
"ctrl_link",
|
||||
"ctrl_link_iface", "stream_pixel";
|
||||
"ctrl_link_iface", "stream_pixel",
|
||||
"stream_1_pixel";
|
||||
interrupt-parent = <&mdss0>;
|
||||
interrupts = <14>;
|
||||
phys = <&mdss0_dp2_phy>;
|
||||
@@ -4873,8 +4883,11 @@ mdss0_dp2: displayport-controller@ae9a000 {
|
||||
power-domains = <&rpmhpd SC8280XP_MMCX>;
|
||||
|
||||
assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
|
||||
<&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
|
||||
assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>;
|
||||
<&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>,
|
||||
<&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>;
|
||||
assigned-clock-parents = <&mdss0_dp2_phy 0>,
|
||||
<&mdss0_dp2_phy 1>,
|
||||
<&mdss0_dp2_phy 1>;
|
||||
operating-points-v2 = <&mdss0_dp2_opp_table>;
|
||||
|
||||
#sound-dai-cells = <0>;
|
||||
@@ -6043,10 +6056,12 @@ mdss1_dp0: displayport-controller@22090000 {
|
||||
<&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>,
|
||||
<&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK>,
|
||||
<&dispcc1 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
|
||||
<&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
|
||||
<&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
|
||||
<&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
|
||||
clock-names = "core_iface", "core_aux",
|
||||
"ctrl_link",
|
||||
"ctrl_link_iface", "stream_pixel";
|
||||
"ctrl_link_iface", "stream_pixel",
|
||||
"stream_1_pixel";
|
||||
interrupt-parent = <&mdss1>;
|
||||
interrupts = <12>;
|
||||
phys = <&mdss1_dp0_phy>;
|
||||
@@ -6054,8 +6069,11 @@ mdss1_dp0: displayport-controller@22090000 {
|
||||
power-domains = <&rpmhpd SC8280XP_MMCX>;
|
||||
|
||||
assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
|
||||
<&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
|
||||
assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>;
|
||||
<&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
|
||||
<&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
|
||||
assigned-clock-parents = <&mdss1_dp0_phy 0>,
|
||||
<&mdss1_dp0_phy 1>,
|
||||
<&mdss1_dp0_phy 1>;
|
||||
operating-points-v2 = <&mdss1_dp0_opp_table>;
|
||||
|
||||
#sound-dai-cells = <0>;
|
||||
@@ -6118,10 +6136,12 @@ mdss1_dp1: displayport-controller@22098000 {
|
||||
<&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>,
|
||||
<&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK>,
|
||||
<&dispcc1 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
|
||||
<&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
|
||||
<&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
|
||||
<&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL1_CLK>;
|
||||
clock-names = "core_iface", "core_aux",
|
||||
"ctrl_link",
|
||||
"ctrl_link_iface", "stream_pixel";
|
||||
"ctrl_link_iface", "stream_pixel",
|
||||
"stream_1_pixel";
|
||||
interrupt-parent = <&mdss1>;
|
||||
interrupts = <13>;
|
||||
phys = <&mdss1_dp1_phy>;
|
||||
@@ -6129,8 +6149,11 @@ mdss1_dp1: displayport-controller@22098000 {
|
||||
power-domains = <&rpmhpd SC8280XP_MMCX>;
|
||||
|
||||
assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
|
||||
<&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
|
||||
assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>;
|
||||
<&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
|
||||
<&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
|
||||
assigned-clock-parents = <&mdss1_dp1_phy 0>,
|
||||
<&mdss1_dp1_phy 1>,
|
||||
<&mdss1_dp1_phy 1>;
|
||||
operating-points-v2 = <&mdss1_dp1_opp_table>;
|
||||
|
||||
#sound-dai-cells = <0>;
|
||||
@@ -6193,10 +6216,12 @@ mdss1_dp2: displayport-controller@2209a000 {
|
||||
<&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>,
|
||||
<&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK>,
|
||||
<&dispcc1 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
|
||||
<&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
|
||||
<&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>,
|
||||
<&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL1_CLK>;
|
||||
clock-names = "core_iface", "core_aux",
|
||||
"ctrl_link",
|
||||
"ctrl_link_iface", "stream_pixel";
|
||||
"ctrl_link_iface", "stream_pixel",
|
||||
"stream_1_pixel";
|
||||
interrupt-parent = <&mdss1>;
|
||||
interrupts = <14>;
|
||||
phys = <&mdss1_dp2_phy>;
|
||||
@@ -6204,8 +6229,11 @@ mdss1_dp2: displayport-controller@2209a000 {
|
||||
power-domains = <&rpmhpd SC8280XP_MMCX>;
|
||||
|
||||
assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
|
||||
<&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
|
||||
assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>;
|
||||
<&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>,
|
||||
<&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>;
|
||||
assigned-clock-parents = <&mdss1_dp2_phy 0>,
|
||||
<&mdss1_dp2_phy 1>,
|
||||
<&mdss1_dp2_phy 1>;
|
||||
operating-points-v2 = <&mdss1_dp2_opp_table>;
|
||||
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
@@ -5,6 +5,7 @@
|
||||
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include "sdm845-oneplus-common.dtsi"
|
||||
|
||||
/ {
|
||||
@@ -61,6 +62,33 @@ &pmi8998_charger {
|
||||
monitored-battery = <&battery>;
|
||||
};
|
||||
|
||||
&pmi8998_lpg {
|
||||
status = "okay";
|
||||
|
||||
multi-led {
|
||||
color = <LED_COLOR_ID_RGB>;
|
||||
function = LED_FUNCTION_STATUS;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
led@3 {
|
||||
reg = <3>;
|
||||
color = <LED_COLOR_ID_BLUE>;
|
||||
};
|
||||
|
||||
led@4 {
|
||||
reg = <4>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
};
|
||||
|
||||
led@5 {
|
||||
reg = <5>;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sound {
|
||||
model = "OnePlus 6";
|
||||
audio-routing = "RX_BIAS", "MCLK",
|
||||
|
||||
@@ -56,6 +56,21 @@ framebuffer: framebuffer@9d400000 {
|
||||
};
|
||||
};
|
||||
|
||||
slpi_regulator: slpi-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
pinctrl-0 = <&slpi_ldo_active_state>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "slpi";
|
||||
|
||||
enable-active-high;
|
||||
gpio = <&tlmm 8 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
vib_regulator: gpio-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
@@ -118,7 +133,7 @@ removed_region: removed-region@88f00000 {
|
||||
};
|
||||
|
||||
slpi_mem: slpi@96700000 {
|
||||
reg = <0 0x96700000 0 0xf00000>;
|
||||
reg = <0 0x96700000 0 0x1000000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
@@ -902,6 +917,13 @@ &ipa {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&slpi_pas {
|
||||
firmware-name = "qcom/sdm845/starqltechn/slpi.mbn";
|
||||
cx-supply = <&slpi_regulator>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1 {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -1028,6 +1050,13 @@ sd_card_det_n_state: sd-card-det-n-state {
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
slpi_ldo_active_state: slpi-ldo-active-state {
|
||||
pins = "gpio8";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
touch_irq_state: touch-irq-state {
|
||||
pins = "gpio120";
|
||||
function = "gpio";
|
||||
|
||||
@@ -4656,12 +4656,19 @@ mdss_dp: displayport-controller@ae90000 {
|
||||
<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
|
||||
clock-names = "core_iface", "core_aux", "ctrl_link",
|
||||
"ctrl_link_iface", "stream_pixel";
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
|
||||
clock-names = "core_iface",
|
||||
"core_aux",
|
||||
"ctrl_link",
|
||||
"ctrl_link_iface",
|
||||
"stream_pixel",
|
||||
"stream_1_pixel";
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
|
||||
assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
|
||||
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
|
||||
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
|
||||
phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
|
||||
phy-names = "dp";
|
||||
|
||||
@@ -4163,6 +4163,17 @@ usb_2_dwc3: usb@a800000 {
|
||||
};
|
||||
};
|
||||
|
||||
tsens0: thermal-sensor@c263000 {
|
||||
compatible = "qcom,qcs615-tsens", "qcom,tsens-v2";
|
||||
reg = <0x0 0x0c263000 0x0 0x1000>,
|
||||
<0x0 0x0c222000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "uplow", "critical";
|
||||
#qcom,sensors = <16>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
remoteproc_adsp: remoteproc@62400000 {
|
||||
compatible = "qcom,qcs615-adsp-pas", "qcom,sm8150-adsp-pas";
|
||||
reg = <0x0 0x62400000 0x0 0x4040>;
|
||||
@@ -4249,7 +4260,6 @@ cpufreq_hw: cpufreq@18323000 {
|
||||
#freq-domain-cells = <1>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
arch_timer: timer {
|
||||
@@ -4259,4 +4269,198 @@ arch_timer: timer {
|
||||
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
aoss-thermal {
|
||||
thermal-sensors = <&tsens0 0>;
|
||||
|
||||
trips {
|
||||
aoss-critical {
|
||||
temperature = <115000>;
|
||||
hysteresis = <1000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpuss-0-thermal {
|
||||
thermal-sensors = <&tsens0 1>;
|
||||
|
||||
trips {
|
||||
cpuss0-critical {
|
||||
temperature = <115000>;
|
||||
hysteresis = <1000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpuss-1-thermal {
|
||||
thermal-sensors = <&tsens0 2>;
|
||||
|
||||
trips {
|
||||
cpuss1-critical {
|
||||
temperature = <115000>;
|
||||
hysteresis = <1000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpuss-2-thermal {
|
||||
thermal-sensors = <&tsens0 3>;
|
||||
|
||||
trips {
|
||||
cpuss2-critical {
|
||||
temperature = <115000>;
|
||||
hysteresis = <1000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpuss-3-thermal {
|
||||
thermal-sensors = <&tsens0 4>;
|
||||
|
||||
trips {
|
||||
cpuss3-critical {
|
||||
temperature = <115000>;
|
||||
hysteresis = <1000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu-1-0-thermal {
|
||||
thermal-sensors = <&tsens0 5>;
|
||||
|
||||
trips {
|
||||
cpu-critical {
|
||||
temperature = <115000>;
|
||||
hysteresis = <1000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu-1-1-thermal {
|
||||
thermal-sensors = <&tsens0 6>;
|
||||
|
||||
trips {
|
||||
cpu-critical {
|
||||
temperature = <115000>;
|
||||
hysteresis = <1000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu-1-2-thermal {
|
||||
thermal-sensors = <&tsens0 7>;
|
||||
|
||||
trips {
|
||||
cpu-critical {
|
||||
temperature = <115000>;
|
||||
hysteresis = <1000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu-1-3-thermal {
|
||||
thermal-sensors = <&tsens0 8>;
|
||||
|
||||
trips {
|
||||
cpu-critical {
|
||||
temperature = <115000>;
|
||||
hysteresis = <1000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpu-thermal {
|
||||
thermal-sensors = <&tsens0 9>;
|
||||
|
||||
trips {
|
||||
gpu-critical {
|
||||
temperature = <115000>;
|
||||
hysteresis = <1000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
q6-hvx-thermal {
|
||||
thermal-sensors = <&tsens0 10>;
|
||||
|
||||
trips {
|
||||
q6-hvx-critical {
|
||||
temperature = <115000>;
|
||||
hysteresis = <1000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdm-core-thermal {
|
||||
thermal-sensors = <&tsens0 11>;
|
||||
|
||||
trips {
|
||||
mdm-core-critical {
|
||||
temperature = <115000>;
|
||||
hysteresis = <1000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
camera-thermal {
|
||||
thermal-sensors = <&tsens0 12>;
|
||||
|
||||
trips {
|
||||
camera-critical {
|
||||
temperature = <115000>;
|
||||
hysteresis = <1000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
wlan-thermal {
|
||||
thermal-sensors = <&tsens0 13>;
|
||||
|
||||
trips {
|
||||
wlan-critical {
|
||||
temperature = <115000>;
|
||||
hysteresis = <1000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
display-thermal {
|
||||
thermal-sensors = <&tsens0 14>;
|
||||
|
||||
trips {
|
||||
display-critical {
|
||||
temperature = <115000>;
|
||||
hysteresis = <1000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
video-thermal {
|
||||
thermal-sensors = <&tsens0 15>;
|
||||
|
||||
trips {
|
||||
video-critical {
|
||||
temperature = <115000>;
|
||||
hysteresis = <1000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -2249,7 +2249,7 @@ opp-560000000 {
|
||||
};
|
||||
|
||||
mdss_dp: displayport-controller@ae90000 {
|
||||
compatible = "qcom,sm6350-dp", "qcom,sm8350-dp";
|
||||
compatible = "qcom,sm6350-dp", "qcom,sc7180-dp";
|
||||
reg = <0x0 0xae90000 0x0 0x200>,
|
||||
<0x0 0xae90200 0x0 0x200>,
|
||||
<0x0 0xae90400 0x0 0x600>,
|
||||
|
||||
@@ -3890,16 +3890,20 @@ mdss_dp: displayport-controller@ae90000 {
|
||||
<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
|
||||
clock-names = "core_iface",
|
||||
"core_aux",
|
||||
"ctrl_link",
|
||||
"ctrl_link_iface",
|
||||
"stream_pixel";
|
||||
"stream_pixel",
|
||||
"stream_1_pixel";
|
||||
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
|
||||
assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
|
||||
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
|
||||
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
|
||||
|
||||
phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
|
||||
@@ -4420,7 +4424,7 @@ frame@17c25000 {
|
||||
frame@17c27000 {
|
||||
frame-number = <3>;
|
||||
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x17c26000 0x1000>;
|
||||
reg = <0x17c27000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
||||
@@ -4771,16 +4771,20 @@ mdss_dp: displayport-controller@ae90000 {
|
||||
<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
|
||||
clock-names = "core_iface",
|
||||
"core_aux",
|
||||
"ctrl_link",
|
||||
"ctrl_link_iface",
|
||||
"stream_pixel";
|
||||
"stream_pixel",
|
||||
"stream_1_pixel";
|
||||
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
|
||||
assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
|
||||
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
|
||||
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
|
||||
|
||||
phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
|
||||
|
||||
@@ -2876,16 +2876,20 @@ mdss_dp: displayport-controller@ae90000 {
|
||||
<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
|
||||
clock-names = "core_iface",
|
||||
"core_aux",
|
||||
"ctrl_link",
|
||||
"ctrl_link_iface",
|
||||
"stream_pixel";
|
||||
"stream_pixel",
|
||||
"stream_1_pixel";
|
||||
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
|
||||
assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
|
||||
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
|
||||
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
|
||||
|
||||
phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
|
||||
|
||||
145
arch/arm64/boot/dts/qcom/sm8450-samsung-r0q.dts
Normal file
145
arch/arm64/boot/dts/qcom/sm8450-samsung-r0q.dts
Normal file
@@ -0,0 +1,145 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
|
||||
|
||||
#include "sm8450.dtsi"
|
||||
#include "pm8350.dtsi"
|
||||
#include "pm8350c.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Samsung Galaxy S22 5G";
|
||||
compatible = "samsung,r0q", "qcom,sm8450";
|
||||
chassis-type = "handset";
|
||||
|
||||
chosen {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
framebuffer: framebuffer@b8000000 {
|
||||
compatible = "simple-framebuffer";
|
||||
reg = <0x0 0xb8000000 0x0 0x2b00000>;
|
||||
width = <1080>;
|
||||
height = <2340>;
|
||||
stride = <(1080 * 4)>;
|
||||
format = "a8r8g8b8";
|
||||
};
|
||||
};
|
||||
|
||||
vph_pwr: regulator-vph-pwr {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vph_pwr";
|
||||
regulator-min-microvolt = <3700000>;
|
||||
regulator-max-microvolt = <3700000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
/*
|
||||
* The bootloader will only keep display hardware enabled
|
||||
* if this memory region is named exactly 'splash_region'
|
||||
*/
|
||||
splash-region@b8000000 {
|
||||
reg = <0x0 0xb8000000 0x0 0x2b00000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&apps_rsc {
|
||||
regulators-0 {
|
||||
compatible = "qcom,pm8350-rpmh-regulators";
|
||||
qcom,pmic-id = "b";
|
||||
|
||||
vdd-s1-supply = <&vph_pwr>;
|
||||
vdd-s2-supply = <&vph_pwr>;
|
||||
vdd-s3-supply = <&vph_pwr>;
|
||||
vdd-s4-supply = <&vph_pwr>;
|
||||
vdd-s5-supply = <&vph_pwr>;
|
||||
vdd-s6-supply = <&vph_pwr>;
|
||||
vdd-s7-supply = <&vph_pwr>;
|
||||
vdd-s8-supply = <&vph_pwr>;
|
||||
vdd-s9-supply = <&vph_pwr>;
|
||||
vdd-s10-supply = <&vph_pwr>;
|
||||
vdd-s11-supply = <&vph_pwr>;
|
||||
vdd-s12-supply = <&vph_pwr>;
|
||||
|
||||
vdd-l2-l7-supply = <&vreg_bob>;
|
||||
vdd-l3-l5-supply = <&vreg_bob>;
|
||||
|
||||
vreg_l2b_3p07: ldo2 {
|
||||
regulator-min-microvolt = <3072000>;
|
||||
regulator-max-microvolt = <3072000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l5b_0p88: ldo5 {
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <888000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators-1 {
|
||||
compatible = "qcom,pm8350c-rpmh-regulators";
|
||||
qcom,pmic-id = "c";
|
||||
|
||||
vdd-s1-supply = <&vph_pwr>;
|
||||
vdd-s2-supply = <&vph_pwr>;
|
||||
vdd-s3-supply = <&vph_pwr>;
|
||||
vdd-s4-supply = <&vph_pwr>;
|
||||
vdd-s5-supply = <&vph_pwr>;
|
||||
vdd-s6-supply = <&vph_pwr>;
|
||||
vdd-s7-supply = <&vph_pwr>;
|
||||
vdd-s8-supply = <&vph_pwr>;
|
||||
vdd-s9-supply = <&vph_pwr>;
|
||||
vdd-s10-supply = <&vph_pwr>;
|
||||
|
||||
vdd-l1-l12-supply = <&vreg_bob>;
|
||||
vdd-l2-l8-supply = <&vreg_bob>;
|
||||
vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob>;
|
||||
vdd-l6-l9-l11-supply = <&vreg_bob>;
|
||||
|
||||
vdd-bob-supply = <&vph_pwr>;
|
||||
|
||||
vreg_bob: bob {
|
||||
regulator-min-microvolt = <3008000>;
|
||||
regulator-max-microvolt = <3960000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_l1c_1p8: ldo1 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
gpio-reserved-ranges = <36 4>; /* SPI (not linked to anything) */
|
||||
};
|
||||
|
||||
&usb_1 {
|
||||
/* Keep USB 2.0 only for now */
|
||||
qcom,select-utmi-as-pipe-clk;
|
||||
|
||||
dr_mode = "peripheral";
|
||||
maximum-speed = "high-speed";
|
||||
/* Remove USB3 phy */
|
||||
phys = <&usb_1_hsphy>;
|
||||
phy-names = "usb2-phy";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1_hsphy {
|
||||
vdda-pll-supply = <&vreg_l5b_0p88>;
|
||||
vdda18-supply = <&vreg_l1c_1p8>;
|
||||
vdda33-supply = <&vreg_l2b_3p07>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
@@ -3300,7 +3300,6 @@ camcc: clock-controller@ade0000 {
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mdss: display-subsystem@ae00000 {
|
||||
@@ -3435,16 +3434,20 @@ mdss_dp0: displayport-controller@ae90000 {
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
|
||||
clock-names = "core_iface",
|
||||
"core_aux",
|
||||
"ctrl_link",
|
||||
"ctrl_link_iface",
|
||||
"stream_pixel";
|
||||
"stream_pixel",
|
||||
"stream_1_pixel";
|
||||
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
|
||||
assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
|
||||
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
|
||||
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
|
||||
|
||||
phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
|
||||
|
||||
@@ -3262,7 +3262,7 @@ &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
|
||||
|
||||
/*
|
||||
* IRIS firmware is signed by vendors, only
|
||||
* enable in boards where the proper signed firmware
|
||||
* enable on boards where the proper signed firmware
|
||||
* is available.
|
||||
*/
|
||||
status = "disabled";
|
||||
@@ -3759,16 +3759,20 @@ mdss_dp0: displayport-controller@ae90000 {
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
|
||||
clock-names = "core_iface",
|
||||
"core_aux",
|
||||
"ctrl_link",
|
||||
"ctrl_link_iface",
|
||||
"stream_pixel";
|
||||
"stream_pixel",
|
||||
"stream_1_pixel";
|
||||
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
|
||||
assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
|
||||
<&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
|
||||
<&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
|
||||
|
||||
phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
|
||||
|
||||
@@ -5186,7 +5186,7 @@ &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
|
||||
|
||||
/*
|
||||
* IRIS firmware is signed by vendors, only
|
||||
* enable in boards where the proper signed firmware
|
||||
* enable on boards where the proper signed firmware
|
||||
* is available.
|
||||
*/
|
||||
status = "disabled";
|
||||
@@ -5660,16 +5660,20 @@ mdss_dp0: displayport-controller@af54000 {
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
|
||||
clock-names = "core_iface",
|
||||
"core_aux",
|
||||
"ctrl_link",
|
||||
"ctrl_link_iface",
|
||||
"stream_pixel";
|
||||
"stream_pixel",
|
||||
"stream_1_pixel";
|
||||
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
|
||||
assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
|
||||
<&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
|
||||
<&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
|
||||
|
||||
operating-points-v2 = <&dp_opp_table>;
|
||||
|
||||
@@ -201,6 +201,74 @@ vph_pwr: vph-pwr-regulator {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
/*
|
||||
* MTPs rev 2.0 (power grid v8) come with two different WiFi chips:
|
||||
* WCN7850 and WCN786x.
|
||||
* Device nodes here for the PMU, WiFi and Bluetooth describe the MTP
|
||||
* variant with WCN7850.
|
||||
*/
|
||||
wcn7850-pmu {
|
||||
compatible = "qcom,wcn7850-pmu";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wlan_en>, <&bt_default>;
|
||||
|
||||
wlan-enable-gpios = <&tlmm 16 GPIO_ACTIVE_HIGH>;
|
||||
bt-enable-gpios = <&pm8550ve_f_gpios 3 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
vdd-supply = <&vreg_s5f_0p85>;
|
||||
vddio-supply = <&vreg_l3f_1p8>;
|
||||
vddio1p2-supply = <&vreg_l2f_1p2>;
|
||||
vddaon-supply = <&vreg_s4d_0p85>;
|
||||
vdddig-supply = <&vreg_s1d_0p97>;
|
||||
vddrfa1p2-supply = <&vreg_s7i_1p2>;
|
||||
vddrfa1p8-supply = <&vreg_s3g_1p8>;
|
||||
|
||||
clocks = <&rpmhcc RPMH_RF_CLK1>;
|
||||
|
||||
regulators {
|
||||
vreg_pmu_rfa_cmn: ldo0 {
|
||||
regulator-name = "vreg_pmu_rfa_cmn";
|
||||
};
|
||||
|
||||
vreg_pmu_aon_0p59: ldo1 {
|
||||
regulator-name = "vreg_pmu_aon_0p59";
|
||||
};
|
||||
|
||||
vreg_pmu_wlcx_0p8: ldo2 {
|
||||
regulator-name = "vreg_pmu_wlcx_0p8";
|
||||
};
|
||||
|
||||
vreg_pmu_wlmx_0p85: ldo3 {
|
||||
regulator-name = "vreg_pmu_wlmx_0p85";
|
||||
};
|
||||
|
||||
vreg_pmu_btcmx_0p85: ldo4 {
|
||||
regulator-name = "vreg_pmu_btcmx_0p85";
|
||||
};
|
||||
|
||||
vreg_pmu_rfa_0p8: ldo5 {
|
||||
regulator-name = "vreg_pmu_rfa_0p8";
|
||||
};
|
||||
|
||||
vreg_pmu_rfa_1p2: ldo6 {
|
||||
regulator-name = "vreg_pmu_rfa_1p2";
|
||||
};
|
||||
|
||||
vreg_pmu_rfa_1p8: ldo7 {
|
||||
regulator-name = "vreg_pmu_rfa_1p8";
|
||||
};
|
||||
|
||||
vreg_pmu_pcie_0p9: ldo8 {
|
||||
regulator-name = "vreg_pmu_pcie_0p9";
|
||||
};
|
||||
|
||||
vreg_pmu_pcie_1p8: ldo9 {
|
||||
regulator-name = "vreg_pmu_pcie_1p8";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&apps_rsc {
|
||||
@@ -426,7 +494,7 @@ vreg_s3d_1p2: smps3 {
|
||||
|
||||
vreg_s4d_0p85: smps4 {
|
||||
regulator-name = "vreg_s4d_0p85";
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-min-microvolt = <852000>;
|
||||
regulator-max-microvolt = <1036000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
@@ -472,9 +540,9 @@ regulators-2 {
|
||||
|
||||
qcom,pmic-id = "f";
|
||||
|
||||
vreg_s5f_0p5: smps5 {
|
||||
regulator-name = "vreg_s5f_0p5";
|
||||
regulator-min-microvolt = <500000>;
|
||||
vreg_s5f_0p85: smps5 {
|
||||
regulator-name = "vreg_s5f_0p85";
|
||||
regulator-min-microvolt = <852000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
@@ -891,6 +959,40 @@ &pon_resin {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
wake-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>;
|
||||
perst-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>;
|
||||
|
||||
pinctrl-0 = <&pcie0_default_state>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0_phy {
|
||||
vdda-phy-supply = <&vreg_l1f_0p88>;
|
||||
vdda-pll-supply = <&vreg_l3g_1p2>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcieport0 {
|
||||
wifi@0 {
|
||||
compatible = "pci17cb,1107";
|
||||
reg = <0x10000 0x0 0x0 0x0 0x0>;
|
||||
|
||||
vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
|
||||
vddaon-supply = <&vreg_pmu_aon_0p59>;
|
||||
vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
|
||||
vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
|
||||
vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
|
||||
vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
|
||||
vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
|
||||
vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
|
||||
vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
|
||||
};
|
||||
};
|
||||
|
||||
&pmih0108_eusb2_repeater {
|
||||
status = "okay";
|
||||
|
||||
@@ -902,6 +1004,10 @@ &qupv3_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qupv3_2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&remoteproc_adsp {
|
||||
firmware-name = "qcom/sm8750/adsp.mbn",
|
||||
"qcom/sm8750/adsp_dtb.mbn";
|
||||
@@ -1035,6 +1141,14 @@ spkr_1_sd_n_active: spkr-1-sd-n-active-state {
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
bt_default: bt-default-state {
|
||||
sw-ctrl-pins {
|
||||
pins = "gpio18";
|
||||
function = "gpio";
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
wcd_default: wcd-reset-n-active-state {
|
||||
pins = "gpio101";
|
||||
function = "gpio";
|
||||
@@ -1042,6 +1156,31 @@ wcd_default: wcd-reset-n-active-state {
|
||||
bias-disable;
|
||||
output-low;
|
||||
};
|
||||
|
||||
wlan_en: wlan-en-state {
|
||||
pins = "gpio16";
|
||||
function = "gpio";
|
||||
drive-strength = <8>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
&uart14 {
|
||||
status = "okay";
|
||||
|
||||
bluetooth {
|
||||
compatible = "qcom,wcn7850-bt";
|
||||
|
||||
vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
|
||||
vddaon-supply = <&vreg_pmu_aon_0p59>;
|
||||
vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
|
||||
vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
|
||||
vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
|
||||
vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
|
||||
vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
|
||||
|
||||
max-speed = <3200000>;
|
||||
};
|
||||
};
|
||||
|
||||
&ufs_mem_phy {
|
||||
|
||||
@@ -12,6 +12,11 @@ &gpu_zap_shader {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&iris {
|
||||
/* TODO: Add video-firmware iommus to start IRIS from EL2 */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/*
|
||||
* When running under Gunyah, this IOMMU is controlled by the firmware,
|
||||
* however when we take ownership of it in EL2, we need to configure
|
||||
|
||||
1544
arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi
Normal file
1544
arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
@@ -967,6 +967,11 @@ touchscreen@10 {
|
||||
/* TODO: second-sourced touchscreen @ 0x41 */
|
||||
};
|
||||
|
||||
&iris {
|
||||
firmware-name = "qcom/x1e80100/LENOVO/21N1/qcvss8380.mbn";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&lpass_tlmm {
|
||||
spkr_01_sd_n_active: spkr-01-sd-n-active-state {
|
||||
pins = "gpio12";
|
||||
|
||||
@@ -16,3 +16,7 @@ / {
|
||||
&gpu_zap_shader {
|
||||
firmware-name = "qcom/x1e80100/gen70500_zap.mbn";
|
||||
};
|
||||
|
||||
&iris {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@@ -37,6 +37,11 @@ touchscreen@10 {
|
||||
};
|
||||
};
|
||||
|
||||
&iris {
|
||||
firmware-name = "qcom/x1e80100/dell/inspiron-14-plus-7441/qcvss8380.mbn";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&remoteproc_adsp {
|
||||
firmware-name = "qcom/x1e80100/dell/inspiron-14-plus-7441/qcadsp8380.mbn",
|
||||
"qcom/x1e80100/dell/inspiron-14-plus-7441/adsp_dtbs.elf";
|
||||
|
||||
@@ -38,6 +38,11 @@ touchscreen@9 {
|
||||
};
|
||||
};
|
||||
|
||||
&iris {
|
||||
firmware-name = "qcom/x1e80100/dell/latitude-7455/qcvss8380.mbn";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&remoteproc_adsp {
|
||||
firmware-name = "qcom/x1e80100/dell/latitude-7455/qcadsp8380.mbn",
|
||||
"qcom/x1e80100/dell/latitude-7455/adsp_dtbs.elf";
|
||||
|
||||
@@ -875,6 +875,11 @@ touchpad@2c {
|
||||
};
|
||||
};
|
||||
|
||||
&iris {
|
||||
firmware-name = "qcom/x1e80100/dell/xps13-9345/qcvss8380.mbn";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1026,6 +1026,11 @@ touchscreen@14 {
|
||||
};
|
||||
};
|
||||
|
||||
&iris {
|
||||
firmware-name = "qcom/x1e80100/LENOVO/83ED/qcvss8380.mbn";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&lpass_tlmm {
|
||||
spkr_01_sd_n_active: spkr-01-sd-n-active-state {
|
||||
pins = "gpio12";
|
||||
|
||||
@@ -5234,6 +5234,93 @@ usb_1_ss1_dwc3_ss: endpoint {
|
||||
};
|
||||
};
|
||||
|
||||
iris: video-codec@aa00000 {
|
||||
compatible = "qcom,x1e80100-iris", "qcom,sm8550-iris";
|
||||
|
||||
reg = <0 0x0aa00000 0 0xf0000>;
|
||||
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
|
||||
<&videocc VIDEO_CC_MVS0_GDSC>,
|
||||
<&rpmhpd RPMHPD_MXC>,
|
||||
<&rpmhpd RPMHPD_MMCX>;
|
||||
power-domain-names = "venus",
|
||||
"vcodec0",
|
||||
"mxc",
|
||||
"mmcx";
|
||||
operating-points-v2 = <&iris_opp_table>;
|
||||
|
||||
clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
|
||||
<&videocc VIDEO_CC_MVS0C_CLK>,
|
||||
<&videocc VIDEO_CC_MVS0_CLK>;
|
||||
clock-names = "iface",
|
||||
"core",
|
||||
"vcodec0_core";
|
||||
|
||||
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
||||
&config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
|
||||
<&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "cpu-cfg",
|
||||
"video-mem";
|
||||
|
||||
memory-region = <&video_mem>;
|
||||
|
||||
resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>;
|
||||
reset-names = "bus";
|
||||
|
||||
iommus = <&apps_smmu 0x1940 0>,
|
||||
<&apps_smmu 0x1947 0>;
|
||||
dma-coherent;
|
||||
|
||||
/*
|
||||
* IRIS firmware is signed by vendors, only
|
||||
* enable on boards where the proper signed firmware
|
||||
* is available.
|
||||
*/
|
||||
status = "disabled";
|
||||
|
||||
iris_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-192000000 {
|
||||
opp-hz = /bits/ 64 <192000000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs_d1>,
|
||||
<&rpmhpd_opp_low_svs_d1>;
|
||||
};
|
||||
|
||||
opp-240000000 {
|
||||
opp-hz = /bits/ 64 <240000000>;
|
||||
required-opps = <&rpmhpd_opp_svs>,
|
||||
<&rpmhpd_opp_low_svs>;
|
||||
};
|
||||
|
||||
opp-338000000 {
|
||||
opp-hz = /bits/ 64 <338000000>;
|
||||
required-opps = <&rpmhpd_opp_svs>,
|
||||
<&rpmhpd_opp_svs>;
|
||||
};
|
||||
|
||||
opp-366000000 {
|
||||
opp-hz = /bits/ 64 <366000000>;
|
||||
required-opps = <&rpmhpd_opp_svs_l1>,
|
||||
<&rpmhpd_opp_svs_l1>;
|
||||
};
|
||||
|
||||
opp-444000000 {
|
||||
opp-hz = /bits/ 64 <444000000>;
|
||||
required-opps = <&rpmhpd_opp_nom>,
|
||||
<&rpmhpd_opp_nom>;
|
||||
};
|
||||
|
||||
opp-481000000 {
|
||||
opp-hz = /bits/ 64 <481000000>;
|
||||
required-opps = <&rpmhpd_opp_turbo>,
|
||||
<&rpmhpd_opp_turbo>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
videocc: clock-controller@aaf0000 {
|
||||
compatible = "qcom,x1e80100-videocc";
|
||||
reg = <0 0x0aaf0000 0 0x10000>;
|
||||
@@ -5389,16 +5476,20 @@ mdss_dp0: displayport-controller@ae90000 {
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
|
||||
clock-names = "core_iface",
|
||||
"core_aux",
|
||||
"ctrl_link",
|
||||
"ctrl_link_iface",
|
||||
"stream_pixel";
|
||||
"stream_pixel",
|
||||
"stream_1_pixel";
|
||||
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
|
||||
assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
|
||||
<&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
|
||||
<&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
|
||||
|
||||
operating-points-v2 = <&mdss_dp0_opp_table>;
|
||||
@@ -5473,16 +5564,20 @@ mdss_dp1: displayport-controller@ae98000 {
|
||||
<&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
|
||||
<&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK>;
|
||||
clock-names = "core_iface",
|
||||
"core_aux",
|
||||
"ctrl_link",
|
||||
"ctrl_link_iface",
|
||||
"stream_pixel";
|
||||
"stream_pixel",
|
||||
"stream_1_pixel";
|
||||
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
|
||||
<&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
|
||||
assigned-clock-parents = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
|
||||
<&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
|
||||
<&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
|
||||
|
||||
operating-points-v2 = <&mdss_dp1_opp_table>;
|
||||
@@ -5557,16 +5652,20 @@ mdss_dp2: displayport-controller@ae9a000 {
|
||||
<&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
|
||||
<&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK>;
|
||||
clock-names = "core_iface",
|
||||
"core_aux",
|
||||
"ctrl_link",
|
||||
"ctrl_link_iface",
|
||||
"stream_pixel";
|
||||
"stream_pixel",
|
||||
"stream_1_pixel";
|
||||
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
|
||||
<&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>;
|
||||
assigned-clock-parents = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>,
|
||||
<&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
|
||||
<&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
|
||||
|
||||
operating-points-v2 = <&mdss_dp2_opp_table>;
|
||||
|
||||
33
arch/arm64/boot/dts/qcom/x1p42100-hp-omnibook-x14.dts
Normal file
33
arch/arm64/boot/dts/qcom/x1p42100-hp-omnibook-x14.dts
Normal file
@@ -0,0 +1,33 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "x1p42100.dtsi"
|
||||
#include "x1e80100-pmics.dtsi"
|
||||
#include "x1-hp-omnibook-x14.dtsi"
|
||||
/delete-node/ &pmc8380_6;
|
||||
/delete-node/ &pmc8380_6_thermal;
|
||||
|
||||
/ {
|
||||
model = "HP Omnibook X 14-fe1";
|
||||
compatible = "hp,omnibook-x14-fe1", "qcom,x1p42100";
|
||||
chassis-type = "laptop";
|
||||
};
|
||||
|
||||
&gpu_zap_shader {
|
||||
firmware-name = "qcom/x1p42100/hp/omnibook-x14/qcdxkmsucpurwa.mbn";
|
||||
};
|
||||
|
||||
&remoteproc_adsp {
|
||||
firmware-name = "qcom/x1p42100/hp/omnibook-x14/qcadsp8380.mbn",
|
||||
"qcom/x1p42100/hp/omnibook-x14/adsp_dtbs.elf";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&remoteproc_cdsp {
|
||||
firmware-name = "qcom/x1p42100/hp/omnibook-x14/qccdsp8380.mbn",
|
||||
"qcom/x1p42100/hp/omnibook-x14/cdsp_dtbs.elf";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
Reference in New Issue
Block a user