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Merge tag 'v5.19-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/dt

Browse Source 
Some fixes to follow DT spec.

MT6795:
- Big update of supported devices: cpu-map, L2 cache, PMU, watchdog,
  MediaTek timer, Arm CCI, pincontroller

MT7622:
- Change WPS button to active low

MT8173:
- Add infracfg property to the IOMMU node (also for mt2712e)
- Add optional AXI clock to NOR Flash node

MT8183:
- add Medaitek CCI support
- add support for Smart Voltag Scaling (SVS)
- add GCE support to mutex
- Add panel default rotation to some chromebooks
- Add power supply to power domain so that SRAM for the GPU has power

MT8186:
- compatible added, DTS not yet ready.

MT8192:
- Add support for Acer Chromebook 514

MT8195:
- Add efuse node
- Enable USB wakeup support
- Add support for Acer Chromebook Spin 513

* tag 'v5.19-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: (66 commits)
  arm64: dts: mt8183: Add panel rotation
  arm64: dts: mt7622: fix BPI-R64 WPS button
  arm64: dts: mt8173: Fix nor_flash node
  arm64: dts: mediatek: cherry: Add I2C-HID touchscreen on I2C4
  arm64: dts: mediatek: cherry: Enable support for the SPI NOR flash
  arm64: dts: mediatek: cherry: Enable MT6360 sub-pmic on I2C7
  arm64: dts: mediatek: cherry: Enable T-PHYs and USB XHCI controllers
  arm64: dts: mediatek: cherry: Enable I2C and SPI controllers
  arm64: dts: mediatek: cherry: Document gpios and add default pin config
  arm64: dts: mediatek: cherry: Add support for internal eMMC storage
  arm64: dts: mediatek: cherry: Assign interrupt line to MT6359 PMIC
  arm64: dts: mediatek: cherry: Add platform regulators layout and config
  arm64: dts: mediatek: Introduce MT8195 Cherry platform's Tomato
  dt-bindings: arm: mediatek: Add MT8195 Cherry Tomato Chromebooks
  arm64: dts: mediatek: asurada: Add SPI NOR flash memory
  arm64: dts: mediatek: asurada: Enable SCP
  arm64: dts: mediatek: asurada: Enable MMC
  arm64: dts: mediatek: asurada: Add SPMI regulators
  arm64: dts: mediatek: asurada: Add MT6359 PMIC
  arm64: dts: mediatek: asurada: Enable PCIe and add WiFi
  ...

Link: https://lore.kernel.org/r/b0d5b584-2693-73b3-79f6-3e2292f006ea@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2022-07-11 14:02:54 +02:00
parent 1a110d77a9 9c61051561
commit 5a75c2951a
31 changed files with 2606 additions and 155 deletions
Download Patch File Download Diff File Expand all files Collapse all files

30
Documentation/devicetree/bindings/arm/mediatek.yaml
View File

@@ -131,6 +131,36 @@ properties:
- enum:
- mediatek,mt8183-evb
- const: mediatek,mt8183
- description: Google Hayato
items:
- const: google,hayato-rev1
- const: google,hayato
- const: mediatek,mt8192
- description: Google Spherion (Acer Chromebook 514)
items:
- const: google,spherion-rev3
- const: google,spherion-rev2
- const: google,spherion-rev1
- const: google,spherion-rev0
- const: google,spherion
- const: mediatek,mt8192
- description: Acer Tomato (Acer Chromebook Spin 513 CP513-2H)
items:
- enum:
- google,tomato-rev2
- google,tomato-rev1
- const: google,tomato
- const: mediatek,mt8195
- description: Acer Tomato rev3 - 4 (Acer Chromebook Spin 513 CP513-2H)
items:
- const: google,tomato-rev4
- const: google,tomato-rev3
- const: google,tomato
- const: mediatek,mt8195
- items:
- enum:
- mediatek,mt8186-evb
- const: mediatek,mt8186
- items:
- enum:
- mediatek,mt8192-evb

1
Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml
View File

@@ -26,6 +26,7 @@ properties:
- mediatek,mt8135-pericfg
- mediatek,mt8173-pericfg
- mediatek,mt8183-pericfg
- mediatek,mt8186-pericfg
- mediatek,mt8195-pericfg
- mediatek,mt8516-pericfg
- const: syscon

5
arch/arm64/boot/dts/mediatek/Makefile
View File

@@ -37,7 +37,12 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku32.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-spherion-r0.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r2.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r3.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb

2
arch/arm64/boot/dts/mediatek/mt2712-evb.dts
View File

@@ -106,7 +106,7 @@ &cpu2 {
};
&eth {
phy-mode ="rgmii-rxid";
phy-mode = "rgmii-rxid";
phy-handle = <&ethernet_phy0>;
mediatek,tx-delay-ps = <1530>;
snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>;

2
arch/arm64/boot/dts/mediatek/mt2712e.dtsi
View File

@@ -329,6 +329,7 @@ iommu0: iommu@10205000 {
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_INFRA_M4U>;
clock-names = "bclk";
mediatek,infracfg = <&infracfg>;
mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
<&larb3>, <&larb6>;
#iommu-cells = <1>;
@@ -346,6 +347,7 @@ iommu1: iommu@1020a000 {
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_INFRA_M4U>;
clock-names = "bclk";
mediatek,infracfg = <&infracfg>;
mediatek,larbs = <&larb4>, <&larb5>, <&larb7>;
#iommu-cells = <1>;
};

268
arch/arm64/boot/dts/mediatek/mt6795.dtsi
View File

@@ -13,6 +13,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/mt6795-pinfunc.h>
/ {
compatible = "mediatek,mt6795";
@@ -34,6 +35,8 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x000>;
cci-control-port = <&cci_control2>;
next-level-cache = <&l2_0>;
};
cpu1: cpu@1 {
@@ -41,6 +44,8 @@ cpu1: cpu@1 {
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x001>;
cci-control-port = <&cci_control2>;
next-level-cache = <&l2_0>;
};
cpu2: cpu@2 {
@@ -48,6 +53,8 @@ cpu2: cpu@2 {
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x002>;
cci-control-port = <&cci_control2>;
next-level-cache = <&l2_0>;
};
cpu3: cpu@3 {
@@ -55,6 +62,8 @@ cpu3: cpu@3 {
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x003>;
cci-control-port = <&cci_control2>;
next-level-cache = <&l2_0>;
};
cpu4: cpu@100 {
@@ -62,6 +71,8 @@ cpu4: cpu@100 {
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x100>;
cci-control-port = <&cci_control1>;
next-level-cache = <&l2_1>;
};
cpu5: cpu@101 {
@@ -69,6 +80,8 @@ cpu5: cpu@101 {
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x101>;
cci-control-port = <&cci_control1>;
next-level-cache = <&l2_1>;
};
cpu6: cpu@102 {
@@ -76,6 +89,8 @@ cpu6: cpu@102 {
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x102>;
cci-control-port = <&cci_control1>;
next-level-cache = <&l2_1>;
};
cpu7: cpu@103 {
@@ -83,7 +98,71 @@ cpu7: cpu@103 {
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x103>;
cci-control-port = <&cci_control1>;
next-level-cache = <&l2_1>;
};
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
};
cluster1 {
core0 {
cpu = <&cpu4>;
};
core1 {
cpu = <&cpu5>;
};
core2 {
cpu = <&cpu6>;
};
core3 {
cpu = <&cpu7>;
};
};
};
l2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
};
l2_1: l2-cache1 {
compatible = "cache";
cache-level = <2>;
};
};
clk26m: oscillator-26m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
clock-output-names = "clk26m";
};
clk32k: oscillator-32k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32000>;
clock-output-names = "clk32k";
};
system_clk: dummy13m {
@@ -92,16 +171,13 @@ system_clk: dummy13m {
#clock-cells = <0>;
};
rtc_clk: dummy32k {
compatible = "fixed-clock";
clock-frequency = <32000>;
#clock-cells = <0>;
};
uart_clk: dummy26m {
compatible = "fixed-clock";
clock-frequency = <26000000>;
#clock-cells = <0>;
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 11 IRQ_TYPE_LEVEL_LOW>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
timer {
@@ -117,59 +193,133 @@ timer {
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
sysirq: intpol-controller@10200620 {
compatible = "mediatek,mt6795-sysirq",
"mediatek,mt6577-sysirq";
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
reg = <0 0x10200620 0 0x20>;
};
soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
ranges;
gic: interrupt-controller@10221000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
interrupt-controller;
reg = <0 0x10221000 0 0x1000>,
<0 0x10222000 0 0x2000>,
<0 0x10224000 0 0x2000>,
<0 0x10226000 0 0x2000>;
};
pio: pinctrl@10005000 {
compatible = "mediatek,mt6795-pinctrl";
reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>;
reg-names = "base", "eint";
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pio 0 0 196>;
interrupt-controller;
#interrupt-cells = <2>;
};
uart0: serial@11002000 {
compatible = "mediatek,mt6795-uart",
"mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x400>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>;
status = "disabled";
};
watchdog: watchdog@10007000 {
compatible = "mediatek,mt6795-wdt";
reg = <0 0x10007000 0 0x100>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>;
#reset-cells = <1>;
timeout-sec = <20>;
};
uart1: serial@11003000 {
compatible = "mediatek,mt6795-uart",
"mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x400>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>;
status = "disabled";
};
timer: timer@10008000 {
compatible = "mediatek,mt6795-timer",
"mediatek,mt6577-timer";
reg = <0 0x10008000 0 0x1000>;
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
clocks = <&system_clk>, <&clk32k>;
};
uart2: serial@11004000 {
compatible = "mediatek,mt6795-uart",
"mediatek,mt6577-uart";
reg = <0 0x11004000 0 0x400>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>;
status = "disabled";
};
sysirq: intpol-controller@10200620 {
compatible = "mediatek,mt6795-sysirq",
"mediatek,mt6577-sysirq";
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
reg = <0 0x10200620 0 0x20>;
};
uart3: serial@11005000 {
compatible = "mediatek,mt6795-uart",
"mediatek,mt6577-uart";
reg = <0 0x11005000 0 0x400>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>;
status = "disabled";
gic: interrupt-controller@10221000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
interrupt-controller;
reg = <0 0x10221000 0 0x1000>,
<0 0x10222000 0 0x2000>,
<0 0x10224000 0 0x2000>,
<0 0x10226000 0 0x2000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
cci: cci@10390000 {
compatible = "arm,cci-400";
#address-cells = <1>;
#size-cells = <1>;
reg = <0 0x10390000 0 0x1000>;
ranges = <0 0 0x10390000 0x10000>;
cci_control0: slave-if@1000 {
compatible = "arm,cci-400-ctrl-if";
interface-type = "ace-lite";
reg = <0x1000 0x1000>;
};
cci_control1: slave-if@4000 {
compatible = "arm,cci-400-ctrl-if";
interface-type = "ace";
reg = <0x4000 0x1000>;
};
cci_control2: slave-if@5000 {
compatible = "arm,cci-400-ctrl-if";
interface-type = "ace";
reg = <0x5000 0x1000>;
};
pmu@9000 {
compatible = "arm,cci-400-pmu,r1";
reg = <0x9000 0x5000>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
};
};
uart0: serial@11002000 {
compatible = "mediatek,mt6795-uart",
"mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x400>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
clocks = <&clk26m>;
status = "disabled";
};
uart1: serial@11003000 {
compatible = "mediatek,mt6795-uart",
"mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x400>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
clocks = <&clk26m>;
status = "disabled";
};
uart2: serial@11004000 {
compatible = "mediatek,mt6795-uart",
"mediatek,mt6577-uart";
reg = <0 0x11004000 0 0x400>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
clocks = <&clk26m>;
status = "disabled";
};
uart3: serial@11005000 {
compatible = "mediatek,mt6795-uart",
"mediatek,mt6577-uart";
reg = <0 0x11005000 0 0x400>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
clocks = <&clk26m>;
status = "disabled";
};
};
};

21
arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
View File

@@ -8,6 +8,7 @@
/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include "mt7622.dtsi"
#include "mt6380.dtsi"
@@ -40,30 +41,32 @@ cpu@1 {
gpio-keys {
compatible = "gpio-keys";
factory {
factory-key {
label = "factory";
linux,code = <BTN_0>;
gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
};
wps {
wps-key {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&pio 102 GPIO_ACTIVE_HIGH>;
gpios = <&pio 102 GPIO_ACTIVE_LOW>;
};
};
leds {
compatible = "gpio-leds";
green {
led-0 {
label = "bpi-r64:pio:green";
color = <LED_COLOR_ID_GREEN>;
gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
red {
led-1 {
label = "bpi-r64:pio:red";
color = <LED_COLOR_ID_RED>;
gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
@@ -336,14 +339,14 @@ mux {
i2c1_pins: i2c1-pins {
mux {
function = "i2c";
groups = "i2c1_0";
groups = "i2c1_0";
};
};
i2c2_pins: i2c2-pins {
mux {
function = "i2c";
groups = "i2c2_0";
groups = "i2c2_0";
};
};
@@ -366,14 +369,14 @@ conf {
irrx_pins: irrx-pins {
mux {
function = "ir";
groups = "ir_1_rx";
groups = "ir_1_rx";
};
};
irtx_pins: irtx-pins {
mux {
function = "ir";
groups = "ir_1_tx";
groups = "ir_1_tx";
};
};

13
arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
View File

@@ -40,15 +40,14 @@ cpu@1 {
gpio-keys {
compatible = "gpio-keys";
poll-interval = <100>;
factory {
key-factory {
label = "factory";
linux,code = <BTN_0>;
gpios = <&pio 0 0>;
};
wps {
key-wps {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&pio 102 0>;
@@ -298,14 +297,14 @@ mux {
i2c1_pins: i2c1-pins {
mux {
function = "i2c";
groups = "i2c1_0";
groups = "i2c1_0";
};
};
i2c2_pins: i2c2-pins {
mux {
function = "i2c";
groups = "i2c2_0";
groups = "i2c2_0";
};
};
@@ -328,14 +327,14 @@ conf {
irrx_pins: irrx-pins {
mux {
function = "ir";
groups = "ir_1_rx";
groups = "ir_1_rx";
};
};
irtx_pins: irtx-pins {
mux {
function = "ir";
groups = "ir_1_tx";
groups = "ir_1_tx";
};
};

10
arch/arm64/boot/dts/mediatek/mt7622.dtsi
View File

@@ -118,8 +118,8 @@ clk25m: oscillator {
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
compatible = "arm,psci-0.2";
method = "smc";
};
pmu {
@@ -616,9 +616,9 @@ audsys: clock-controller@11220000 {
afe: audio-controller {
compatible = "mediatek,mt7622-audio";
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "afe", "asys";
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "afe", "asys";
clocks = <&infracfg CLK_INFRA_AUDIO_PD>,
<&topckgen CLK_TOP_AUD1_SEL>,

4
arch/arm64/boot/dts/mediatek/mt7986a.dtsi
View File

@@ -57,8 +57,8 @@ cpu3: cpu@3 {
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
compatible = "arm,psci-0.2";
method = "smc";
};
reserved-memory {

6
arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts
View File

@@ -21,7 +21,7 @@ cpu_crit: cpu_crit0 {
};
&gpio_keys {
/delete-node/tablet_mode;
/delete-node/volume_down;
/delete-node/volume_up;
/delete-node/switch-tablet-mode;
/delete-node/switch-volume-down;
/delete-node/switch-volume-up;
};

24
arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi
View File

@@ -53,7 +53,7 @@ gpio_keys: gpio-keys {
pinctrl-names = "default";
pinctrl-0 = <&gpio_keys_pins>;
lid {
switch-lid {
label = "Lid";
gpios = <&pio 69 GPIO_ACTIVE_LOW>;
linux,code = <SW_LID>;
@@ -61,7 +61,7 @@ lid {
gpio-key,wakeup;
};
power {
switch-power {
label = "Power";
gpios = <&pio 14 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_POWER>;
@@ -69,7 +69,7 @@ power {
gpio-key,wakeup;
};
tablet_mode {
switch-tablet-mode {
label = "Tablet_mode";
gpios = <&pio 121 GPIO_ACTIVE_HIGH>;
linux,code = <SW_TABLET_MODE>;
@@ -77,13 +77,13 @@ tablet_mode {
gpio-key,wakeup;
};
volume_down {
switch-volume-down {
label = "Volume_down";
gpios = <&pio 123 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
};
volume_up {
switch-volume-up {
label = "Volume_up";
gpios = <&pio 124 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
@@ -300,8 +300,8 @@ da9211_vcpu_reg: BUCKA {
regulator-name = "VBUCKA";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1310000>;
regulator-min-microamp = <2000000>;
regulator-max-microamp = <4400000>;
regulator-min-microamp = <2000000>;
regulator-max-microamp = <4400000>;
regulator-ramp-delay = <10000>;
regulator-always-on;
regulator-allowed-modes = <DA9211_BUCK_MODE_SYNC
@@ -312,8 +312,8 @@ da9211_vgpu_reg: BUCKB {
regulator-name = "VBUCKB";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1310000>;
regulator-min-microamp = <2000000>;
regulator-max-microamp = <3000000>;
regulator-min-microamp = <2000000>;
regulator-max-microamp = <3000000>;
regulator-ramp-delay = <10000>;
};
};
@@ -374,8 +374,8 @@ &mmc0 {
mmc-hs400-1_8v;
cap-mmc-hw-reset;
hs400-ds-delay = <0x14015>;
mediatek,hs200-cmd-int-delay=<30>;
mediatek,hs400-cmd-int-delay=<14>;
mediatek,hs200-cmd-int-delay = <30>;
mediatek,hs400-cmd-int-delay = <14>;
mediatek,hs400-cmd-resp-sel-rising;
vmmc-supply = <&mt6397_vemc_3v3_reg>;
vqmmc-supply = <&mt6397_vio18_reg>;
@@ -410,7 +410,7 @@ &mmc3 {
sd-uhs-sdr50;
sd-uhs-sdr104;
keep-power-in-suspend;
enable-sdio-wakeup;
wakeup-source;
cap-sdio-irq;
vmmc-supply = <&sdio_fixed_3v3>;
vqmmc-supply = <&mt6397_vgp3_reg>;

12
arch/arm64/boot/dts/mediatek/mt8173-evb.dts
View File

@@ -122,8 +122,8 @@ da9211_vcpu_reg: BUCKA {
regulator-name = "VBUCKA";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1310000>;
regulator-min-microamp = <2000000>;
regulator-max-microamp = <4400000>;
regulator-min-microamp = <2000000>;
regulator-max-microamp = <4400000>;
regulator-ramp-delay = <10000>;
regulator-always-on;
};
@@ -132,8 +132,8 @@ da9211_vgpu_reg: BUCKB {
regulator-name = "VBUCKB";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1310000>;
regulator-min-microamp = <2000000>;
regulator-max-microamp = <3000000>;
regulator-min-microamp = <2000000>;
regulator-max-microamp = <3000000>;
regulator-ramp-delay = <10000>;
};
};
@@ -148,8 +148,8 @@ &mmc0 {
bus-width = <8>;
max-frequency = <50000000>;
cap-mmc-highspeed;
mediatek,hs200-cmd-int-delay=<26>;
mediatek,hs400-cmd-int-delay=<14>;
mediatek,hs200-cmd-int-delay = <26>;
mediatek,hs400-cmd-int-delay = <14>;
mediatek,hs400-cmd-resp-sel-rising;
vmmc-supply = <&mt6397_vemc_3v3_reg>;
vqmmc-supply = <&mt6397_vio18_reg>;

16
arch/arm64/boot/dts/mediatek/mt8173.dtsi
View File

@@ -246,9 +246,9 @@ pmu_a72 {
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
method = "smc";
cpu_suspend = <0x84000001>;
cpu_off = <0x84000002>;
cpu_on = <0x84000003>;
cpu_suspend = <0x84000001>;
cpu_off = <0x84000002>;
cpu_on = <0x84000003>;
};
clk26m: oscillator0 {
@@ -588,6 +588,7 @@ iommu: iommu@10205000 {
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_INFRA_M4U>;
clock-names = "bclk";
mediatek,infracfg = <&infracfg>;
mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
<&larb3>, <&larb4>, <&larb5>;
#iommu-cells = <1>;
@@ -790,9 +791,12 @@ thermal: thermal@1100b000 {
nor_flash: spi@1100d000 {
compatible = "mediatek,mt8173-nor";
reg = <0 0x1100d000 0 0xe0>;
assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>;
assigned-clock-parents = <&clk26m>;
clocks = <&pericfg CLK_PERI_SPI>,
<&topckgen CLK_TOP_SPINFI_IFR_SEL>;
clock-names = "spi", "sf";
<&topckgen CLK_TOP_SPINFI_IFR_SEL>,
<&pericfg CLK_PERI_NFI>;
clock-names = "spi", "sf", "axi";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1505,7 +1509,7 @@ larb5: larb@19001000 {
vcodec_enc_vp8: vcodec@19002000 {
compatible = "mediatek,mt8173-vcodec-enc-vp8";
reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>,
<&iommu M4U_PORT_VENC_REC_FRM_SET2>,

38
arch/arm64/boot/dts/mediatek/mt8183-evb.dts
View File

@@ -134,7 +134,7 @@ &mmc1 {
vmmc-supply = <&mt6358_vmch_reg>;
vqmmc-supply = <&mt6358_vmc_reg>;
keep-power-in-suspend;
enable-sdio-wakeup;
wakeup-source;
non-removable;
};
@@ -412,6 +412,42 @@ &spi5 {
};
&cci {
proc-supply = <&mt6358_vproc12_reg>;
};
&cpu0 {
proc-supply = <&mt6358_vproc12_reg>;
};
&cpu1 {
proc-supply = <&mt6358_vproc12_reg>;
};
&cpu2 {
proc-supply = <&mt6358_vproc12_reg>;
};
&cpu3 {
proc-supply = <&mt6358_vproc12_reg>;
};
&cpu4 {
proc-supply = <&mt6358_vproc11_reg>;
};
&cpu5 {
proc-supply = <&mt6358_vproc11_reg>;
};
&cpu6 {
proc-supply = <&mt6358_vproc11_reg>;
};
&cpu7 {
proc-supply = <&mt6358_vproc11_reg>;
};
&uart0 {
status = "okay";
};

4
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi
View File

@@ -73,7 +73,7 @@ volume_buttons: volume-buttons {
pinctrl-names = "default";
pinctrl-0 = <&volume_button_pins>;
volume_down {
button-volume-down {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
debounce-interval = <100>;
@@ -81,7 +81,7 @@ volume_down {
gpios = <&pio 6 GPIO_ACTIVE_LOW>;
};
volume_up {
button-volume-up {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
debounce-interval = <100>;

2
arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi
View File

@@ -45,7 +45,7 @@ gpio-keys {
pinctrl-names = "default";
pinctrl-0 = <&pen_eject>;
pen-insert {
switch-pen-insert {
label = "Pen Insert";
/* Insert = low, eject = high */
gpios = <&pio 6 GPIO_ACTIVE_LOW>;

13
arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
View File

@@ -144,7 +144,7 @@ wifi_wakeup: wifi-wakeup {
pinctrl-names = "default";
pinctrl-0 = <&wifi_pins_wakeup>;
wowlan {
button-wowlan {
label = "Wake on WiFi";
gpios = <&pio 113 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_WAKEUP>;
@@ -230,6 +230,10 @@ &auxadc {
status = "okay";
};
&cci {
proc-supply = <&mt6358_vproc12_reg>;
};
&cpu0 {
proc-supply = <&mt6358_vproc12_reg>;
};
@@ -276,6 +280,7 @@ panel: panel@0 {
avee-supply = <&ppvarp_lcd>;
pp1800-supply = <&pp1800_lcd>;
backlight = <&backlight_lcd0>;
rotation = <270>;
port {
panel_in: endpoint {
remote-endpoint = <&dsi_out>;
@@ -378,7 +383,7 @@ &mmc1 {
sd-uhs-sdr50;
sd-uhs-sdr104;
keep-power-in-suspend;
enable-sdio-wakeup;
wakeup-source;
cap-sdio-irq;
non-removable;
no-mmc;
@@ -817,6 +822,10 @@ cros_ec {
};
};
&mfg_async {
domain-supply = <&mt6358_vsram_gpu_reg>;
};
&mfg {
domain-supply = <&mt6358_vgpu_reg>;
};

2
arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts
View File

@@ -159,7 +159,7 @@ &mmc1 {
vmmc-supply = <&mt6358_vmch_reg>;
vqmmc-supply = <&mt6358_vmc_reg>;
keep-power-in-suspend;
enable-sdio-wakeup;
wakeup-source;
non-removable;
};

315
arch/arm64/boot/dts/mediatek/mt8183.dtsi
View File

@@ -42,6 +42,252 @@ aliases {
rdma1 = &rdma1;
};
cluster0_opp: opp-table-cluster0 {
compatible = "operating-points-v2";
opp-shared;
opp0-793000000 {
opp-hz = /bits/ 64 <793000000>;
opp-microvolt = <650000>;
required-opps = <&opp2_00>;
};
opp0-910000000 {
opp-hz = /bits/ 64 <910000000>;
opp-microvolt = <687500>;
required-opps = <&opp2_01>;
};
opp0-1014000000 {
opp-hz = /bits/ 64 <1014000000>;
opp-microvolt = <718750>;
required-opps = <&opp2_02>;
};
opp0-1131000000 {
opp-hz = /bits/ 64 <1131000000>;
opp-microvolt = <756250>;
required-opps = <&opp2_03>;
};
opp0-1248000000 {
opp-hz = /bits/ 64 <1248000000>;
opp-microvolt = <800000>;
required-opps = <&opp2_04>;
};
opp0-1326000000 {
opp-hz = /bits/ 64 <1326000000>;
opp-microvolt = <818750>;
required-opps = <&opp2_05>;
};
opp0-1417000000 {
opp-hz = /bits/ 64 <1417000000>;
opp-microvolt = <850000>;
required-opps = <&opp2_06>;
};
opp0-1508000000 {
opp-hz = /bits/ 64 <1508000000>;
opp-microvolt = <868750>;
required-opps = <&opp2_07>;
};
opp0-1586000000 {
opp-hz = /bits/ 64 <1586000000>;
opp-microvolt = <893750>;
required-opps = <&opp2_08>;
};
opp0-1625000000 {
opp-hz = /bits/ 64 <1625000000>;
opp-microvolt = <906250>;
required-opps = <&opp2_09>;
};
opp0-1677000000 {
opp-hz = /bits/ 64 <1677000000>;
opp-microvolt = <931250>;
required-opps = <&opp2_10>;
};
opp0-1716000000 {
opp-hz = /bits/ 64 <1716000000>;
opp-microvolt = <943750>;
required-opps = <&opp2_11>;
};
opp0-1781000000 {
opp-hz = /bits/ 64 <1781000000>;
opp-microvolt = <975000>;
required-opps = <&opp2_12>;
};
opp0-1846000000 {
opp-hz = /bits/ 64 <1846000000>;
opp-microvolt = <1000000>;
required-opps = <&opp2_13>;
};
opp0-1924000000 {
opp-hz = /bits/ 64 <1924000000>;
opp-microvolt = <1025000>;
required-opps = <&opp2_14>;
};
opp0-1989000000 {
opp-hz = /bits/ 64 <1989000000>;
opp-microvolt = <1050000>;
required-opps = <&opp2_15>;
}; };
cluster1_opp: opp-table-cluster1 {
compatible = "operating-points-v2";
opp-shared;
opp1-793000000 {
opp-hz = /bits/ 64 <793000000>;
opp-microvolt = <700000>;
required-opps = <&opp2_00>;
};
opp1-910000000 {
opp-hz = /bits/ 64 <910000000>;
opp-microvolt = <725000>;
required-opps = <&opp2_01>;
};
opp1-1014000000 {
opp-hz = /bits/ 64 <1014000000>;
opp-microvolt = <750000>;
required-opps = <&opp2_02>;
};
opp1-1131000000 {
opp-hz = /bits/ 64 <1131000000>;
opp-microvolt = <775000>;
required-opps = <&opp2_03>;
};
opp1-1248000000 {
opp-hz = /bits/ 64 <1248000000>;
opp-microvolt = <800000>;
required-opps = <&opp2_04>;
};
opp1-1326000000 {
opp-hz = /bits/ 64 <1326000000>;
opp-microvolt = <825000>;
required-opps = <&opp2_05>;
};
opp1-1417000000 {
opp-hz = /bits/ 64 <1417000000>;
opp-microvolt = <850000>;
required-opps = <&opp2_06>;
};
opp1-1508000000 {
opp-hz = /bits/ 64 <1508000000>;
opp-microvolt = <875000>;
required-opps = <&opp2_07>;
};
opp1-1586000000 {
opp-hz = /bits/ 64 <1586000000>;
opp-microvolt = <900000>;
required-opps = <&opp2_08>;
};
opp1-1625000000 {
opp-hz = /bits/ 64 <1625000000>;
opp-microvolt = <912500>;
required-opps = <&opp2_09>;
};
opp1-1677000000 {
opp-hz = /bits/ 64 <1677000000>;
opp-microvolt = <931250>;
required-opps = <&opp2_10>;
};
opp1-1716000000 {
opp-hz = /bits/ 64 <1716000000>;
opp-microvolt = <950000>;
required-opps = <&opp2_11>;
};
opp1-1781000000 {
opp-hz = /bits/ 64 <1781000000>;
opp-microvolt = <975000>;
required-opps = <&opp2_12>;
};
opp1-1846000000 {
opp-hz = /bits/ 64 <1846000000>;
opp-microvolt = <1000000>;
required-opps = <&opp2_13>;
};
opp1-1924000000 {
opp-hz = /bits/ 64 <1924000000>;
opp-microvolt = <1025000>;
required-opps = <&opp2_14>;
};
opp1-1989000000 {
opp-hz = /bits/ 64 <1989000000>;
opp-microvolt = <1050000>;
required-opps = <&opp2_15>;
};
};
cci_opp: opp-table-cci {
compatible = "operating-points-v2";
opp-shared;
opp2_00: opp-273000000 {
opp-hz = /bits/ 64 <273000000>;
opp-microvolt = <650000>;
};
opp2_01: opp-338000000 {
opp-hz = /bits/ 64 <338000000>;
opp-microvolt = <687500>;
};
opp2_02: opp-403000000 {
opp-hz = /bits/ 64 <403000000>;
opp-microvolt = <718750>;
};
opp2_03: opp-463000000 {
opp-hz = /bits/ 64 <463000000>;
opp-microvolt = <756250>;
};
opp2_04: opp-546000000 {
opp-hz = /bits/ 64 <546000000>;
opp-microvolt = <800000>;
};
opp2_05: opp-624000000 {
opp-hz = /bits/ 64 <624000000>;
opp-microvolt = <818750>;
};
opp2_06: opp-689000000 {
opp-hz = /bits/ 64 <689000000>;
opp-microvolt = <850000>;
};
opp2_07: opp-767000000 {
opp-hz = /bits/ 64 <767000000>;
opp-microvolt = <868750>;
};
opp2_08: opp-845000000 {
opp-hz = /bits/ 64 <845000000>;
opp-microvolt = <893750>;
};
opp2_09: opp-871000000 {
opp-hz = /bits/ 64 <871000000>;
opp-microvolt = <906250>;
};
opp2_10: opp-923000000 {
opp-hz = /bits/ 64 <923000000>;
opp-microvolt = <931250>;
};
opp2_11: opp-962000000 {
opp-hz = /bits/ 64 <962000000>;
opp-microvolt = <943750>;
};
opp2_12: opp-1027000000 {
opp-hz = /bits/ 64 <1027000000>;
opp-microvolt = <975000>;
};
opp2_13: opp-1092000000 {
opp-hz = /bits/ 64 <1092000000>;
opp-microvolt = <1000000>;
};
opp2_14: opp-1144000000 {
opp-hz = /bits/ 64 <1144000000>;
opp-microvolt = <1025000>;
};
opp2_15: opp-1196000000 {
opp-hz = /bits/ 64 <1196000000>;
opp-microvolt = <1050000>;
};
};
cci: cci {
compatible = "mediatek,mt8183-cci";
clocks = <&mcucfg CLK_MCU_BUS_SEL>,
<&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
clock-names = "cci", "intermediate";
operating-points-v2 = <&cci_opp>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -85,8 +331,13 @@ cpu0: cpu@0 {
enable-method = "psci";
capacity-dmips-mhz = <741>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
clocks = <&mcucfg CLK_MCU_MP0_SEL>,
<&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
#cooling-cells = <2>;
mediatek,cci = <&cci>;
};
cpu1: cpu@1 {
@@ -96,8 +347,13 @@ cpu1: cpu@1 {
enable-method = "psci";
capacity-dmips-mhz = <741>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
clocks = <&mcucfg CLK_MCU_MP0_SEL>,
<&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
#cooling-cells = <2>;
mediatek,cci = <&cci>;
};
cpu2: cpu@2 {
@@ -107,8 +363,13 @@ cpu2: cpu@2 {
enable-method = "psci";
capacity-dmips-mhz = <741>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
clocks = <&mcucfg CLK_MCU_MP0_SEL>,
<&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
#cooling-cells = <2>;
mediatek,cci = <&cci>;
};
cpu3: cpu@3 {
@@ -118,8 +379,13 @@ cpu3: cpu@3 {
enable-method = "psci";
capacity-dmips-mhz = <741>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
clocks = <&mcucfg CLK_MCU_MP0_SEL>,
<&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
#cooling-cells = <2>;
mediatek,cci = <&cci>;
};
cpu4: cpu@100 {
@@ -129,8 +395,13 @@ cpu4: cpu@100 {
enable-method = "psci";
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
clocks = <&mcucfg CLK_MCU_MP2_SEL>,
<&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
#cooling-cells = <2>;
mediatek,cci = <&cci>;
};
cpu5: cpu@101 {
@@ -140,8 +411,13 @@ cpu5: cpu@101 {
enable-method = "psci";
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
clocks = <&mcucfg CLK_MCU_MP2_SEL>,
<&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
#cooling-cells = <2>;
mediatek,cci = <&cci>;
};
cpu6: cpu@102 {
@@ -151,8 +427,13 @@ cpu6: cpu@102 {
enable-method = "psci";
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
clocks = <&mcucfg CLK_MCU_MP2_SEL>,
<&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
#cooling-cells = <2>;
mediatek,cci = <&cci>;
};
cpu7: cpu@103 {
@@ -162,8 +443,13 @@ cpu7: cpu@103 {
enable-method = "psci";
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
clocks = <&mcucfg CLK_MCU_MP2_SEL>,
<&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
#cooling-cells = <2>;
mediatek,cci = <&cci>;
};
idle-states {
@@ -295,8 +581,8 @@ pmu-a73 {
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
compatible = "arm,psci-1.0";
method = "smc";
};
clk26m: oscillator {
@@ -321,7 +607,7 @@ soc {
compatible = "simple-bus";
ranges;
soc_data: soc_data@8000000 {
soc_data: efuse@8000000 {
compatible = "mediatek,mt8183-efuse",
"mediatek,efuse";
reg = <0 0x08000000 0 0x0010>;
@@ -502,9 +788,9 @@ power-domain@MT8183_POWER_DOMAIN_CONN {
#power-domain-cells = <0>;
};
power-domain@MT8183_POWER_DOMAIN_MFG_ASYNC {
mfg_async: power-domain@MT8183_POWER_DOMAIN_MFG_ASYNC {
reg = <MT8183_POWER_DOMAIN_MFG_ASYNC>;
clocks = <&topckgen CLK_TOP_MUX_MFG>;
clocks = <&topckgen CLK_TOP_MUX_MFG>;
clock-names = "mfg";
#address-cells = <1>;
#size-cells = <0>;
@@ -807,6 +1093,18 @@ spi0: spi@1100a000 {
status = "disabled";
};
svs: svs@1100b000 {
compatible = "mediatek,mt8183-svs";
reg = <0 0x1100b000 0 0x1000>;
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_INFRA_THERM>;
clock-names = "main";
nvmem-cells = <&svs_calibration>,
<&thermal_calibration>;
nvmem-cell-names = "svs-calibration-data",
"t-calibration-data";
};
thermal: thermal@1100b000 {
#thermal-sensor-cells = <1>;
compatible = "mediatek,mt8183-thermal";
@@ -1150,7 +1448,7 @@ i2c8: i2c@1101b000 {
};
ssusb: usb@11201000 {
compatible ="mediatek,mt8183-mtu3", "mediatek,mtu3";
compatible = "mediatek,mt8183-mtu3", "mediatek,mtu3";
reg = <0 0x11201000 0 0x2e00>,
<0 0x11203e00 0 0x0100>;
reg-names = "mac", "ippc";
@@ -1325,6 +1623,10 @@ thermal_calibration: calib@180 {
mipi_tx_calibration: calib@190 {
reg = <0x190 0xc>;
};
svs_calibration: calib@580 {
reg = <0x580 0x64>;
};
};
u3phy: t-phy@11f40000 {
@@ -1508,6 +1810,7 @@ mutex: mutex@14016000 {
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
<CMDQ_EVENT_MUTEX_STREAM_DONE1>;
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
};
larb0: larb@14017000 {

47
arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts Normal file
View File

@@ -0,0 +1,47 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2020 Google LLC
*/
/dts-v1/;
#include "mt8192-asurada.dtsi"
/ {
model = "Google Hayato rev1";
compatible = "google,hayato-rev1", "google,hayato", "mediatek,mt8192";
};
&keyboard_controller {
function-row-physmap = <
MATRIX_KEY(0x00, 0x02, 0) /* T1 */
MATRIX_KEY(0x03, 0x02, 0) /* T2 */
MATRIX_KEY(0x02, 0x02, 0) /* T3 */
MATRIX_KEY(0x01, 0x02, 0) /* T4 */
MATRIX_KEY(0x03, 0x04, 0) /* T5 */
MATRIX_KEY(0x02, 0x04, 0) /* T6 */
MATRIX_KEY(0x01, 0x04, 0) /* T7 */
MATRIX_KEY(0x02, 0x09, 0) /* T8 */
MATRIX_KEY(0x01, 0x09, 0) /* T9 */
MATRIX_KEY(0x00, 0x04, 0) /* T10 */
>;
linux,keymap = <
MATRIX_KEY(0x00, 0x02, KEY_BACK)
MATRIX_KEY(0x03, 0x02, KEY_FORWARD)
MATRIX_KEY(0x02, 0x02, KEY_REFRESH)
MATRIX_KEY(0x01, 0x02, KEY_FULL_SCREEN)
MATRIX_KEY(0x03, 0x04, KEY_SCALE)
MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN)
MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP)
MATRIX_KEY(0x02, 0x09, KEY_MUTE)
MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)
MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)
CROS_STD_MAIN_KEYMAP
>;
};
&touchscreen {
compatible = "hid-over-i2c";
post-power-on-delay-ms = <10>;
hid-descr-addr = <0x0001>;
vdd-supply = <&pp3300_u>;
};

62
arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts Normal file
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@@ -0,0 +1,62 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2021 Google LLC
*/
/dts-v1/;
#include "mt8192-asurada.dtsi"
#include <dt-bindings/leds/common.h>
/ {
model = "Google Spherion (rev0 - 3)";
compatible = "google,spherion-rev3", "google,spherion-rev2",
"google,spherion-rev1", "google,spherion-rev0",
"google,spherion", "mediatek,mt8192";
pwmleds {
compatible = "pwm-leds";
led {
function = LED_FUNCTION_KBD_BACKLIGHT;
color = <LED_COLOR_ID_WHITE>;
pwms = <&cros_ec_pwm 0>;
max-brightness = <1023>;
};
};
};
&cros_ec_pwm {
status = "okay";
};
&keyboard_controller {
function-row-physmap = <
MATRIX_KEY(0x00, 0x02, 0) /* T1 */
MATRIX_KEY(0x03, 0x02, 0) /* T2 */
MATRIX_KEY(0x02, 0x02, 0) /* T3 */
MATRIX_KEY(0x01, 0x02, 0) /* T4 */
MATRIX_KEY(0x03, 0x04, 0) /* T5 */
MATRIX_KEY(0x02, 0x04, 0) /* T6 */
MATRIX_KEY(0x01, 0x04, 0) /* T7 */
MATRIX_KEY(0x02, 0x09, 0) /* T8 */
MATRIX_KEY(0x01, 0x09, 0) /* T9 */
MATRIX_KEY(0x00, 0x04, 0) /* T10 */
>;
linux,keymap = <
MATRIX_KEY(0x00, 0x02, KEY_BACK)
MATRIX_KEY(0x03, 0x02, KEY_REFRESH)
MATRIX_KEY(0x02, 0x02, KEY_FULL_SCREEN)
MATRIX_KEY(0x01, 0x02, KEY_SCALE)
MATRIX_KEY(0x03, 0x04, KEY_SYSRQ)
MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN)
MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP)
MATRIX_KEY(0x02, 0x09, KEY_MUTE)
MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)
MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)
CROS_STD_MAIN_KEYMAP
>;
};
&touchscreen {
compatible = "elan,ekth3500";
};

959
arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi Normal file
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2020 MediaTek Inc.
* Author: Seiya Wang <seiya.wang@mediatek.com>
*/
/dts-v1/;
#include "mt8192.dtsi"
#include "mt6359.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/spmi/spmi.h>
/ {
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0 0x80000000>;
};
/* system wide LDO 1.8V power rail */
pp1800_ldo_g: regulator-1v8-g {
compatible = "regulator-fixed";
regulator-name = "pp1800_ldo_g";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&pp3300_g>;
};
/* system wide switching 3.3V power rail */
pp3300_g: regulator-3v3-g {
compatible = "regulator-fixed";
regulator-name = "pp3300_g";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&ppvar_sys>;
};
/* system wide LDO 3.3V power rail */
pp3300_ldo_z: regulator-3v3-z {
compatible = "regulator-fixed";
regulator-name = "pp3300_ldo_z";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&ppvar_sys>;
};
/* separately switched 3.3V power rail */
pp3300_u: regulator-3v3-u {
compatible = "regulator-fixed";
regulator-name = "pp3300_u";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
/* enable pin wired to GPIO controlled by EC */
vin-supply = <&pp3300_g>;
};
pp3300_wlan: regulator-3v3-wlan {
compatible = "regulator-fixed";
regulator-name = "pp3300_wlan";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
pinctrl-names = "default";
pinctrl-0 = <&pp3300_wlan_pins>;
enable-active-high;
gpio = <&pio 143 GPIO_ACTIVE_HIGH>;
};
/* system wide switching 5.0V power rail */
pp5000_a: regulator-5v0-a {
compatible = "regulator-fixed";
regulator-name = "pp5000_a";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&ppvar_sys>;
};
/* system wide semi-regulated power rail from battery or USB */
ppvar_sys: regulator-var-sys {
compatible = "regulator-fixed";
regulator-name = "ppvar_sys";
regulator-always-on;
regulator-boot-on;
};
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
scp_mem_reserved: scp@50000000 {
compatible = "shared-dma-pool";
reg = <0 0x50000000 0 0x2900000>;
no-map;
};
wifi_restricted_dma_region: wifi@c0000000 {
compatible = "restricted-dma-pool";
reg = <0 0xc0000000 0 0x4000000>;
};
};
};
&i2c0 {
status = "okay";
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
touchscreen: touchscreen@10 {
reg = <0x10>;
interrupts-extended = <&pio 21 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&touchscreen_pins>;
};
};
&i2c1 {
status = "okay";
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
};
&i2c2 {
status = "okay";
clock-frequency = <400000>;
clock-stretch-ns = <12600>;
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
trackpad@15 {
compatible = "elan,ekth3000";
reg = <0x15>;
interrupts-extended = <&pio 15 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&trackpad_pins>;
vcc-supply = <&pp3300_u>;
wakeup-source;
};
};
&i2c3 {
status = "okay";
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&i2c3_pins>;
};
&i2c7 {
status = "okay";
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&i2c7_pins>;
};
&mmc0 {
status = "okay";
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&mmc0_default_pins>;
pinctrl-1 = <&mmc0_uhs_pins>;
bus-width = <8>;
max-frequency = <200000000>;
vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
vqmmc-supply = <&mt6359_vufs_ldo_reg>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
supports-cqe;
cap-mmc-hw-reset;
mmc-hs400-enhanced-strobe;
hs400-ds-delay = <0x12814>;
no-sdio;
no-sd;
non-removable;
};
&mmc1 {
status = "okay";
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&mmc1_default_pins>;
pinctrl-1 = <&mmc1_uhs_pins>;
bus-width = <4>;
max-frequency = <200000000>;
cd-gpios = <&pio 17 GPIO_ACTIVE_LOW>;
vmmc-supply = <&mt6360_ldo5_reg>;
vqmmc-supply = <&mt6360_ldo3_reg>;
cap-sd-highspeed;
sd-uhs-sdr50;
sd-uhs-sdr104;
no-sdio;
no-mmc;
};
/* for CORE */
&mt6359_vgpu11_buck_reg {
regulator-always-on;
};
&mt6359_vgpu11_sshub_buck_reg {
regulator-always-on;
regulator-min-microvolt = <575000>;
regulator-max-microvolt = <575000>;
};
&mt6359_vrf12_ldo_reg {
regulator-always-on;
};
&mt6359_vufs_ldo_reg {
regulator-always-on;
};
&mt6359codec {
mediatek,dmic-mode = <1>; /* one-wire */
mediatek,mic-type-0 = <2>; /* DMIC */
mediatek,mic-type-2 = <2>; /* DMIC */
};
&nor_flash {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&nor_flash_pins>;
assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6_D8>;
flash@0 {
compatible = "winbond,w25q64jwm", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <52000000>;
spi-rx-bus-width = <2>;
spi-tx-bus-width = <2>;
};
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pcie_pins>;
pcie0: pcie@0,0 {
device_type = "pci";
reg = <0x0000 0 0 0 0>;
num-lanes = <1>;
bus-range = <0x1 0x1>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi: wifi@0,0 {
reg = <0x10000 0 0 0 0x100000>,
<0x10000 0 0x100000 0 0x100000>;
memory-region = <&wifi_restricted_dma_region>;
};
};
};
&pio {
/* 220 lines */
gpio-line-names = "I2S_DP_LRCK",
"IS_DP_BCLK",
"I2S_DP_MCLK",
"I2S_DP_DATAOUT",
"SAR0_INT_ODL",
"EC_AP_INT_ODL",
"EDPBRDG_INT_ODL",
"DPBRDG_INT_ODL",
"DPBRDG_PWREN",
"DPBRDG_RST_ODL",
"I2S_HP_MCLK",
"I2S_HP_BCK",
"I2S_HP_LRCK",
"I2S_HP_DATAIN",
/*
* AP_FLASH_WP_L is crossystem ABI. Schematics
* call it AP_FLASH_WP_ODL.
*/
"AP_FLASH_WP_L",
"TRACKPAD_INT_ODL",
"EC_AP_HPD_OD",
"SD_CD_ODL",
"HP_INT_ODL_ALC",
"EN_PP1000_DPBRDG",
"AP_GPIO20",
"TOUCH_INT_L_1V8",
"UART_BT_WAKE_ODL",
"AP_GPIO23",
"AP_SPI_FLASH_CS_L",
"AP_SPI_FLASH_CLK",
"EN_PP3300_DPBRDG_DX",
"AP_SPI_FLASH_MOSI",
"AP_SPI_FLASH_MISO",
"I2S_HP_DATAOUT",
"AP_GPIO30",
"I2S_SPKR_MCLK",
"I2S_SPKR_BCLK",
"I2S_SPKR_LRCK",
"I2S_SPKR_DATAIN",
"I2S_SPKR_DATAOUT",
"AP_SPI_H1_TPM_CLK",
"AP_SPI_H1_TPM_CS_L",
"AP_SPI_H1_TPM_MISO",
"AP_SPI_H1_TPM_MOSI",
"BL_PWM",
"EDPBRDG_PWREN",
"EDPBRDG_RST_ODL",
"EN_PP3300_HUB",
"HUB_RST_L",
"",
"",
"",
"",
"",
"",
"SD_CLK",
"SD_CMD",
"SD_DATA3",
"SD_DATA0",
"SD_DATA2",
"SD_DATA1",
"",
"",
"",
"",
"",
"",
"PCIE_WAKE_ODL",
"PCIE_RST_L",
"PCIE_CLKREQ_ODL",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"SPMI_SCL",
"SPMI_SDA",
"AP_GOOD",
"UART_DBG_TX_AP_RX",
"UART_AP_TX_DBG_RX",
"UART_AP_TX_BT_RX",
"UART_BT_TX_AP_RX",
"MIPI_DPI_D0_R",
"MIPI_DPI_D1_R",
"MIPI_DPI_D2_R",
"MIPI_DPI_D3_R",
"MIPI_DPI_D4_R",
"MIPI_DPI_D5_R",
"MIPI_DPI_D6_R",
"MIPI_DPI_D7_R",
"MIPI_DPI_D8_R",
"MIPI_DPI_D9_R",
"MIPI_DPI_D10_R",
"",
"",
"MIPI_DPI_DE_R",
"MIPI_DPI_D11_R",
"MIPI_DPI_VSYNC_R",
"MIPI_DPI_CLK_R",
"MIPI_DPI_HSYNC_R",
"PCM_BT_DATAIN",
"PCM_BT_SYNC",
"PCM_BT_DATAOUT",
"PCM_BT_CLK",
"AP_I2C_AUDIO_SCL",
"AP_I2C_AUDIO_SDA",
"SCP_I2C_SCL",
"SCP_I2C_SDA",
"AP_I2C_WLAN_SCL",
"AP_I2C_WLAN_SDA",
"AP_I2C_DPBRDG_SCL",
"AP_I2C_DPBRDG_SDA",
"EN_PP1800_DPBRDG_DX",
"EN_PP3300_EDP_DX",
"EN_PP1800_EDPBRDG_DX",
"EN_PP1000_EDPBRDG",
"SCP_JTAG0_TDO",
"SCP_JTAG0_TDI",
"SCP_JTAG0_TMS",
"SCP_JTAG0_TCK",
"SCP_JTAG0_TRSTN",
"EN_PP3000_VMC_PMU",
"EN_PP3300_DISPLAY_DX",
"TOUCH_RST_L_1V8",
"TOUCH_REPORT_DISABLE",
"",
"",
"AP_I2C_TRACKPAD_SCL_1V8",
"AP_I2C_TRACKPAD_SDA_1V8",
"EN_PP3300_WLAN",
"BT_KILL_L",
"WIFI_KILL_L",
"SET_VMC_VOLT_AT_1V8",
"EN_SPK",
"AP_WARM_RST_REQ",
"",
"",
"EN_PP3000_SD_S3",
"AP_EDP_BKLTEN",
"",
"",
"",
"AP_SPI_EC_CLK",
"AP_SPI_EC_CS_L",
"AP_SPI_EC_MISO",
"AP_SPI_EC_MOSI",
"AP_I2C_EDPBRDG_SCL",
"AP_I2C_EDPBRDG_SDA",
"MT6315_PROC_INT",
"MT6315_GPU_INT",
"UART_SERVO_TX_SCP_RX",
"UART_SCP_TX_SERVO_RX",
"BT_RTS_AP_CTS",
"AP_RTS_BT_CTS",
"UART_AP_WAKE_BT_ODL",
"WLAN_ALERT_ODL",
"EC_IN_RW_ODL",
"H1_AP_INT_ODL",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"MSDC0_CMD",
"MSDC0_DAT0",
"MSDC0_DAT2",
"MSDC0_DAT4",
"MSDC0_DAT6",
"MSDC0_DAT1",
"MSDC0_DAT5",
"MSDC0_DAT7",
"MSDC0_DSL",
"MSDC0_CLK",
"MSDC0_DAT3",
"MSDC0_RST_L",
"SCP_VREQ_VAO",
"AUD_DAT_MOSI2",
"AUD_NLE_MOSI1",
"AUD_NLE_MOSI0",
"AUD_DAT_MISO2",
"AP_I2C_SAR_SDA",
"AP_I2C_SAR_SCL",
"AP_I2C_PWR_SCL",
"AP_I2C_PWR_SDA",
"AP_I2C_TS_SCL_1V8",
"AP_I2C_TS_SDA_1V8",
"SRCLKENA0",
"SRCLKENA1",
"AP_EC_WATCHDOG_L",
"PWRAP_SPI0_MI",
"PWRAP_SPI0_CSN",
"PWRAP_SPI0_MO",
"PWRAP_SPI0_CK",
"AP_RTC_CLK32K",
"AUD_CLK_MOSI",
"AUD_SYNC_MOSI",
"AUD_DAT_MOSI0",
"AUD_DAT_MOSI1",
"AUD_DAT_MISO0",
"AUD_DAT_MISO1";
cr50_int: cr50-irq-default-pins {
pins-gsc-ap-int-odl {
pinmux = <PINMUX_GPIO171__FUNC_GPIO171>;
input-enable;
};
};
cros_ec_int: cros-ec-irq-default-pins {
pins-ec-ap-int-odl {
pinmux = <PINMUX_GPIO5__FUNC_GPIO5>;
input-enable;
bias-pull-up;
};
};
i2c0_pins: i2c0-default-pins {
pins-bus {
pinmux = <PINMUX_GPIO204__FUNC_SCL0>,
<PINMUX_GPIO205__FUNC_SDA0>;
bias-pull-up = <MTK_PULL_SET_RSEL_011>;
drive-strength-microamp = <1000>;
};
};
i2c1_pins: i2c1-default-pins {
pins-bus {
pinmux = <PINMUX_GPIO118__FUNC_SCL1>,
<PINMUX_GPIO119__FUNC_SDA1>;
bias-pull-up = <MTK_PULL_SET_RSEL_011>;
drive-strength-microamp = <1000>;
};
};
i2c2_pins: i2c2-default-pins {
pins-bus {
pinmux = <PINMUX_GPIO141__FUNC_SCL2>,
<PINMUX_GPIO142__FUNC_SDA2>;
bias-pull-up = <MTK_PULL_SET_RSEL_011>;
};
};
i2c3_pins: i2c3-default-pins {
pins-bus {
pinmux = <PINMUX_GPIO160__FUNC_SCL3>,
<PINMUX_GPIO161__FUNC_SDA3>;
bias-disable;
drive-strength-microamp = <1000>;
};
};
i2c7_pins: i2c7-default-pins {
pins-bus {
pinmux = <PINMUX_GPIO124__FUNC_SCL7>,
<PINMUX_GPIO125__FUNC_SDA7>;
bias-disable;
drive-strength-microamp = <1000>;
};
};
mmc0_default_pins: mmc0-default-pins {
pins-cmd-dat {
pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>,
<PINMUX_GPIO188__FUNC_MSDC0_DAT1>,
<PINMUX_GPIO185__FUNC_MSDC0_DAT2>,
<PINMUX_GPIO193__FUNC_MSDC0_DAT3>,
<PINMUX_GPIO186__FUNC_MSDC0_DAT4>,
<PINMUX_GPIO189__FUNC_MSDC0_DAT5>,
<PINMUX_GPIO187__FUNC_MSDC0_DAT6>,
<PINMUX_GPIO190__FUNC_MSDC0_DAT7>,
<PINMUX_GPIO183__FUNC_MSDC0_CMD>;
input-enable;
drive-strength = <8>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins-clk {
pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>;
drive-strength = <8>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
pins-rst {
pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>;
drive-strength = <8>;
bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
};
};
mmc0_uhs_pins: mmc0-uhs-pins {
pins-cmd-dat {
pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>,
<PINMUX_GPIO188__FUNC_MSDC0_DAT1>,
<PINMUX_GPIO185__FUNC_MSDC0_DAT2>,
<PINMUX_GPIO193__FUNC_MSDC0_DAT3>,
<PINMUX_GPIO186__FUNC_MSDC0_DAT4>,
<PINMUX_GPIO189__FUNC_MSDC0_DAT5>,
<PINMUX_GPIO187__FUNC_MSDC0_DAT6>,
<PINMUX_GPIO190__FUNC_MSDC0_DAT7>,
<PINMUX_GPIO183__FUNC_MSDC0_CMD>;
input-enable;
drive-strength = <10>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins-clk {
pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>;
drive-strength = <10>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
pins-rst {
pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>;
drive-strength = <8>;
bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
};
pins-ds {
pinmux = <PINMUX_GPIO191__FUNC_MSDC0_DSL>;
drive-strength = <10>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
};
mmc1_default_pins: mmc1-default-pins {
pins-cmd-dat {
pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>,
<PINMUX_GPIO56__FUNC_MSDC1_DAT1>,
<PINMUX_GPIO55__FUNC_MSDC1_DAT2>,
<PINMUX_GPIO53__FUNC_MSDC1_DAT3>,
<PINMUX_GPIO52__FUNC_MSDC1_CMD>;
input-enable;
drive-strength = <8>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins-clk {
pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>;
drive-strength = <8>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
pins-insert {
pinmux = <PINMUX_GPIO17__FUNC_GPIO17>;
input-enable;
bias-pull-up;
};
};
mmc1_uhs_pins: mmc1-uhs-pins {
pins-cmd-dat {
pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>,
<PINMUX_GPIO56__FUNC_MSDC1_DAT1>,
<PINMUX_GPIO55__FUNC_MSDC1_DAT2>,
<PINMUX_GPIO53__FUNC_MSDC1_DAT3>,
<PINMUX_GPIO52__FUNC_MSDC1_CMD>;
input-enable;
drive-strength = <8>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins-clk {
pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>;
input-enable;
drive-strength = <8>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
};
nor_flash_pins: nor-flash-default-pins {
pins-cs-io1 {
pinmux = <PINMUX_GPIO24__FUNC_SPINOR_CS>,
<PINMUX_GPIO28__FUNC_SPINOR_IO1>;
input-enable;
bias-pull-up;
drive-strength = <10>;
};
pins-io0 {
pinmux = <PINMUX_GPIO27__FUNC_SPINOR_IO0>;
bias-pull-up;
drive-strength = <10>;
};
pins-clk {
pinmux = <PINMUX_GPIO25__FUNC_SPINOR_CK>;
input-enable;
bias-pull-up;
drive-strength = <10>;
};
};
pcie_pins: pcie-default-pins {
pins-pcie-wake {
pinmux = <PINMUX_GPIO63__FUNC_PCIE_WAKE_N>;
bias-pull-up;
};
pins-pcie-pereset {
pinmux = <PINMUX_GPIO64__FUNC_PCIE_PERESET_N>;
};
pins-pcie-clkreq {
pinmux = <PINMUX_GPIO65__FUNC_PCIE_CLKREQ_N>;
bias-pull-up;
};
pins-wifi-kill {
pinmux = <PINMUX_GPIO145__FUNC_GPIO145>; /* WIFI_KILL_L */
output-high;
};
};
pp3300_wlan_pins: pp3300-wlan-pins {
pins-pcie-en-pp3300-wlan {
pinmux = <PINMUX_GPIO143__FUNC_GPIO143>;
output-high;
};
};
scp_pins: scp-pins {
pins-vreq-vao {
pinmux = <PINMUX_GPIO195__FUNC_SCP_VREQ_VAO>;
};
};
spi1_pins: spi1-default-pins {
pins-cs-mosi-clk {
pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>,
<PINMUX_GPIO159__FUNC_SPI1_A_MO>,
<PINMUX_GPIO156__FUNC_SPI1_A_CLK>;
bias-disable;
};
pins-miso {
pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>;
bias-pull-down;
};
};
spi5_pins: spi5-default-pins {
pins-bus {
pinmux = <PINMUX_GPIO38__FUNC_SPI5_A_MI>,
<PINMUX_GPIO37__FUNC_GPIO37>,
<PINMUX_GPIO39__FUNC_SPI5_A_MO>,
<PINMUX_GPIO36__FUNC_SPI5_A_CLK>;
bias-disable;
};
};
trackpad_pins: trackpad-default-pins {
pins-int-n {
pinmux = <PINMUX_GPIO15__FUNC_GPIO15>;
input-enable;
bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
};
};
touchscreen_pins: touchscreen-default-pins {
pins-irq {
pinmux = <PINMUX_GPIO21__FUNC_GPIO21>;
input-enable;
bias-pull-up;
};
pins-reset {
pinmux = <PINMUX_GPIO137__FUNC_GPIO137>;
output-high;
};
pins-report-sw {
pinmux = <PINMUX_GPIO138__FUNC_GPIO138>;
output-low;
};
};
};
&pmic {
interrupts-extended = <&pio 214 IRQ_TYPE_LEVEL_HIGH>;
};
&scp {
status = "okay";
firmware-name = "mediatek/mt8192/scp.img";
memory-region = <&scp_mem_reserved>;
pinctrl-names = "default";
pinctrl-0 = <&scp_pins>;
cros-ec {
compatible = "google,cros-ec-rpmsg";
mediatek,rpmsg-name = "cros-ec-rpmsg";
};
};
&spi1 {
status = "okay";
mediatek,pad-select = <0>;
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins>;
cros_ec: ec@0 {
compatible = "google,cros-ec-spi";
reg = <0>;
interrupts-extended = <&pio 5 IRQ_TYPE_LEVEL_LOW>;
spi-max-frequency = <3000000>;
pinctrl-names = "default";
pinctrl-0 = <&cros_ec_int>;
#address-cells = <1>;
#size-cells = <0>;
base_detection: cbas {
compatible = "google,cros-cbas";
};
cros_ec_pwm: pwm {
compatible = "google,cros-ec-pwm";
#pwm-cells = <1>;
status = "disabled";
};
i2c_tunnel: i2c-tunnel {
compatible = "google,cros-ec-i2c-tunnel";
google,remote-bus = <0>;
#address-cells = <1>;
#size-cells = <0>;
};
mt6360_ldo3_reg: regulator@0 {
compatible = "google,cros-ec-regulator";
reg = <0>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
mt6360_ldo5_reg: regulator@1 {
compatible = "google,cros-ec-regulator";
reg = <1>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
typec {
compatible = "google,cros-ec-typec";
#address-cells = <1>;
#size-cells = <0>;
usb_c0: connector@0 {
compatible = "usb-c-connector";
reg = <0>;
label = "left";
power-role = "dual";
data-role = "host";
try-power-role = "source";
};
usb_c1: connector@1 {
compatible = "usb-c-connector";
reg = <1>;
label = "right";
power-role = "dual";
data-role = "host";
try-power-role = "source";
};
};
};
};
&spi5 {
status = "okay";
cs-gpios = <&pio 37 GPIO_ACTIVE_LOW>;
mediatek,pad-select = <0>;
pinctrl-names = "default";
pinctrl-0 = <&spi5_pins>;
cr50@0 {
compatible = "google,cr50";
reg = <0>;
interrupts-extended = <&pio 171 IRQ_TYPE_EDGE_RISING>;
spi-max-frequency = <1000000>;
pinctrl-names = "default";
pinctrl-0 = <&cr50_int>;
};
};
&spmi {
#address-cells = <2>;
#size-cells = <0>;
mt6315_6: pmic@6 {
compatible = "mediatek,mt6315-regulator";
reg = <0x6 SPMI_USID>;
regulators {
mt6315_6_vbuck1: vbuck1 {
regulator-compatible = "vbuck1";
regulator-name = "Vbcpu";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1193750>;
regulator-enable-ramp-delay = <256>;
regulator-allowed-modes = <0 1 2>;
regulator-always-on;
};
mt6315_6_vbuck3: vbuck3 {
regulator-compatible = "vbuck3";
regulator-name = "Vlcpu";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1193750>;
regulator-enable-ramp-delay = <256>;
regulator-allowed-modes = <0 1 2>;
regulator-always-on;
};
};
};
mt6315_7: pmic@7 {
compatible = "mediatek,mt6315-regulator";
reg = <0x7 SPMI_USID>;
regulators {
mt6315_7_vbuck1: vbuck1 {
regulator-compatible = "vbuck1";
regulator-name = "Vgpu";
regulator-min-microvolt = <606250>;
regulator-max-microvolt = <1193750>;
regulator-enable-ramp-delay = <256>;
regulator-allowed-modes = <0 1 2>;
};
};
};
};
&uart0 {
status = "okay";
};
&xhci {
status = "okay";
wakeup-source;
vusb33-supply = <&pp3300_g>;
vbus-supply = <&pp5000_a>;
};
#include <arm/cros-ec-keyboard.dtsi>
#include <arm/cros-ec-sbs.dtsi>

29
arch/arm64/boot/dts/mediatek/mt8192.dtsi
View File

@@ -43,7 +43,7 @@ cpu0: cpu@0 {
reg = <0x000>;
enable-method = "psci";
clock-frequency = <1701000000>;
cpu-idle-states = <&cpuoff_l &clusteroff_l>;
cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <530>;
};
@@ -54,7 +54,7 @@ cpu1: cpu@100 {
reg = <0x100>;
enable-method = "psci";
clock-frequency = <1701000000>;
cpu-idle-states = <&cpuoff_l &clusteroff_l>;
cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <530>;
};
@@ -65,7 +65,7 @@ cpu2: cpu@200 {
reg = <0x200>;
enable-method = "psci";
clock-frequency = <1701000000>;
cpu-idle-states = <&cpuoff_l &clusteroff_l>;
cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <530>;
};
@@ -76,7 +76,7 @@ cpu3: cpu@300 {
reg = <0x300>;
enable-method = "psci";
clock-frequency = <1701000000>;
cpu-idle-states = <&cpuoff_l &clusteroff_l>;
cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <530>;
};
@@ -87,7 +87,7 @@ cpu4: cpu@400 {
reg = <0x400>;
enable-method = "psci";
clock-frequency = <2171000000>;
cpu-idle-states = <&cpuoff_b &clusteroff_b>;
cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
next-level-cache = <&l2_1>;
capacity-dmips-mhz = <1024>;
};
@@ -98,7 +98,7 @@ cpu5: cpu@500 {
reg = <0x500>;
enable-method = "psci";
clock-frequency = <2171000000>;
cpu-idle-states = <&cpuoff_b &clusteroff_b>;
cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
next-level-cache = <&l2_1>;
capacity-dmips-mhz = <1024>;
};
@@ -109,7 +109,7 @@ cpu6: cpu@600 {
reg = <0x600>;
enable-method = "psci";
clock-frequency = <2171000000>;
cpu-idle-states = <&cpuoff_b &clusteroff_b>;
cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
next-level-cache = <&l2_1>;
capacity-dmips-mhz = <1024>;
};
@@ -120,7 +120,7 @@ cpu7: cpu@700 {
reg = <0x700>;
enable-method = "psci";
clock-frequency = <2171000000>;
cpu-idle-states = <&cpuoff_b &clusteroff_b>;
cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
next-level-cache = <&l2_1>;
capacity-dmips-mhz = <1024>;
};
@@ -172,8 +172,8 @@ l3_0: l3-cache {
};
idle-states {
entry-method = "arm,psci";
cpuoff_l: cpuoff_l {
entry-method = "psci";
cpu_sleep_l: cpu-sleep-l {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x00010001>;
local-timer-stop;
@@ -181,7 +181,7 @@ cpuoff_l: cpuoff_l {
exit-latency-us = <140>;
min-residency-us = <780>;
};
cpuoff_b: cpuoff_b {
cpu_sleep_b: cpu-sleep-b {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x00010001>;
local-timer-stop;
@@ -189,7 +189,7 @@ cpuoff_b: cpuoff_b {
exit-latency-us = <145>;
min-residency-us = <720>;
};
clusteroff_l: clusteroff_l {
cluster_sleep_l: cluster-sleep-l {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x01010002>;
local-timer-stop;
@@ -197,7 +197,7 @@ clusteroff_l: clusteroff_l {
exit-latency-us = <155>;
min-residency-us = <860>;
};
clusteroff_b: clusteroff_b {
cluster_sleep_b: cluster-sleep-b {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x01010002>;
local-timer-stop;
@@ -271,6 +271,7 @@ infracfg: syscon@10001000 {
compatible = "mediatek,mt8192-infracfg", "syscon";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
pericfg: syscon@10003000 {
@@ -911,7 +912,7 @@ nor_flash: spi@11234000 {
};
efuse: efuse@11c10000 {
compatible = "mediatek,efuse";
compatible = "mediatek,mt8192-efuse", "mediatek,efuse";
reg = <0 0x11c10000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;

15
arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts Normal file
View File

@@ -0,0 +1,15 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2021 MediaTek Inc.
*/
/dts-v1/;
#include "mt8195-cherry.dtsi"
/ {
model = "Acer Tomato (rev1) board";
compatible = "google,tomato-rev1", "google,tomato", "mediatek,mt8195";
};
&ts_10 {
status = "okay";
};

35
arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts Normal file
View File

@@ -0,0 +1,35 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2021 MediaTek Inc.
*/
/dts-v1/;
#include "mt8195-cherry.dtsi"
/ {
model = "Acer Tomato (rev2) board";
compatible = "google,tomato-rev2", "google,tomato", "mediatek,mt8195";
};
&pio_default {
pins-low-power-hdmi-disable {
pinmux = <PINMUX_GPIO31__FUNC_GPIO31>,
<PINMUX_GPIO32__FUNC_GPIO32>,
<PINMUX_GPIO33__FUNC_GPIO33>,
<PINMUX_GPIO34__FUNC_GPIO34>,
<PINMUX_GPIO35__FUNC_GPIO35>;
input-enable;
bias-pull-down;
};
pins-low-power-pcie0-disable {
pinmux = <PINMUX_GPIO19__FUNC_GPIO19>,
<PINMUX_GPIO20__FUNC_GPIO20>,
<PINMUX_GPIO21__FUNC_GPIO21>;
input-enable;
bias-pull-down;
};
};
&ts_10 {
status = "okay";
};

36
arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r3.dts Normal file
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@@ -0,0 +1,36 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2021 MediaTek Inc.
*/
/dts-v1/;
#include "mt8195-cherry.dtsi"
/ {
model = "Acer Tomato (rev3 - 4) board";
compatible = "google,tomato-rev4", "google,tomato-rev3",
"google,tomato", "mediatek,mt8195";
};
&pio_default {
pins-low-power-hdmi-disable {
pinmux = <PINMUX_GPIO31__FUNC_GPIO31>,
<PINMUX_GPIO32__FUNC_GPIO32>,
<PINMUX_GPIO33__FUNC_GPIO33>,
<PINMUX_GPIO34__FUNC_GPIO34>,
<PINMUX_GPIO35__FUNC_GPIO35>;
input-enable;
bias-pull-down;
};
pins-low-power-pcie0-disable {
pinmux = <PINMUX_GPIO19__FUNC_GPIO19>,
<PINMUX_GPIO20__FUNC_GPIO20>,
<PINMUX_GPIO21__FUNC_GPIO21>;
input-enable;
bias-pull-down;
};
};
&ts_10 {
status = "okay";
};

702
arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi Normal file
View File

@@ -0,0 +1,702 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2021 MediaTek Inc.
*/
#include <dt-bindings/gpio/gpio.h>
#include "mt8195.dtsi"
#include "mt6359.dtsi"
/ {
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c7 = &i2c7;
mmc0 = &mmc0;
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0 0x80000000>;
};
/* system wide LDO 3.3V power rail */
pp3300_z5: regulator-pp3300-ldo-z5 {
compatible = "regulator-fixed";
regulator-name = "pp3300_ldo_z5";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&ppvar_sys>;
};
/* separately switched 3.3V power rail */
pp3300_s3: regulator-pp3300-s3 {
compatible = "regulator-fixed";
regulator-name = "pp3300_s3";
/* automatically sequenced by PMIC EXT_PMIC_EN2 */
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&pp3300_z2>;
};
/* system wide 3.3V power rail */
pp3300_z2: regulator-pp3300-z2 {
compatible = "regulator-fixed";
regulator-name = "pp3300_z2";
/* EN pin tied to pp4200_z2, which is controlled by EC */
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&ppvar_sys>;
};
/* system wide 4.2V power rail */
pp4200_z2: regulator-pp4200-z2 {
compatible = "regulator-fixed";
regulator-name = "pp4200_z2";
/* controlled by EC */
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <4200000>;
regulator-max-microvolt = <4200000>;
vin-supply = <&ppvar_sys>;
};
/* system wide switching 5.0V power rail */
pp5000_s5: regulator-pp5000-s5 {
compatible = "regulator-fixed";
regulator-name = "pp5000_s5";
/* controlled by EC */
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&ppvar_sys>;
};
/* system wide semi-regulated power rail from battery or USB */
ppvar_sys: regulator-ppvar-sys {
compatible = "regulator-fixed";
regulator-name = "ppvar_sys";
regulator-always-on;
regulator-boot-on;
};
usb_vbus: regulator-5v0-usb-vbus {
compatible = "regulator-fixed";
regulator-name = "usb-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
};
};
&i2c0 {
status = "okay";
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
};
&i2c1 {
status = "okay";
clock-frequency = <400000>;
i2c-scl-internal-delay-ns = <12500>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
};
&i2c2 {
status = "okay";
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
};
&i2c3 {
status = "okay";
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&i2c3_pins>;
};
&i2c4 {
status = "okay";
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&i2c4_pins>;
ts_10: touchscreen@10 {
compatible = "hid-over-i2c";
reg = <0x10>;
hid-descr-addr = <0x0001>;
interrupts-extended = <&pio 92 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&touchscreen_pins>;
post-power-on-delay-ms = <10>;
vdd-supply = <&pp3300_s3>;
status = "disabled";
};
};
&i2c5 {
status = "okay";
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&i2c5_pins>;
};
&i2c7 {
status = "okay";
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&i2c7_pins>;
pmic@34 {
#interrupt-cells = <1>;
compatible = "mediatek,mt6360";
reg = <0x34>;
interrupt-controller;
interrupts-extended = <&pio 130 IRQ_TYPE_EDGE_FALLING>;
interrupt-names = "IRQB";
pinctrl-names = "default";
pinctrl-0 = <&subpmic_default>;
wakeup-source;
};
};
&mmc0 {
status = "okay";
bus-width = <8>;
cap-mmc-highspeed;
cap-mmc-hw-reset;
hs400-ds-delay = <0x14c11>;
max-frequency = <200000000>;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
no-sdio;
no-sd;
non-removable;
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&mmc0_pins_default>;
pinctrl-1 = <&mmc0_pins_uhs>;
vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
vqmmc-supply = <&mt6359_vufs_ldo_reg>;
};
/* for CPU-L */
&mt6359_vcore_buck_reg {
regulator-always-on;
};
/* for CORE */
&mt6359_vgpu11_buck_reg {
regulator-always-on;
};
&mt6359_vgpu11_sshub_buck_reg {
regulator-always-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <550000>;
};
/* for CORE SRAM */
&mt6359_vpu_buck_reg {
regulator-always-on;
};
&mt6359_vrf12_ldo_reg {
regulator-always-on;
};
/* for GPU SRAM */
&mt6359_vsram_others_ldo_reg {
regulator-always-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
};
&mt6359_vufs_ldo_reg {
regulator-always-on;
};
&nor_flash {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&nor_pins_default>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <52000000>;
spi-rx-bus-width = <2>;
spi-tx-bus-width = <2>;
};
};
&pio {
mediatek,rsel-resistance-in-si-unit;
pinctrl-names = "default";
pinctrl-0 = <&pio_default>;
/* 144 lines */
gpio-line-names =
"I2S_SPKR_MCLK",
"I2S_SPKR_DATAIN",
"I2S_SPKR_LRCK",
"I2S_SPKR_BCLK",
"EC_AP_INT_ODL",
/*
* AP_FLASH_WP_L is crossystem ABI. Schematics
* call it AP_FLASH_WP_ODL.
*/
"AP_FLASH_WP_L",
"TCHPAD_INT_ODL",
"EDP_HPD_1V8",
"AP_I2C_CAM_SDA",
"AP_I2C_CAM_SCL",
"AP_I2C_TCHPAD_SDA_1V8",
"AP_I2C_TCHPAD_SCL_1V8",
"AP_I2C_AUD_SDA",
"AP_I2C_AUD_SCL",
"AP_I2C_TPM_SDA_1V8",
"AP_I2C_TPM_SCL_1V8",
"AP_I2C_TCHSCR_SDA_1V8",
"AP_I2C_TCHSCR_SCL_1V8",
"EC_AP_HPD_OD",
"",
"PCIE_NVME_RST_L",
"PCIE_NVME_CLKREQ_ODL",
"PCIE_RST_1V8_L",
"PCIE_CLKREQ_1V8_ODL",
"PCIE_WAKE_1V8_ODL",
"CLK_24M_CAM0",
"CAM1_SEN_EN",
"AP_I2C_PWR_SCL_1V8",
"AP_I2C_PWR_SDA_1V8",
"AP_I2C_MISC_SCL",
"AP_I2C_MISC_SDA",
"EN_PP5000_HDMI_X",
"AP_HDMITX_HTPLG",
"",
"AP_HDMITX_SCL_1V8",
"AP_HDMITX_SDA_1V8",
"AP_RTC_CLK32K",
"AP_EC_WATCHDOG_L",
"SRCLKENA0",
"SRCLKENA1",
"PWRAP_SPI0_CS_L",
"PWRAP_SPI0_CK",
"PWRAP_SPI0_MOSI",
"PWRAP_SPI0_MISO",
"SPMI_SCL",
"SPMI_SDA",
"",
"",
"",
"I2S_HP_DATAIN",
"I2S_HP_MCLK",
"I2S_HP_BCK",
"I2S_HP_LRCK",
"I2S_HP_DATAOUT",
"SD_CD_ODL",
"EN_PP3300_DISP_X",
"TCHSCR_RST_1V8_L",
"TCHSCR_REPORT_DISABLE",
"EN_PP3300_WLAN_X",
"BT_KILL_1V8_L",
"I2S_SPKR_DATAOUT",
"WIFI_KILL_1V8_L",
"BEEP_ON",
"SCP_I2C_SENSOR_SCL_1V8",
"SCP_I2C_SENSOR_SDA_1V8",
"",
"",
"",
"",
"AUD_CLK_MOSI",
"AUD_SYNC_MOSI",
"AUD_DAT_MOSI0",
"AUD_DAT_MOSI1",
"AUD_DAT_MISO0",
"AUD_DAT_MISO1",
"AUD_DAT_MISO2",
"SCP_VREQ_VAO",
"AP_SPI_GSC_TPM_CLK",
"AP_SPI_GSC_TPM_MOSI",
"AP_SPI_GSC_TPM_CS_L",
"AP_SPI_GSC_TPM_MISO",
"EN_PP1000_CAM_X",
"AP_EDP_BKLTEN",
"",
"USB3_HUB_RST_L",
"",
"WLAN_ALERT_ODL",
"EC_IN_RW_ODL",
"GSC_AP_INT_ODL",
"HP_INT_ODL",
"CAM0_RST_L",
"CAM1_RST_L",
"TCHSCR_INT_1V8_L",
"CAM1_DET_L",
"RST_ALC1011_L",
"",
"",
"BL_PWM_1V8",
"UART_AP_TX_DBG_RX",
"UART_DBG_TX_AP_RX",
"EN_SPKR",
"AP_EC_WARM_RST_REQ",
"UART_SCP_TX_DBGCON_RX",
"UART_DBGCON_TX_SCP_RX",
"",
"",
"KPCOL0",
"",
"MT6315_GPU_INT",
"MT6315_PROC_BC_INT",
"SD_CMD",
"SD_CLK",
"SD_DAT0",
"SD_DAT1",
"SD_DAT2",
"SD_DAT3",
"EMMC_DAT7",
"EMMC_DAT6",
"EMMC_DAT5",
"EMMC_DAT4",
"EMMC_RSTB",
"EMMC_CMD",
"EMMC_CLK",
"EMMC_DAT3",
"EMMC_DAT2",
"EMMC_DAT1",
"EMMC_DAT0",
"EMMC_DSL",
"",
"",
"MT6360_INT_ODL",
"SCP_JTAG0_TRSTN",
"AP_SPI_EC_CS_L",
"AP_SPI_EC_CLK",
"AP_SPI_EC_MOSI",
"AP_SPI_EC_MISO",
"SCP_JTAG0_TMS",
"SCP_JTAG0_TCK",
"SCP_JTAG0_TDO",
"SCP_JTAG0_TDI",
"AP_SPI_FLASH_CS_L",
"AP_SPI_FLASH_CLK",
"AP_SPI_FLASH_MOSI",
"AP_SPI_FLASH_MISO";
i2c0_pins: i2c0-default-pins {
pins-bus {
pinmux = <PINMUX_GPIO8__FUNC_SDA0>,
<PINMUX_GPIO9__FUNC_SCL0>;
bias-disable;
drive-strength-microamp = <1000>;
};
};
i2c1_pins: i2c1-default-pins {
pins-bus {
pinmux = <PINMUX_GPIO10__FUNC_SDA1>,
<PINMUX_GPIO11__FUNC_SCL1>;
bias-pull-up = <1000>;
drive-strength-microamp = <1000>;
};
};
i2c2_pins: i2c2-default-pins {
pins-bus {
pinmux = <PINMUX_GPIO12__FUNC_SDA2>,
<PINMUX_GPIO13__FUNC_SCL2>;
bias-disable;
drive-strength-microamp = <1000>;
};
};
i2c3_pins: i2c3-default-pins {
pins-bus {
pinmux = <PINMUX_GPIO14__FUNC_SDA3>,
<PINMUX_GPIO15__FUNC_SCL3>;
bias-pull-up = <1000>;
drive-strength-microamp = <1000>;
};
};
i2c4_pins: i2c4-default-pins {
pins-bus {
pinmux = <PINMUX_GPIO16__FUNC_SDA4>,
<PINMUX_GPIO17__FUNC_SCL4>;
bias-pull-up = <1000>;
drive-strength = <4>;
};
};
i2c5_pins: i2c5-default-pins {
pins-bus {
pinmux = <PINMUX_GPIO29__FUNC_SCL5>,
<PINMUX_GPIO30__FUNC_SDA5>;
bias-disable;
drive-strength-microamp = <1000>;
};
};
i2c7_pins: i2c7-default-pins {
pins-bus {
pinmux = <PINMUX_GPIO27__FUNC_SCL7>,
<PINMUX_GPIO28__FUNC_SDA7>;
bias-disable;
};
};
mmc0_pins_default: mmc0-default-pins {
pins-cmd-dat {
pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
<PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
<PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
<PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
<PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
<PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
<PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
<PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
<PINMUX_GPIO121__FUNC_MSDC0_CMD>;
input-enable;
drive-strength = <6>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins-clk {
pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
drive-strength = <6>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
pins-rst {
pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
drive-strength = <6>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
mmc0_pins_uhs: mmc0-uhs-pins {
pins-cmd-dat {
pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
<PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
<PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
<PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
<PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
<PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
<PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
<PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
<PINMUX_GPIO121__FUNC_MSDC0_CMD>;
input-enable;
drive-strength = <8>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins-clk {
pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
drive-strength = <8>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
pins-ds {
pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>;
drive-strength = <8>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
pins-rst {
pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
drive-strength = <8>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
nor_pins_default: nor-default-pins {
pins-ck-io {
pinmux = <PINMUX_GPIO142__FUNC_SPINOR_IO0>,
<PINMUX_GPIO141__FUNC_SPINOR_CK>,
<PINMUX_GPIO143__FUNC_SPINOR_IO1>;
drive-strength = <6>;
bias-pull-down;
};
pins-cs {
pinmux = <PINMUX_GPIO140__FUNC_SPINOR_CS>;
drive-strength = <6>;
bias-pull-up;
};
};
pio_default: pio-default-pins {
pins-wifi-enable {
pinmux = <PINMUX_GPIO58__FUNC_GPIO58>;
output-high;
drive-strength = <14>;
};
pins-low-power-pd {
pinmux = <PINMUX_GPIO25__FUNC_GPIO25>,
<PINMUX_GPIO26__FUNC_GPIO26>,
<PINMUX_GPIO46__FUNC_GPIO46>,
<PINMUX_GPIO47__FUNC_GPIO47>,
<PINMUX_GPIO48__FUNC_GPIO48>,
<PINMUX_GPIO65__FUNC_GPIO65>,
<PINMUX_GPIO66__FUNC_GPIO66>,
<PINMUX_GPIO67__FUNC_GPIO67>,
<PINMUX_GPIO68__FUNC_GPIO68>,
<PINMUX_GPIO128__FUNC_GPIO128>,
<PINMUX_GPIO129__FUNC_GPIO129>;
input-enable;
bias-pull-down;
};
pins-low-power-pupd {
pinmux = <PINMUX_GPIO77__FUNC_GPIO77>,
<PINMUX_GPIO78__FUNC_GPIO78>,
<PINMUX_GPIO79__FUNC_GPIO79>,
<PINMUX_GPIO80__FUNC_GPIO80>,
<PINMUX_GPIO83__FUNC_GPIO83>,
<PINMUX_GPIO85__FUNC_GPIO85>,
<PINMUX_GPIO90__FUNC_GPIO90>,
<PINMUX_GPIO91__FUNC_GPIO91>,
<PINMUX_GPIO93__FUNC_GPIO93>,
<PINMUX_GPIO94__FUNC_GPIO94>,
<PINMUX_GPIO95__FUNC_GPIO95>,
<PINMUX_GPIO96__FUNC_GPIO96>,
<PINMUX_GPIO104__FUNC_GPIO104>,
<PINMUX_GPIO105__FUNC_GPIO105>,
<PINMUX_GPIO107__FUNC_GPIO107>;
input-enable;
bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
};
};
spi0_pins: spi0-default-pins {
pins-cs-mosi-clk {
pinmux = <PINMUX_GPIO132__FUNC_SPIM0_CSB>,
<PINMUX_GPIO134__FUNC_SPIM0_MO>,
<PINMUX_GPIO133__FUNC_SPIM0_CLK>;
bias-disable;
};
pins-miso {
pinmux = <PINMUX_GPIO135__FUNC_SPIM0_MI>;
bias-pull-down;
};
};
subpmic_default: subpmic-default-pins {
subpmic_pin_irq: pins-subpmic-int-n {
pinmux = <PINMUX_GPIO130__FUNC_GPIO130>;
input-enable;
bias-pull-up;
};
};
touchscreen_pins: touchscreen-default-pins {
pins-int-n {
pinmux = <PINMUX_GPIO92__FUNC_GPIO92>;
input-enable;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins-rst {
pinmux = <PINMUX_GPIO56__FUNC_GPIO56>;
output-high;
};
pins-report-sw {
pinmux = <PINMUX_GPIO57__FUNC_GPIO57>;
output-low;
};
};
};
&pmic {
interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
};
&spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
mediatek,pad-select = <0>;
};
&u3phy0 {
status = "okay";
};
&u3phy1 {
status = "okay";
};
&u3phy2 {
status = "okay";
};
&u3phy3 {
status = "okay";
};
&uart0 {
status = "okay";
};
&xhci0 {
status = "okay";
vusb33-supply = <&mt6359_vusb_ldo_reg>;
vbus-supply = <&usb_vbus>;
};
&xhci1 {
status = "okay";
vusb33-supply = <&mt6359_vusb_ldo_reg>;
vbus-supply = <&usb_vbus>;
};
&xhci2 {
status = "okay";
vusb33-supply = <&mt6359_vusb_ldo_reg>;
vbus-supply = <&usb_vbus>;
};
&xhci3 {
status = "okay";
/* MT7921's USB Bluetooth has issues with USB2 LPM */
usb2-lpm-disable;
vusb33-supply = <&mt6359_vusb_ldo_reg>;
vbus-supply = <&usb_vbus>;
};

8
arch/arm64/boot/dts/mediatek/mt8195-evb.dts
View File

@@ -139,19 +139,19 @@ pins {
};
&u3phy0 {
status="okay";
status = "okay";
};
&u3phy1 {
status="okay";
status = "okay";
};
&u3phy2 {
status="okay";
status = "okay";
};
&u3phy3 {
status="okay";
status = "okay";
};
&uart0 {

76
arch/arm64/boot/dts/mediatek/mt8195.dtsi
View File

@@ -10,7 +10,6 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
#include <dt-bindings/reset/ti-syscon.h>
/ {
compatible = "mediatek,mt8195";
@@ -295,17 +294,7 @@ infracfg_ao: syscon@10001000 {
compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
infracfg_rst: reset-controller {
compatible = "ti,syscon-reset";
#reset-cells = <1>;
ti,reset-bits = <
0x140 18 0x144 18 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* pcie */
0x120 0 0x124 0 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */
0x730 10 0x734 10 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */
0x150 5 0x154 5 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* svs gpu */
>;
};
#reset-cells = <1>;
};
pericfg: syscon@10003000 {
@@ -573,6 +562,8 @@ xhci0: usb@11200000 {
<&apmixedsys CLK_APMIXED_USB1PLL>,
<&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>;
clock-names = "sys_ck", "ref_ck", "mcu_ck", "xhci_ck";
mediatek,syscon-wakeup = <&pericfg 0x400 103>;
wakeup-source;
status = "disabled";
};
@@ -636,6 +627,8 @@ xhci1: usb@11290000 {
<&apmixedsys CLK_APMIXED_USB1PLL>,
<&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>;
clock-names = "sys_ck", "ref_ck", "mcu_ck","xhci_ck";
mediatek,syscon-wakeup = <&pericfg 0x400 104>;
wakeup-source;
status = "disabled";
};
@@ -655,6 +648,8 @@ xhci2: usb@112a0000 {
<&topckgen CLK_TOP_SSUSB_P2_REF>,
<&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>;
clock-names = "sys_ck", "ref_ck", "xhci_ck";
mediatek,syscon-wakeup = <&pericfg 0x400 105>;
wakeup-source;
status = "disabled";
};
@@ -674,6 +669,8 @@ xhci3: usb@112b0000 {
<&topckgen CLK_TOP_SSUSB_P3_REF>,
<&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>;
clock-names = "sys_ck", "ref_ck", "xhci_ck";
mediatek,syscon-wakeup = <&pericfg 0x400 106>;
wakeup-source;
status = "disabled";
};
@@ -691,6 +688,53 @@ nor_flash: spi@1132c000 {
status = "disabled";
};
efuse: efuse@11c10000 {
compatible = "mediatek,mt8195-efuse", "mediatek,efuse";
reg = <0 0x11c10000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
u3_tx_imp_p0: usb3-tx-imp@184,1 {
reg = <0x184 0x1>;
bits = <0 5>;
};
u3_rx_imp_p0: usb3-rx-imp@184,2 {
reg = <0x184 0x2>;
bits = <5 5>;
};
u3_intr_p0: usb3-intr@185 {
reg = <0x185 0x1>;
bits = <2 6>;
};
comb_tx_imp_p1: usb3-tx-imp@186,1 {
reg = <0x186 0x1>;
bits = <0 5>;
};
comb_rx_imp_p1: usb3-rx-imp@186,2 {
reg = <0x186 0x2>;
bits = <5 5>;
};
comb_intr_p1: usb3-intr@187 {
reg = <0x187 0x1>;
bits = <2 6>;
};
u2_intr_p0: usb2-intr-p0@188,1 {
reg = <0x188 0x1>;
bits = <0 5>;
};
u2_intr_p1: usb2-intr-p1@188,2 {
reg = <0x188 0x2>;
bits = <5 5>;
};
u2_intr_p2: usb2-intr-p2@189,1 {
reg = <0x189 0x1>;
bits = <2 5>;
};
u2_intr_p3: usb2-intr-p3@189,2 {
reg = <0x189 0x2>;
bits = <7 5>;
};
};
u3phy2: t-phy@11c40000 {
compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
#address-cells = <1>;
@@ -873,6 +917,10 @@ u3port1: usb-phy@700 {
clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
<&topckgen CLK_TOP_SSUSB_PHY_P1_REF>;
clock-names = "ref", "da_ref";
nvmem-cells = <&comb_intr_p1>,
<&comb_rx_imp_p1>,
<&comb_tx_imp_p1>;
nvmem-cell-names = "intr", "rx_imp", "tx_imp";
#phy-cells = <1>;
};
};
@@ -897,6 +945,10 @@ u3port0: usb-phy@700 {
clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
<&topckgen CLK_TOP_SSUSB_PHY_REF>;
clock-names = "ref", "da_ref";
nvmem-cells = <&u3_intr_p0>,
<&u3_rx_imp_p0>,
<&u3_tx_imp_p0>;
nvmem-cell-names = "intr", "rx_imp", "tx_imp";
#phy-cells = <1>;
};
};

4
arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi
View File

@@ -28,7 +28,7 @@ gpio-keys {
pinctrl-names = "default";
pinctrl-0 = <&gpio_keys_default>;
volume-up {
key-volume-up {
gpios = <&pio 42 GPIO_ACTIVE_LOW>;
label = "volume_up";
linux,code = <115>;
@@ -36,7 +36,7 @@ volume-up {
debounce-interval = <15>;
};
volume-down {
key-volume-down {
gpios = <&pio 43 GPIO_ACTIVE_LOW>;
label = "volume_down";
linux,code = <114>;