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arm64: dts: qcom: monaco-evk: Add IFP Mezzanine

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The IFP Mezzanine is an hardware expansion add-on board designed
to be stacked on top of Monaco EVK.

It has following peripherals :
- 4x Type A USB ports in host mode.
- TC9563 PCIe switch, which has following three downstream ports (DSP) :
   - 1st DSP is routed to an M.2 E-Key connector, intended for
     WLAN modules.
   - 2nd DSP is routed to an M.2 B-key connector, intended for
     cellular modems.
   - 3rd DSP with support for Dual Ethernet ports.
- EEPROM.
- LVDS Display.
- 2*mini DP.

Add support for following peripherals :
- TC9563 PCIe Switch.
- EEPROM.

Enable support for USB hub, LVDS display and mini-DP later once dependent
changes are available in monaco-evk core-kit.

Written with inputs from :
    Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> - PCIe
    Monish Chunara <monish.chunara@oss.qualcomm.com> - EEPROM.

Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260303164314.886733-2-umang.chheda@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Umang Chheda
2026-03-03 22:13:14 +05:30
committed by Bjorn Andersson
parent 01022af2d2
commit 5a67924d2f
2 changed files with 151 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm64/boot/dts/qcom/Makefile
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@@ -61,6 +61,8 @@ dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-camera-imx577.dtb
monaco-evk-el2-dtbs := monaco-evk.dtb monaco-el2.dtbo
dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-el2.dtb
monaco-evk-ifp-mezzanine-dtbs := monaco-evk.dtb monaco-evk-ifp-mezzanine.dtbo
dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-ifp-mezzanine.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8216-samsung-fortuna3g.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb

149
arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso Normal file
View File

@@ -0,0 +1,149 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
&{/} {
model = "Qualcomm Technologies, Inc. Monaco-EVK IFP Mezzanine";
vreg_0p9: regulator-0v9 {
compatible = "regulator-fixed";
regulator-name = "VREG_0P9";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-always-on;
regulator-boot-on;
};
vreg_1p8: regulator-1v8 {
compatible = "regulator-fixed";
regulator-name = "VREG_1P8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
};
&i2c15 {
#address-cells = <1>;
#size-cells = <0>;
eeprom1: eeprom@52 {
compatible = "giantec,gt24c256c", "atmel,24c256";
reg = <0x52>;
pagesize = <64>;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
};
};
};
&pcie0 {
iommu-map = <0x0 &pcie_smmu 0x0 0x1>,
<0x100 &pcie_smmu 0x1 0x1>,
<0x208 &pcie_smmu 0x2 0x1>,
<0x210 &pcie_smmu 0x3 0x1>,
<0x218 &pcie_smmu 0x4 0x1>,
<0x300 &pcie_smmu 0x5 0x1>,
<0x400 &pcie_smmu 0x6 0x1>,
<0x500 &pcie_smmu 0x7 0x1>,
<0x501 &pcie_smmu 0x8 0x1>;
};
&pcieport0 {
#address-cells = <3>;
#size-cells = <2>;
pcie@0,0 {
compatible = "pci1179,0623";
reg = <0x10000 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges;
bus-range = <0x2 0xff>;
vddc-supply = <&vreg_0p9>;
vdd18-supply = <&vreg_1p8>;
vdd09-supply = <&vreg_0p9>;
vddio1-supply = <&vreg_1p8>;
vddio2-supply = <&vreg_1p8>;
vddio18-supply = <&vreg_1p8>;
i2c-parent = <&i2c15 0x77>;
resx-gpios = <&tlmm 124 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&tc9563_resx_n>;
pinctrl-names = "default";
pcie@1,0 {
reg = <0x20800 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges;
bus-range = <0x3 0xff>;
};
pcie@2,0 {
reg = <0x21000 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges;
bus-range = <0x4 0xff>;
};
pcie@3,0 {
reg = <0x21800 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges;
bus-range = <0x5 0xff>;
pci@0,0 {
reg = <0x50000 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges;
};
pci@0,1 {
reg = <0x50100 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges;
};
};
};
};
&tlmm {
tc9563_resx_n: tc9563-resx-state {
pins = "gpio124";
function = "gpio";
bias-disable;
/* Reset pin of tc9563 is active low hence set default
* state of this pin to output-high.
*/
output-high;
};
};