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net/mlx5: HWS, Create STEs directly from matcher

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Matchers were using the pool abstraction solely as a convenience
to allocate two STE ranges. The pool's core functionality, that
of allocating individual items from the range, was unused.
Matchers rely either on the hardware to hash rules into a table,
or on a user-provided index.

Remove the STE pool from the matcher and allocate the STE ranges
manually instead.

Signed-off-by: Vlad Dogaru <vdogaru@nvidia.com>
Reviewed-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Signed-off-by: Mark Bloch <mbloch@nvidia.com>
Link: https://patch.msgid.link/20250703185431.445571-6-mbloch@nvidia.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Vlad Dogaru
2025-07-03 21:54:26 +03:00
committed by Jakub Kicinski
parent 3dcac700d2
commit 59807d0717
3 changed files with 40 additions and 42 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/debug.c
View File

@@ -118,7 +118,6 @@ static int hws_debug_dump_matcher(struct seq_file *f, struct mlx5hws_matcher *ma
{
enum mlx5hws_table_type tbl_type = matcher->tbl->type;
struct mlx5hws_cmd_ft_query_attr ft_attr = {0};
struct mlx5hws_pool *ste_pool;
u64 icm_addr_0 = 0;
u64 icm_addr_1 = 0;
u32 ste_0_id = -1;
@@ -133,12 +132,9 @@ static int hws_debug_dump_matcher(struct seq_file *f, struct mlx5hws_matcher *ma
matcher->end_ft_id,
matcher->col_matcher ? HWS_PTR_TO_ID(matcher->col_matcher) : 0);
ste_pool = matcher->match_ste.pool;
if (ste_pool) {
ste_0_id = mlx5hws_pool_get_base_id(ste_pool);
if (tbl_type == MLX5HWS_TABLE_TYPE_FDB)
ste_1_id = mlx5hws_pool_get_base_mirror_id(ste_pool);
}
ste_0_id = matcher->match_ste.ste_0_base;
if (tbl_type == MLX5HWS_TABLE_TYPE_FDB)
ste_1_id = matcher->match_ste.ste_1_base;
seq_printf(f, ",%d,%d,%d,%d",
matcher->match_ste.rtc_0_id,

69
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.c
View File

@@ -507,10 +507,8 @@ static int hws_matcher_create_rtc(struct mlx5hws_matcher *matcher)
}
}
obj_id = mlx5hws_pool_get_base_id(matcher->match_ste.pool);
rtc_attr.pd = ctx->pd_num;
rtc_attr.ste_base = obj_id;
rtc_attr.ste_base = matcher->match_ste.ste_0_base;
rtc_attr.reparse_mode = mlx5hws_context_get_reparse_mode(ctx);
rtc_attr.table_type = mlx5hws_table_get_res_fw_ft_type(tbl->type, false);
hws_matcher_set_rtc_attr_sz(matcher, &rtc_attr, false);
@@ -527,9 +525,7 @@ static int hws_matcher_create_rtc(struct mlx5hws_matcher *matcher)
}
if (tbl->type == MLX5HWS_TABLE_TYPE_FDB) {
obj_id = mlx5hws_pool_get_base_mirror_id(
matcher->match_ste.pool);
rtc_attr.ste_base = obj_id;
rtc_attr.ste_base = matcher->match_ste.ste_1_base;
rtc_attr.table_type = mlx5hws_table_get_res_fw_ft_type(tbl->type, true);
obj_id = mlx5hws_pool_get_base_mirror_id(ctx->stc_pool);
@@ -588,21 +584,6 @@ hws_matcher_check_attr_sz(struct mlx5hws_cmd_query_caps *caps,
return 0;
}
static void hws_matcher_set_pool_attr(struct mlx5hws_pool_attr *attr,
struct mlx5hws_matcher *matcher)
{
switch (matcher->attr.optimize_flow_src) {
case MLX5HWS_MATCHER_FLOW_SRC_VPORT:
attr->opt_type = MLX5HWS_POOL_OPTIMIZE_ORIG;
break;
case MLX5HWS_MATCHER_FLOW_SRC_WIRE:
attr->opt_type = MLX5HWS_POOL_OPTIMIZE_MIRROR;
break;
default:
break;
}
}
static int hws_matcher_check_and_process_at(struct mlx5hws_matcher *matcher,
struct mlx5hws_action_template *at)
{
@@ -683,8 +664,8 @@ static void hws_matcher_set_ip_version_match(struct mlx5hws_matcher *matcher)
static int hws_matcher_bind_mt(struct mlx5hws_matcher *matcher)
{
struct mlx5hws_cmd_ste_create_attr ste_attr = {};
struct mlx5hws_context *ctx = matcher->tbl->ctx;
struct mlx5hws_pool_attr pool_attr = {0};
int ret;
/* Calculate match, range and hash definers */
@@ -699,22 +680,39 @@ static int hws_matcher_bind_mt(struct mlx5hws_matcher *matcher)
hws_matcher_set_ip_version_match(matcher);
/* Create an STE pool per matcher*/
pool_attr.table_type = matcher->tbl->type;
pool_attr.pool_type = MLX5HWS_POOL_TYPE_STE;
pool_attr.alloc_log_sz = matcher->attr.table.sz_col_log +
matcher->attr.table.sz_row_log;
hws_matcher_set_pool_attr(&pool_attr, matcher);
/* Create an STE range each for RX and TX. */
ste_attr.table_type = FS_FT_FDB_RX;
ste_attr.log_obj_range =
matcher->attr.optimize_flow_src ==
MLX5HWS_MATCHER_FLOW_SRC_VPORT ?
0 : matcher->attr.table.sz_col_log +
matcher->attr.table.sz_row_log;
matcher->match_ste.pool = mlx5hws_pool_create(ctx, &pool_attr);
if (!matcher->match_ste.pool) {
mlx5hws_err(ctx, "Failed to allocate matcher STE pool\n");
ret = -EOPNOTSUPP;
ret = mlx5hws_cmd_ste_create(ctx->mdev, &ste_attr,
&matcher->match_ste.ste_0_base);
if (ret) {
mlx5hws_err(ctx, "Failed to allocate RX STE range (%d)\n", ret);
goto uninit_match_definer;
}
ste_attr.table_type = FS_FT_FDB_TX;
ste_attr.log_obj_range =
matcher->attr.optimize_flow_src ==
MLX5HWS_MATCHER_FLOW_SRC_WIRE ?
0 : matcher->attr.table.sz_col_log +
matcher->attr.table.sz_row_log;
ret = mlx5hws_cmd_ste_create(ctx->mdev, &ste_attr,
&matcher->match_ste.ste_1_base);
if (ret) {
mlx5hws_err(ctx, "Failed to allocate TX STE range (%d)\n", ret);
goto destroy_rx_ste_range;
}
return 0;
destroy_rx_ste_range:
mlx5hws_cmd_ste_destroy(ctx->mdev, matcher->match_ste.ste_0_base);
uninit_match_definer:
if (!(matcher->flags & MLX5HWS_MATCHER_FLAGS_COLLISION))
mlx5hws_definer_mt_uninit(ctx, matcher->mt);
@@ -723,9 +721,12 @@ static int hws_matcher_bind_mt(struct mlx5hws_matcher *matcher)
static void hws_matcher_unbind_mt(struct mlx5hws_matcher *matcher)
{
mlx5hws_pool_destroy(matcher->match_ste.pool);
struct mlx5hws_context *ctx = matcher->tbl->ctx;
mlx5hws_cmd_ste_destroy(ctx->mdev, matcher->match_ste.ste_1_base);
mlx5hws_cmd_ste_destroy(ctx->mdev, matcher->match_ste.ste_0_base);
if (!(matcher->flags & MLX5HWS_MATCHER_FLAGS_COLLISION))
mlx5hws_definer_mt_uninit(matcher->tbl->ctx, matcher->mt);
mlx5hws_definer_mt_uninit(ctx, matcher->mt);
}
static int

3
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.h
View File

@@ -48,7 +48,8 @@ struct mlx5hws_match_template {
struct mlx5hws_matcher_match_ste {
u32 rtc_0_id;
u32 rtc_1_id;
struct mlx5hws_pool *pool;
u32 ste_0_base;
u32 ste_1_base;
};
enum {