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gpio: ppc44x: drop PPC-specific IO helpers

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Replace PPC-specific clrbits32()/setbits32() with local helpers using
ioread32be()/iowrite32be() which are equivalent on PPC since commit
894fa235eb ("powerpc: inline iomap accessors").

Add COMPILE_TEST as a result to increase compile coverage.

Assisted-by: opencode:big-pickle
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Reviewed-by: Linus Walleij <linusw@kernel.org>
Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com>
Link: https://patch.msgid.link/20260803223539.86303-7-rosenp@gmail.com
This commit is contained in:
Rosen Penev
2026-08-03 15:35:37 -07:00
committed by Madhavan Srinivasan
parent 714d445a1c
commit 595f5f25a9
2 changed files with 29 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpio/Kconfig
View File

@@ -595,7 +595,7 @@ config GPIO_POLARFIRE_SOC
config GPIO_PPC44X
tristate "PPC44x GPIO support"
depends on 44x
depends on 44x || COMPILE_TEST
select GPIO_GENERIC
help
Enable gpiolib support for ppc440 based boards.

40
drivers/gpio/gpio-ppc44x.c
View File

@@ -48,6 +48,22 @@ struct ppc44x_gpio_chip {
void __iomem *regs;
};
static inline void ppc44x_clrbits32(void __iomem *addr, u32 mask)
{
u32 val = ioread32be(addr);
val &= ~mask;
iowrite32be(val, addr);
}
static inline void ppc44x_setbits32(void __iomem *addr, u32 mask)
{
u32 val = ioread32be(addr);
val |= mask;
iowrite32be(val, addr);
}
/*
* GPIO LIB API implementation for GPIOs
*
@@ -77,19 +93,19 @@ static int ppc44x_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
guard(gpio_generic_lock_irqsave)(gen_gc);
/* Disable open-drain function */
clrbits32(&regs->odr, GPIO_MASK(gpio));
ppc44x_clrbits32(&regs->odr, GPIO_MASK(gpio));
/* Float the pin */
clrbits32(&regs->tcr, GPIO_MASK(gpio));
ppc44x_clrbits32(&regs->tcr, GPIO_MASK(gpio));
gen_gc->sdir &= ~GPIO_MASK(gpio);
/* Bits 0-15 use TSRL/OSRL, bits 16-31 use TSRH/OSRH */
if (gpio < 16) {
clrbits32(&regs->osrl, GPIO_MASK2(gpio));
clrbits32(&regs->tsrl, GPIO_MASK2(gpio));
ppc44x_clrbits32(&regs->osrl, GPIO_MASK2(gpio));
ppc44x_clrbits32(&regs->tsrl, GPIO_MASK2(gpio));
} else {
clrbits32(&regs->osrh, GPIO_MASK2(gpio));
clrbits32(&regs->tsrh, GPIO_MASK2(gpio));
ppc44x_clrbits32(&regs->osrh, GPIO_MASK2(gpio));
ppc44x_clrbits32(&regs->tsrh, GPIO_MASK2(gpio));
}
return 0;
@@ -108,19 +124,19 @@ ppc44x_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
__ppc44x_gpio_set(gc, gpio, val);
/* Disable open-drain function */
clrbits32(&regs->odr, GPIO_MASK(gpio));
ppc44x_clrbits32(&regs->odr, GPIO_MASK(gpio));
/* Drive the pin */
setbits32(&regs->tcr, GPIO_MASK(gpio));
ppc44x_setbits32(&regs->tcr, GPIO_MASK(gpio));
gen_gc->sdir |= GPIO_MASK(gpio);
/* Bits 0-15 use TSRL, bits 16-31 use TSRH */
if (gpio < 16) {
clrbits32(&regs->osrl, GPIO_MASK2(gpio));
clrbits32(&regs->tsrl, GPIO_MASK2(gpio));
ppc44x_clrbits32(&regs->osrl, GPIO_MASK2(gpio));
ppc44x_clrbits32(&regs->tsrl, GPIO_MASK2(gpio));
} else {
clrbits32(&regs->osrh, GPIO_MASK2(gpio));
clrbits32(&regs->tsrh, GPIO_MASK2(gpio));
ppc44x_clrbits32(&regs->osrh, GPIO_MASK2(gpio));
ppc44x_clrbits32(&regs->tsrh, GPIO_MASK2(gpio));
}
pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);