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soc: mediatek: svs: Add support for MT8186 SoC
MT8186 svs has a number of banks which used as optimization of opp voltage table for corresponding dvfs drivers. MT8186 svs big core uses 2-line high bank and low bank to optimize the voltage of opp table for higher and lower frequency respectively. Signed-off-by: Mark Tseng <chun-jen.tseng@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
This commit is contained in:
Mark Tseng
committed by
AngeloGioacchino Del Regno
AngeloGioacchino Del Regno
parent
8ccda5ceca
commit
58dbf59308
@@ -1986,6 +1986,89 @@ static bool svs_mt8188_efuse_parsing(struct svs_platform *svsp)
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return true;
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}
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static bool svs_mt8186_efuse_parsing(struct svs_platform *svsp)
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{
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struct svs_bank *svsb;
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u32 idx, i, golden_temp;
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int ret;
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for (i = 0; i < svsp->efuse_max; i++)
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if (svsp->efuse[i])
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dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n",
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i, svsp->efuse[i]);
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if (!svsp->efuse[0]) {
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dev_notice(svsp->dev, "svs_efuse[0] = 0x0?\n");
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return false;
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}
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/* Svs efuse parsing */
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for (idx = 0; idx < svsp->bank_max; idx++) {
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svsb = &svsp->banks[idx];
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switch (svsb->sw_id) {
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case SVSB_CPU_BIG:
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if (svsb->type == SVSB_HIGH) {
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svsb->mdes = (svsp->efuse[2] >> 24) & GENMASK(7, 0);
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svsb->bdes = (svsp->efuse[2] >> 16) & GENMASK(7, 0);
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svsb->mtdes = svsp->efuse[2] & GENMASK(7, 0);
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svsb->dcmdet = (svsp->efuse[13] >> 8) & GENMASK(7, 0);
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svsb->dcbdet = svsp->efuse[13] & GENMASK(7, 0);
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} else if (svsb->type == SVSB_LOW) {
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svsb->mdes = (svsp->efuse[3] >> 24) & GENMASK(7, 0);
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svsb->bdes = (svsp->efuse[3] >> 16) & GENMASK(7, 0);
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svsb->mtdes = svsp->efuse[3] & GENMASK(7, 0);
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svsb->dcmdet = (svsp->efuse[14] >> 24) & GENMASK(7, 0);
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svsb->dcbdet = (svsp->efuse[14] >> 16) & GENMASK(7, 0);
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}
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break;
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case SVSB_CPU_LITTLE:
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svsb->mdes = (svsp->efuse[4] >> 24) & GENMASK(7, 0);
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svsb->bdes = (svsp->efuse[4] >> 16) & GENMASK(7, 0);
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svsb->mtdes = svsp->efuse[4] & GENMASK(7, 0);
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svsb->dcmdet = (svsp->efuse[14] >> 8) & GENMASK(7, 0);
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svsb->dcbdet = svsp->efuse[14] & GENMASK(7, 0);
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break;
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case SVSB_CCI:
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svsb->mdes = (svsp->efuse[5] >> 24) & GENMASK(7, 0);
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svsb->bdes = (svsp->efuse[5] >> 16) & GENMASK(7, 0);
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svsb->mtdes = svsp->efuse[5] & GENMASK(7, 0);
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svsb->dcmdet = (svsp->efuse[15] >> 24) & GENMASK(7, 0);
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svsb->dcbdet = (svsp->efuse[15] >> 16) & GENMASK(7, 0);
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break;
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case SVSB_GPU:
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svsb->mdes = (svsp->efuse[6] >> 24) & GENMASK(7, 0);
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svsb->bdes = (svsp->efuse[6] >> 16) & GENMASK(7, 0);
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svsb->mtdes = svsp->efuse[6] & GENMASK(7, 0);
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svsb->dcmdet = (svsp->efuse[15] >> 8) & GENMASK(7, 0);
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svsb->dcbdet = svsp->efuse[15] & GENMASK(7, 0);
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break;
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default:
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dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id);
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return false;
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}
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svsb->vmax += svsb->dvt_fixed;
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}
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ret = svs_get_efuse_data(svsp, "t-calibration-data",
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&svsp->tefuse, &svsp->tefuse_max);
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if (ret)
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return false;
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golden_temp = (svsp->tefuse[0] >> 24) & GENMASK(7, 0);
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if (!golden_temp)
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golden_temp = 50;
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for (idx = 0; idx < svsp->bank_max; idx++) {
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svsb = &svsp->banks[idx];
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svsb->mts = 409;
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svsb->bts = (((500 * golden_temp + 204650) / 1000) - 25) * 4;
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}
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return true;
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}
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static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp)
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{
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struct svs_bank *svsb;
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@@ -2252,6 +2335,50 @@ static int svs_mt8192_platform_probe(struct svs_platform *svsp)
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return 0;
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}
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static int svs_mt8186_platform_probe(struct svs_platform *svsp)
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{
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struct device *dev;
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struct svs_bank *svsb;
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u32 idx;
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svsp->rst = devm_reset_control_get_optional(svsp->dev, "svs_rst");
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if (IS_ERR(svsp->rst))
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return dev_err_probe(svsp->dev, PTR_ERR(svsp->rst),
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"cannot get svs reset control\n");
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dev = svs_add_device_link(svsp, "lvts");
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if (IS_ERR(dev))
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return dev_err_probe(svsp->dev, PTR_ERR(dev),
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"failed to get lvts device\n");
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for (idx = 0; idx < svsp->bank_max; idx++) {
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svsb = &svsp->banks[idx];
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switch (svsb->sw_id) {
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case SVSB_CPU_LITTLE:
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case SVSB_CPU_BIG:
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svsb->opp_dev = get_cpu_device(svsb->cpu_id);
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break;
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case SVSB_CCI:
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svsb->opp_dev = svs_add_device_link(svsp, "cci");
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break;
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case SVSB_GPU:
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svsb->opp_dev = svs_add_device_link(svsp, "gpu");
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break;
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default:
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dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id);
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return -EINVAL;
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}
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if (IS_ERR(svsb->opp_dev))
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return dev_err_probe(svsp->dev, PTR_ERR(svsb->opp_dev),
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"failed to get OPP device for bank %d\n",
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idx);
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}
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return 0;
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}
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static int svs_mt8183_platform_probe(struct svs_platform *svsp)
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{
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struct device *dev;
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@@ -2461,6 +2588,149 @@ static struct svs_bank svs_mt8188_banks[] = {
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},
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};
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static struct svs_bank svs_mt8186_banks[] = {
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{
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.sw_id = SVSB_CPU_BIG,
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.type = SVSB_LOW,
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.set_freq_pct = svs_set_bank_freq_pct_v3,
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.get_volts = svs_get_bank_volts_v3,
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.cpu_id = 6,
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.volt_flags = SVSB_REMOVE_DVTFIXED_VOLT,
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.mode_support = SVSB_MODE_INIT02,
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.opp_count = MAX_OPP_ENTRIES,
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.freq_base = 1670000000,
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.turn_freq_base = 1670000000,
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.volt_step = 6250,
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.volt_base = 400000,
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.volt_od = 4,
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.vmax = 0x59,
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.vmin = 0x20,
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.age_config = 0x1,
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.dc_config = 0x1,
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.dvt_fixed = 0x3,
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.vco = 0x10,
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.chk_shift = 0x87,
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.core_sel = 0x0fff0100,
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.int_st = BIT(0),
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.ctl0 = 0x00540003,
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},
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{
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.sw_id = SVSB_CPU_BIG,
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.type = SVSB_HIGH,
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.set_freq_pct = svs_set_bank_freq_pct_v3,
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.get_volts = svs_get_bank_volts_v3,
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.cpu_id = 6,
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.tzone_name = "cpu_big0",
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.volt_flags = SVSB_REMOVE_DVTFIXED_VOLT |
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SVSB_MON_VOLT_IGNORE,
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.mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON,
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.opp_count = MAX_OPP_ENTRIES,
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.freq_base = 2050000000,
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.turn_freq_base = 1670000000,
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.volt_step = 6250,
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.volt_base = 400000,
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.volt_od = 4,
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.vmax = 0x73,
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.vmin = 0x20,
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.age_config = 0x1,
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.dc_config = 0x1,
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.dvt_fixed = 0x6,
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.vco = 0x10,
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.chk_shift = 0x87,
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.core_sel = 0x0fff0101,
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.int_st = BIT(1),
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.ctl0 = 0x00540003,
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.tzone_htemp = 85000,
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.tzone_htemp_voffset = 8,
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.tzone_ltemp = 25000,
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.tzone_ltemp_voffset = 8,
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},
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{
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.sw_id = SVSB_CPU_LITTLE,
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.set_freq_pct = svs_set_bank_freq_pct_v2,
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.get_volts = svs_get_bank_volts_v2,
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.cpu_id = 0,
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.tzone_name = "cpu_zone0",
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.volt_flags = SVSB_REMOVE_DVTFIXED_VOLT |
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SVSB_MON_VOLT_IGNORE,
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.mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON,
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.opp_count = MAX_OPP_ENTRIES,
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.freq_base = 2000000000,
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.volt_step = 6250,
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.volt_base = 400000,
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.volt_od = 3,
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.vmax = 0x65,
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.vmin = 0x20,
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.age_config = 0x1,
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.dc_config = 0x1,
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.dvt_fixed = 0x6,
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.vco = 0x10,
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.chk_shift = 0x87,
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.core_sel = 0x0fff0102,
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.int_st = BIT(2),
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.ctl0 = 0x3210000f,
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.tzone_htemp = 85000,
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.tzone_htemp_voffset = 8,
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.tzone_ltemp = 25000,
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.tzone_ltemp_voffset = 8,
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},
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{
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.sw_id = SVSB_CCI,
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.set_freq_pct = svs_set_bank_freq_pct_v2,
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.get_volts = svs_get_bank_volts_v2,
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.tzone_name = "cpu_zone0",
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.volt_flags = SVSB_REMOVE_DVTFIXED_VOLT |
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SVSB_MON_VOLT_IGNORE,
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.mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON,
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.opp_count = MAX_OPP_ENTRIES,
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.freq_base = 1400000000,
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.volt_step = 6250,
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.volt_base = 400000,
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.volt_od = 3,
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.vmax = 0x65,
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.vmin = 0x20,
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.age_config = 0x1,
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.dc_config = 0x1,
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.dvt_fixed = 0x6,
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.vco = 0x10,
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.chk_shift = 0x87,
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.core_sel = 0x0fff0103,
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.int_st = BIT(3),
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.ctl0 = 0x3210000f,
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.tzone_htemp = 85000,
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.tzone_htemp_voffset = 8,
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.tzone_ltemp = 25000,
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.tzone_ltemp_voffset = 8,
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},
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{
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.sw_id = SVSB_GPU,
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.set_freq_pct = svs_set_bank_freq_pct_v2,
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.get_volts = svs_get_bank_volts_v2,
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.tzone_name = "mfg",
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.volt_flags = SVSB_REMOVE_DVTFIXED_VOLT |
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SVSB_MON_VOLT_IGNORE,
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.mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON,
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.opp_count = MAX_OPP_ENTRIES,
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.freq_base = 850000000,
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.volt_step = 6250,
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.volt_base = 400000,
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.vmax = 0x58,
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.vmin = 0x20,
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.age_config = 0x555555,
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.dc_config = 0x1,
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.dvt_fixed = 0x4,
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.vco = 0x10,
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.chk_shift = 0x87,
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.core_sel = 0x0fff0104,
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.int_st = BIT(4),
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.ctl0 = 0x00100003,
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.tzone_htemp = 85000,
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.tzone_htemp_voffset = 8,
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.tzone_ltemp = 25000,
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.tzone_ltemp_voffset = 7,
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},
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};
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static struct svs_bank svs_mt8183_banks[] = {
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{
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.sw_id = SVSB_CPU_LITTLE,
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@@ -2592,6 +2862,15 @@ static const struct svs_platform_data svs_mt8188_platform_data = {
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.bank_max = ARRAY_SIZE(svs_mt8188_banks),
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};
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static const struct svs_platform_data svs_mt8186_platform_data = {
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.name = "mt8186-svs",
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.banks = svs_mt8186_banks,
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.efuse_parsing = svs_mt8186_efuse_parsing,
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.probe = svs_mt8186_platform_probe,
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.regs = svs_regs_v2,
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.bank_max = ARRAY_SIZE(svs_mt8186_banks),
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};
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static const struct svs_platform_data svs_mt8183_platform_data = {
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.name = "mt8183-svs",
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.banks = svs_mt8183_banks,
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@@ -2611,6 +2890,9 @@ static const struct of_device_id svs_of_match[] = {
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}, {
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.compatible = "mediatek,mt8188-svs",
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.data = &svs_mt8188_platform_data,
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}, {
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.compatible = "mediatek,mt8186-svs",
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.data = &svs_mt8186_platform_data,
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}, {
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.compatible = "mediatek,mt8183-svs",
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.data = &svs_mt8183_platform_data,
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