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drm/i915: Enable DSI PLL for both DSI0 and DSI1 in case of dual link

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For Dual link MIPI Panels, dsipll clock for both DSI0 and DSI1 needs to be enabled.

v2: Address review comments by Jani
    - Added wait time for PLL to be locked.

v3: separate patch created for cck read for checking PLL to be locked

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Gaurav K Singh
2014-12-04 10:58:52 +05:30
committed by Daniel Vetter
parent 4510cd779e
commit 58cf8887c9
1 changed files with 3 additions and 0 deletions
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3
drivers/gpu/drm/i915/intel_dsi_pll.c
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@@ -243,6 +243,9 @@ static void vlv_configure_dsi_pll(struct intel_encoder *encoder)
dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
if (intel_dsi->dual_link)
dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;
DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n",
dsi_mnp.dsi_pll_div, dsi_mnp.dsi_pll_ctrl);