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irqchip/irq-realtek-rtl: Use readl_be()/writel_be() instead of readl()/writel()

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When CONFIG_SWAP_IO_SPACE is enabled, readl() performs a swap from little
endian device to big endian CPU and vice versa for writel().

This is incorrect for Realtek Interrupt controller as that is a big endian
device and so the LE to BE conversions are unwanted.

Fix this by converting the MMIO accesses to readl_be() and writel_be().

Fixes: 9f3a0f34b8 ("irqchip: Add support for Realtek RTL838x/RTL839x interrupt controller")
Signed-off-by: Rustam Adilov <adilov@disroot.org>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Tested-by: Carlo Szelinsky <github@szelinsky.de>
Link: https://patch.msgid.link/20260820162017.28507-1-adilov@disroot.org
This commit is contained in:
Rustam Adilov
2026-08-20 21:20:17 +05:00
committed by Thomas Gleixner
parent a1ee1a1ca7
commit 58b34b72b6
1 changed files with 13 additions and 7 deletions
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20
drivers/irqchip/irq-realtek-rtl.c
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@@ -1,5 +1,10 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Realtek Interrupt controller.
*
* The Realtek Interrupt controller is a big endian device found in the
* Realtek MIPS SoCs.
*
* Copyright (C) 2020 Birger Koblitz <mail@birger-koblitz.de>
* Copyright (C) 2020 Bert Vermeulen <bert@biot.com>
* Copyright (C) 2020 John Crispin <john@phrozen.org>
@@ -50,18 +55,18 @@ static inline void enable_gimr(unsigned int cpu, unsigned int hw_irq)
{
u32 gimr;
gimr = readl(REG(cpu, RTL_ICTL_GIMR));
gimr = readl_be(REG(cpu, RTL_ICTL_GIMR));
gimr |= BIT(hw_irq);
writel(gimr, REG(cpu, RTL_ICTL_GIMR));
writel_be(gimr, REG(cpu, RTL_ICTL_GIMR));
}
static inline void disable_gimr(unsigned int cpu, unsigned int hw_irq)
{
u32 gimr;
gimr = readl(REG(cpu, RTL_ICTL_GIMR));
gimr = readl_be(REG(cpu, RTL_ICTL_GIMR));
gimr &= ~BIT(hw_irq);
writel(gimr, REG(cpu, RTL_ICTL_GIMR));
writel_be(gimr, REG(cpu, RTL_ICTL_GIMR));
}
static void write_irr(unsigned int cpu, int hw_irq, u32 value)
@@ -71,9 +76,9 @@ static void write_irr(unsigned int cpu, int hw_irq, u32 value)
unsigned int shift = IRR_SHIFT(hw_irq);
u32 irr;
irr = readl(irr0 + offset) & ~(0xf << shift);
irr = readl_be(irr0 + offset) & ~(0xf << shift);
irr |= (value & 0xf) << shift;
writel(irr, irr0 + offset);
writel_be(irr, irr0 + offset);
}
static void realtek_ictl_unmask_irq(struct irq_data *i)
@@ -159,7 +164,8 @@ static void realtek_irq_dispatch(struct irq_desc *desc)
unsigned int hw_irq;
chained_irq_enter(chip, desc);
pending = readl(REG(cpu, RTL_ICTL_GIMR)) & readl(REG(cpu, RTL_ICTL_GISR)) & output->mask;
pending = readl_be(REG(cpu, RTL_ICTL_GIMR)) &
readl_be(REG(cpu, RTL_ICTL_GISR)) & output->mask;
if (unlikely(!pending)) {
spurious_interrupt();