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ARM: dts: qcom: sdx65: Add support for PCIe PHY

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Add devicetree support for PCIe PHY used in SDX65 platform. This PHY is
used by the PCIe EP controller.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/1684432073-28490-3-git-send-email-quic_rohiagar@quicinc.com
This commit is contained in:
Rohit Agarwal
2023-05-18 23:17:50 +05:30
committed by Bjorn Andersson
parent d2f1bd8f0b
commit 57b60d03d5
1 changed files with 31 additions and 0 deletions
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31
arch/arm/boot/dts/qcom-sdx65.dtsi
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@@ -295,6 +295,37 @@ qpic_nand: nand-controller@1b30000 {
status = "disabled";
};
pcie_phy: phy@1c06000 {
compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy";
reg = <0x01c06000 0x2000>;
clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>,
<&gcc GCC_PCIE_CFG_AHB_CLK>,
<&gcc GCC_PCIE_0_CLKREF_EN>,
<&gcc GCC_PCIE_RCHNG_PHY_CLK>,
<&gcc GCC_PCIE_PIPE_CLK>;
clock-names = "aux",
"cfg_ahb",
"ref",
"rchng",
"pipe";
resets = <&gcc GCC_PCIE_PHY_BCR>;
reset-names = "phy";
assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
assigned-clock-rates = <100000000>;
power-domains = <&gcc PCIE_GDSC>;
#clock-cells = <0>;
clock-output-names = "pcie_pipe_clk";
#phy-cells = <0>;
status = "disabled";
};
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x01f40000 0x40000>;