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Merge tag 'clk-renesas-for-v5.8-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven:
- A minor fix for the currently unused suspend/resume handling on
RZ/A1 and RZ/A2
- Two more conversions of Renesas DT bindings to json-schema
* tag 'clk-renesas-for-v5.8-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
dt-bindings: clock: renesas: mstp: Convert to json-schema
dt-bindings: clock: renesas: div6: Convert to json-schema
clk: renesas: cpg-mssr: Fix STBCR suspend/resume handling
This commit is contained in:
Stephen Boyd
@@ -0,0 +1,60 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/renesas,cpg-div6-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas CPG DIV6 Clock
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maintainers:
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- Geert Uytterhoeven <geert+renesas@glider.be>
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description:
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The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse
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Generator (CPG). Their clock input is divided by a configurable factor from 1
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to 64.
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properties:
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compatible:
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items:
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- enum:
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- renesas,r8a73a4-div6-clock # R-Mobile APE6
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- renesas,r8a7740-div6-clock # R-Mobile A1
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- renesas,sh73a0-div6-clock # SH-Mobile AG5
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- const: renesas,cpg-div6-clock
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reg:
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maxItems: 1
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clocks:
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oneOf:
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- maxItems: 1
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- maxItems: 4
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- maxItems: 8
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description:
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For clocks with multiple parents, invalid settings must be specified as
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"<0>".
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'#clock-cells':
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const: 0
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clock-output-names: true
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/r8a73a4-clock.h>
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sdhi2_clk: sdhi2_clk@e615007c {
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compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe615007c 4>;
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clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>,
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<&extal2_clk>;
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#clock-cells = <0>;
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};
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@@ -1,40 +0,0 @@
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* Renesas CPG DIV6 Clock
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The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse
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Generator (CPG). Their clock input is divided by a configurable factor from 1
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to 64.
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Required Properties:
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- compatible: Must be one of the following
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- "renesas,r8a73a4-div6-clock" for R8A73A4 (R-Mobile APE6) DIV6 clocks
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- "renesas,r8a7740-div6-clock" for R8A7740 (R-Mobile A1) DIV6 clocks
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- "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks
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- "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2-W) DIV6 clocks
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- "renesas,r8a7793-div6-clock" for R8A7793 (R-Car M2-N) DIV6 clocks
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- "renesas,r8a7794-div6-clock" for R8A7794 (R-Car E2) DIV6 clocks
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- "renesas,sh73a0-div6-clock" for SH73A0 (SH-Mobile AG5) DIV6 clocks
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and "renesas,cpg-div6-clock" as a fallback.
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- reg: Base address and length of the memory resource used by the DIV6 clock
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- clocks: Reference to the parent clock(s); either one, four, or eight
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clocks must be specified. For clocks with multiple parents, invalid
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settings must be specified as "<0>".
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- #clock-cells: Must be 0
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Optional Properties:
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- clock-output-names: The name of the clock as a free-form string
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Example
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-------
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sdhi2_clk: sdhi2_clk@e615007c {
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compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
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reg = <0 0xe615007c 0 4>;
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clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
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<0>, <&extal2_clk>;
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#clock-cells = <0>;
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clock-output-names = "sdhi2ck";
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};
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@@ -1,60 +0,0 @@
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* Renesas CPG Module Stop (MSTP) Clocks
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The CPG can gate SoC device clocks. The gates are organized in groups of up to
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32 gates.
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This device tree binding describes a single 32 gate clocks group per node.
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Clocks are referenced by user nodes by the MSTP node phandle and the clock
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index in the group, from 0 to 31.
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Required Properties:
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- compatible: Must be one of the following
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- "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks
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- "renesas,r8a73a4-mstp-clocks" for R8A73A4 (R-Mobile APE6) MSTP gate clocks
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- "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks
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- "renesas,r8a7778-mstp-clocks" for R8A7778 (R-Car M1) MSTP gate clocks
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- "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
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- "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
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- "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2-W) MSTP gate clocks
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- "renesas,r8a7792-mstp-clocks" for R8A7792 (R-Car V2H) MSTP gate clocks
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- "renesas,r8a7793-mstp-clocks" for R8A7793 (R-Car M2-N) MSTP gate clocks
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- "renesas,r8a7794-mstp-clocks" for R8A7794 (R-Car E2) MSTP gate clocks
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- "renesas,sh73a0-mstp-clocks" for SH73A0 (SH-MobileAG5) MSTP gate clocks
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and "renesas,cpg-mstp-clocks" as a fallback.
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- reg: Base address and length of the I/O mapped registers used by the MSTP
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clocks. The first register is the clock control register and is mandatory.
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The second register is the clock status register and is optional when not
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implemented in hardware.
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- clocks: Reference to the parent clocks, one per output clock. The parents
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must appear in the same order as the output clocks.
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- #clock-cells: Must be 1
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- clock-output-names: The name of the clocks as free-form strings
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- clock-indices: Indices of the gate clocks into the group (0 to 31)
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The clocks, clock-output-names and clock-indices properties contain one entry
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per gate clock. The MSTP groups are sparsely populated. Unimplemented gate
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clocks must not be declared.
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Example
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-------
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#include <dt-bindings/clock/r8a7790-clock.h>
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mstp3_clks: mstp3_clks@e615013c {
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compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
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clocks = <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>,
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<&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>,
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<&mmc0_clk>;
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#clock-cells = <1>;
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clock-output-names =
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"tpu0", "mmcif1", "sdhi3", "sdhi2",
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"sdhi1", "sdhi0", "mmcif0";
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clock-indices = <
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R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
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R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0
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R8A7790_CLK_MMCIF0
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>;
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};
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@@ -0,0 +1,82 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/renesas,cpg-mstp-clocks.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas Clock Pulse Generator (CPG) Module Stop (MSTP) Clocks
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maintainers:
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- Geert Uytterhoeven <geert+renesas@glider.be>
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description:
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The Clock Pulse Generator (CPG) can gate SoC device clocks. The gates are
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organized in groups of up to 32 gates.
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This device tree binding describes a single 32 gate clocks group per node.
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Clocks are referenced by user nodes by the Module Stop (MSTP) node phandle
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and the clock index in the group, from 0 to 31.
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properties:
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compatible:
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items:
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- enum:
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- renesas,r7s72100-mstp-clocks # RZ/A1
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- renesas,r8a73a4-mstp-clocks # R-Mobile APE6
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- renesas,r8a7740-mstp-clocks # R-Mobile A1
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- renesas,r8a7778-mstp-clocks # R-Car M1
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- renesas,r8a7779-mstp-clocks # R-Car H1
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- renesas,sh73a0-mstp-clocks # SH-Mobile AG5
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- const: renesas,cpg-mstp-clocks
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reg:
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minItems: 1
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items:
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- description: Module Stop Control Register (MSTPCR)
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- description: Module Stop Status Register (MSTPSR)
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clocks:
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minItems: 1
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maxItems: 32
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'#clock-cells':
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const: 1
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clock-indices:
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minItems: 1
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maxItems: 32
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clock-output-names:
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minItems: 1
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maxItems: 32
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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- clock-indices
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- clock-output-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/r8a73a4-clock.h>
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mstp2_clks: mstp2_clks@e6150138 {
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compatible = "renesas,r8a73a4-mstp-clocks",
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"renesas,cpg-mstp-clocks";
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reg = <0xe6150138 4>, <0xe6150040 4>;
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clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
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<&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
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#clock-cells = <1>;
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clock-indices = <
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R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1
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R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1
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R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3
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R8A73A4_CLK_DMAC
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>;
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clock-output-names =
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"scifa0", "scifa1", "scifb0", "scifb1", "scifb2", "scifb3",
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"dmac";
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};
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@@ -818,7 +818,8 @@ static int cpg_mssr_suspend_noirq(struct device *dev)
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/* Save module registers with bits under our control */
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for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {
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if (priv->smstpcr_saved[reg].mask)
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priv->smstpcr_saved[reg].val =
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priv->smstpcr_saved[reg].val = priv->stbyctrl ?
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readb(priv->base + STBCR(reg)) :
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readl(priv->base + SMSTPCR(reg));
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}
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@@ -878,8 +879,9 @@ static int cpg_mssr_resume_noirq(struct device *dev)
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}
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if (!i)
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dev_warn(dev, "Failed to enable SMSTP %p[0x%x]\n",
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priv->base + SMSTPCR(reg), oldval & mask);
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dev_warn(dev, "Failed to enable %s%u[0x%x]\n",
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priv->stbyctrl ? "STB" : "SMSTP", reg,
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oldval & mask);
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}
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return 0;
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