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drm/nouveau/bar: modify interface to bar1 vmm mapping

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Upcoming changes will remove the nvkm_vmm pointer from nvkm_vma, instead
requiring it to be explicitly specified on each operation.

It's not currently possible to get this information for BAR1 mappings,
so let's fix that ahead of time.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
2017-11-01 03:56:19 +10:00
parent e988952eef
commit 570889dc50
13 changed files with 32 additions and 28 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/drm/nouveau/include/nvkm/core/os.h
View File

@@ -1,4 +1,5 @@
#ifndef __NVKM_OS_H__
#define __NVKM_OS_H__
#include <nvif/os.h>
#define nvkm_vmm nvkm_vm
#endif

2
drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h
View File

@@ -14,11 +14,11 @@ struct nvkm_bar {
bool iomap_uncached;
};
struct nvkm_vmm *nvkm_bar_bar1_vmm(struct nvkm_device *);
void nvkm_bar_bar2_init(struct nvkm_device *);
void nvkm_bar_bar2_fini(struct nvkm_device *);
void nvkm_bar_flush(struct nvkm_bar *);
struct nvkm_vm *nvkm_bar_kmap(struct nvkm_bar *);
int nvkm_bar_umap(struct nvkm_bar *, u64 size, int type, struct nvkm_vma *);
int nv50_bar_new(struct nvkm_device *, int, struct nvkm_bar **);
int g84_bar_new(struct nvkm_device *, int, struct nvkm_bar **);

6
drivers/gpu/drm/nouveau/nouveau_bo.c
View File

@@ -1362,13 +1362,13 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *reg)
reg->bus.base = device->func->resource_addr(device, 1);
reg->bus.is_iomem = true;
if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
struct nvkm_bar *bar = nvxx_bar(&drm->client.device);
struct nvkm_vmm *bar = nvkm_bar_bar1_vmm(device);
int page_shift = 12;
if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_FERMI)
page_shift = mem->page_shift;
ret = nvkm_bar_umap(bar, mem->size << 12, page_shift,
&mem->bar_vma);
ret = nvkm_vm_get(bar, mem->size << 12, page_shift,
NV_MEM_ACCESS_RW, &mem->bar_vma);
if (ret)
return ret;

5
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
View File

@@ -28,6 +28,7 @@
#include <core/enum.h>
#include <core/gpuobj.h>
#include <subdev/bar.h>
#include <subdev/fb.h>
#include <engine/sw.h>
#include <nvif/class.h>
@@ -559,6 +560,7 @@ gf100_fifo_oneinit(struct nvkm_fifo *base)
struct gf100_fifo *fifo = gf100_fifo(base);
struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
struct nvkm_device *device = subdev->device;
struct nvkm_vmm *bar = nvkm_bar_bar1_vmm(device);
int ret;
/* Determine number of PBDMAs by checking valid enable bits. */
@@ -584,7 +586,8 @@ gf100_fifo_oneinit(struct nvkm_fifo *base)
if (ret)
return ret;
ret = nvkm_bar_umap(device->bar, 128 * 0x1000, 12, &fifo->user.bar);
ret = nvkm_vm_get(bar, nvkm_memory_size(fifo->user.mem), 12,
NV_MEM_ACCESS_RW, &fifo->user.bar);
if (ret)
return ret;

6
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
View File

@@ -27,6 +27,7 @@
#include <core/client.h>
#include <core/gpuobj.h>
#include <subdev/bar.h>
#include <subdev/fb.h>
#include <subdev/timer.h>
#include <subdev/top.h>
#include <engine/sw.h>
@@ -771,6 +772,7 @@ gk104_fifo_oneinit(struct nvkm_fifo *base)
struct gk104_fifo *fifo = gk104_fifo(base);
struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
struct nvkm_device *device = subdev->device;
struct nvkm_vmm *bar = nvkm_bar_bar1_vmm(device);
int engn, runl, pbid, ret, i, j;
enum nvkm_devidx engidx;
u32 *map;
@@ -834,8 +836,8 @@ gk104_fifo_oneinit(struct nvkm_fifo *base)
if (ret)
return ret;
ret = nvkm_bar_umap(device->bar, fifo->base.nr * 0x200, 12,
&fifo->user.bar);
ret = nvkm_vm_get(bar, nvkm_memory_size(fifo->user.mem), 12,
NV_MEM_ACCESS_RW, &fifo->user.bar);
if (ret)
return ret;

6
drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c
View File

@@ -39,10 +39,10 @@ nvkm_bar_kmap(struct nvkm_bar *bar)
return NULL;
}
int
nvkm_bar_umap(struct nvkm_bar *bar, u64 size, int type, struct nvkm_vma *vma)
struct nvkm_vmm *
nvkm_bar_bar1_vmm(struct nvkm_device *device)
{
return bar->func->umap(bar, size, type, vma);
return device->bar->func->bar1.vmm(device->bar);
}
void

2
drivers/gpu/drm/nouveau/nvkm/subdev/bar/g84.c
View File

@@ -47,11 +47,11 @@ g84_bar_func = {
.bar1.init = nv50_bar_bar1_init,
.bar1.fini = nv50_bar_bar1_fini,
.bar1.wait = nv50_bar_bar1_wait,
.bar1.vmm = nv50_bar_bar1_vmm,
.bar2.init = nv50_bar_bar2_init,
.bar2.fini = nv50_bar_bar2_fini,
.bar2.wait = nv50_bar_bar1_wait,
.kmap = nv50_bar_kmap,
.umap = nv50_bar_umap,
.flush = g84_bar_flush,
};

9
drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c
View File

@@ -34,11 +34,10 @@ gf100_bar_kmap(struct nvkm_bar *base)
return gf100_bar(base)->bar[0].vm;
}
int
gf100_bar_umap(struct nvkm_bar *base, u64 size, int type, struct nvkm_vma *vma)
struct nvkm_vmm *
gf100_bar_bar1_vmm(struct nvkm_bar *base)
{
struct gf100_bar *bar = gf100_bar(base);
return nvkm_vm_get(bar->bar[1].vm, size, type, NV_MEM_ACCESS_RW, vma);
return gf100_bar(base)->bar[1].vm;
}
void
@@ -195,11 +194,11 @@ gf100_bar_func = {
.bar1.init = gf100_bar_bar1_init,
.bar1.fini = gf100_bar_bar1_fini,
.bar1.wait = gf100_bar_bar1_wait,
.bar1.vmm = gf100_bar_bar1_vmm,
.bar2.init = gf100_bar_bar2_init,
.bar2.fini = gf100_bar_bar2_fini,
.bar2.wait = gf100_bar_bar1_wait,
.kmap = gf100_bar_kmap,
.umap = gf100_bar_umap,
.flush = g84_bar_flush,
};

2
drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.h
View File

@@ -21,6 +21,6 @@ void *gf100_bar_dtor(struct nvkm_bar *);
int gf100_bar_oneinit(struct nvkm_bar *);
void gf100_bar_bar1_init(struct nvkm_bar *);
void gf100_bar_bar1_wait(struct nvkm_bar *);
struct nvkm_vmm *gf100_bar_bar1_vmm(struct nvkm_bar *);
void gf100_bar_bar2_init(struct nvkm_bar *);
int gf100_bar_umap(struct nvkm_bar *, u64, int, struct nvkm_vma *);
#endif

2
drivers/gpu/drm/nouveau/nvkm/subdev/bar/gk20a.c
View File

@@ -28,7 +28,7 @@ gk20a_bar_func = {
.bar1.init = gf100_bar_bar1_init,
.bar1.fini = gf100_bar_bar1_fini,
.bar1.wait = gf100_bar_bar1_wait,
.umap = gf100_bar_umap,
.bar1.vmm = gf100_bar_bar1_vmm,
.flush = g84_bar_flush,
};

15
drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c
View File

@@ -34,13 +34,6 @@ nv50_bar_kmap(struct nvkm_bar *base)
return nv50_bar(base)->bar2_vm;
}
int
nv50_bar_umap(struct nvkm_bar *base, u64 size, int type, struct nvkm_vma *vma)
{
struct nv50_bar *bar = nv50_bar(base);
return nvkm_vm_get(bar->bar1_vm, size, type, NV_MEM_ACCESS_RW, vma);
}
static void
nv50_bar_flush(struct nvkm_bar *base)
{
@@ -56,6 +49,12 @@ nv50_bar_flush(struct nvkm_bar *base)
spin_unlock_irqrestore(&bar->base.lock, flags);
}
struct nvkm_vmm *
nv50_bar_bar1_vmm(struct nvkm_bar *base)
{
return nv50_bar(base)->bar1_vm;
}
void
nv50_bar_bar1_wait(struct nvkm_bar *base)
{
@@ -229,11 +228,11 @@ nv50_bar_func = {
.bar1.init = nv50_bar_bar1_init,
.bar1.fini = nv50_bar_bar1_fini,
.bar1.wait = nv50_bar_bar1_wait,
.bar1.vmm = nv50_bar_bar1_vmm,
.bar2.init = nv50_bar_bar2_init,
.bar2.fini = nv50_bar_bar2_fini,
.bar2.wait = nv50_bar_bar1_wait,
.kmap = nv50_bar_kmap,
.umap = nv50_bar_umap,
.flush = nv50_bar_flush,
};

2
drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.h
View File

@@ -22,8 +22,8 @@ int nv50_bar_oneinit(struct nvkm_bar *);
void nv50_bar_init(struct nvkm_bar *);
void nv50_bar_bar1_init(struct nvkm_bar *);
void nv50_bar_bar1_wait(struct nvkm_bar *);
struct nvkm_vmm *nv50_bar_bar1_vmm(struct nvkm_bar *);
void nv50_bar_bar2_init(struct nvkm_bar *);
struct nvkm_vm *nv50_bar_kmap(struct nvkm_bar *);
int nv50_bar_umap(struct nvkm_bar *, u64, int, struct nvkm_vma *);
void nv50_bar_unmap(struct nvkm_bar *, struct nvkm_vma *);
#endif

2
drivers/gpu/drm/nouveau/nvkm/subdev/bar/priv.h
View File

@@ -15,10 +15,10 @@ struct nvkm_bar_func {
void (*init)(struct nvkm_bar *);
void (*fini)(struct nvkm_bar *);
void (*wait)(struct nvkm_bar *);
struct nvkm_vmm *(*vmm)(struct nvkm_bar *);
} bar1, bar2;
struct nvkm_vm *(*kmap)(struct nvkm_bar *);
int (*umap)(struct nvkm_bar *, u64 size, int type, struct nvkm_vma *);
void (*flush)(struct nvkm_bar *);
};