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Merge tag 'sunxi-dt-for-7.2-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt

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Allwinner device tree changes for 7.2 - Take 2

Some changes for old chips and some for recent ones.

- A83T gained the MIPI CSI-2 receiver
- overlays enabled for Pine64 boards
- D1s / T113 and H616 gained the high speed timer
- T113s watchdog enabled (for reboot)
- H616 gained proper SRAM regions
- A523 family gained EL2 virtual timer interrupt and GPADC
- A523 pinctrl IRQ fix

* tag 'sunxi-dt-for-7.2-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  arm64: dts: allwinner: a523: Add missing GPIO interrupt
  arm64: dts: allwinner: a523: add gpadc node
  arm64: dts: allwinner: Add EL2 virtual timer interrupt
  ARM: dts: sun8i: a83t: Add MIPI CSI-2 controller node
  dt-bindings: media: sun6i-a31-isp: Add optional interconnect properties
  dt-bindings: media: sun6i-a31-csi: Add optional interconnect properties
  arm64: dts: allwinner: sun50i-a64: Enable DT overlays
  arm: dts: allwinner: t113s: enable watchdog for reboot
  arm64: dts: allwinner: h616: add hstimer node
  riscv: dts: allwinner: d1s-t113: add hstimer node
  arm64: dts: allwinner: sun50i-h616: Add SRAM nodes

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2026-06-11 23:07:12 +02:00
parent 74b1b75a32 6b81aa0c8a
commit 564edaca14
8 changed files with 128 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml
View File

@@ -40,6 +40,12 @@ properties:
resets:
maxItems: 1
interconnects:
maxItems: 1
interconnect-names:
const: dma-mem
port:
$ref: /schemas/graph.yaml#/$defs/port-base
description: Parallel input port, connect to a parallel sensor

6
Documentation/devicetree/bindings/media/allwinner,sun6i-a31-isp.yaml
View File

@@ -36,6 +36,12 @@ properties:
resets:
maxItems: 1
interconnects:
maxItems: 1
interconnect-names:
const: dma-mem
ports:
$ref: /schemas/graph.yaml#/properties/ports

43
arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
View File

@@ -1062,6 +1062,49 @@ csi: camera@1cb0000 {
clock-names = "bus", "mod", "ram";
resets = <&ccu RST_BUS_CSI>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
csi_in_mipi_csi2: endpoint {
remote-endpoint = <&mipi_csi2_out_csi>;
};
};
};
};
mipi_csi2: csi@1cb1000 {
compatible = "allwinner,sun8i-a83t-mipi-csi2";
reg = <0x01cb1000 0x1000>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_CSI>,
<&ccu CLK_CSI_SCLK>,
<&ccu CLK_MIPI_CSI>,
<&ccu CLK_CSI_MISC>;
clock-names = "bus", "mod", "mipi", "misc";
resets = <&ccu RST_BUS_CSI>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
mipi_csi2_in: port@0 {
reg = <0>;
};
mipi_csi2_out: port@1 {
reg = <1>;
mipi_csi2_out_csi: endpoint {
remote-endpoint = <&csi_in_mipi_csi2>;
};
};
};
};
hdmi: hdmi@1ee0000 {

4
arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi
View File

@@ -90,3 +90,7 @@ cpu-crit {
};
};
};
&wdt {
status = "okay";
};

6
arch/arm64/boot/dts/allwinner/Makefile
View File

@@ -1,4 +1,10 @@
# SPDX-License-Identifier: GPL-2.0
# Enables support for device-tree overlays for named devices
DTC_FLAGS_sun50i-a64-pine64-lts := -@
DTC_FLAGS_sun50i-a64-pine64 := -@
DTC_FLAGS_sun50i-a64-pine64-plus := -@
DTC_FLAGS_sun50i-a64-sopine-baseboard := -@
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-amarula-relic.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-bananapi-m64.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-nanopi-a64.dtb

38
arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
View File

@@ -182,12 +182,38 @@ syscon: syscon@3000000 {
#size-cells = <1>;
ranges;
sram_c: sram@28000 {
/* SRAM C */
sram@28000 {
compatible = "mmio-sram";
reg = <0x00028000 0x30000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x00028000 0x30000>;
/*
* 0x0 ~ 0x20000 is partial alias of VE SRAM below.
* 0x20000 ~ 0x2ffff is (partial?) alias of DE SRAM.
* However the whole region is toggled together.
*/
sram_c: sram-section@0 {
compatible = "allwinner,sun50i-h616-sram-c",
"allwinner,sun50i-a64-sram-c";
reg = <0x00000 0x30000>;
};
};
/* VE SRAM */
sram@1a00000 {
compatible = "mmio-sram";
reg = <0x01a00000 0x200000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x01a00000 0x200000>;
ve_sram: sram-section@0 {
compatible = "allwinner,sun50i-h616-ve-sram";
reg = <0x000000 0x200000>;
};
};
};
@@ -237,6 +263,16 @@ timer0: timer@3009000 {
clocks = <&osc24M>;
};
hstimer@3005000 {
compatible = "allwinner,sun50i-h616-hstimer",
"allwinner,sun20i-d1-hstimer";
reg = <0x03005000 0x1000>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_HSTIMER>;
resets = <&ccu RST_BUS_HSTIMER>;
};
watchdog: watchdog@30090a0 {
compatible = "allwinner,sun50i-h616-wdt",
"allwinner,sun6i-a31-wdt";

19
arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
View File

@@ -101,7 +101,8 @@ timer {
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>;
};
soc {
@@ -128,7 +129,8 @@ gpu: gpu@1800000 {
pio: pinctrl@2000000 {
compatible = "allwinner,sun55i-a523-pinctrl";
reg = <0x2000000 0x800>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
@@ -340,6 +342,19 @@ ledc: led-controller@2008000 {
status = "disabled";
};
gpadc: adc@2009000 {
compatible = "allwinner,sun55i-a523-gpadc";
reg = <0x2009000 0x400>;
clocks = <&ccu CLK_BUS_GPADC0>, <&ccu CLK_GPADC0>;
clock-names = "bus", "mod";
resets = <&ccu RST_BUS_GPADC0>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
#io-channel-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
wdt: watchdog@2050000 {
compatible = "allwinner,sun55i-a523-wdt";
reg = <0x2050000 0x20>;

9
arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
View File

@@ -295,6 +295,15 @@ timer: timer@2050000 {
clocks = <&dcxo>;
};
hstimer@3008000 {
compatible = "allwinner,sun20i-d1-hstimer";
reg = <0x03008000 0x1000>;
interrupts = <SOC_PERIPHERAL_IRQ(55) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(56) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_HSTIMER>;
resets = <&ccu RST_BUS_HSTIMER>;
};
wdt: watchdog@20500a0 {
compatible = "allwinner,sun20i-d1-wdt-reset",
"allwinner,sun20i-d1-wdt";