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media: rzv2h-ivc: Fix FM_STOP register write
Bit 20 should be written in this register to stop frame processing.
So fix that, as well as the poll condition.
Cc: stable@vger.kernel.org
Fixes: f0b3984d82 ("media: platform: Add Renesas Input Video Control block driver")
Reviewed-by: Daniel Scally <dan.scally@ideasonboard.com>
Signed-off-by: Barnabás Pőcze <barnabas.pocze+renesas@ideasonboard.com>
Signed-off-by: Jacopo Mondi <jacopo.mondi+renesas@ideasonboard.com>
Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
This commit is contained in:
committed by
Hans Verkuil
parent
d901c42835
commit
562d2e0a67
@@ -297,9 +297,10 @@ static void rzv2h_ivc_stop_streaming(struct vb2_queue *q)
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struct rzv2h_ivc *ivc = vb2_get_drv_priv(q);
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u32 val = 0;
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rzv2h_ivc_write(ivc, RZV2H_IVC_REG_FM_STOP, 0x1);
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rzv2h_ivc_write(ivc, RZV2H_IVC_REG_FM_STOP, RZV2H_IVC_REG_FM_STOP_FSTOP);
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readl_poll_timeout(ivc->base + RZV2H_IVC_REG_FM_STOP,
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val, !val, 10 * USEC_PER_MSEC, 250 * USEC_PER_MSEC);
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val, !(val & RZV2H_IVC_REG_FM_STOP_FSTOP),
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10 * USEC_PER_MSEC, 250 * USEC_PER_MSEC);
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rzv2h_ivc_return_buffers(ivc, VB2_BUF_STATE_ERROR);
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video_device_pipeline_stop(&ivc->vdev.dev);
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@@ -46,6 +46,7 @@
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#define RZV2H_IVC_REG_FM_MCON 0x0104
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#define RZV2H_IVC_REG_FM_FRCON 0x0108
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#define RZV2H_IVC_REG_FM_STOP 0x010c
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#define RZV2H_IVC_REG_FM_STOP_FSTOP BIT(20)
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#define RZV2H_IVC_REG_FM_INT_EN 0x0120
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#define RZV2H_IVC_VVAL_IFPE BIT(0)
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#define RZV2H_IVC_REG_FM_INT_STA 0x0124
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