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drm/msm/dsi: Remove dsi_phy_write_[un]delay()

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These are dummy wrappers that do literally nothing interesting.
Remove them.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/590703/
Link: https://lore.kernel.org/r/20240423-topic-msm_cleanup-v1-2-b30f39f43b90@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
This commit is contained in:
Konrad Dybcio
2024-04-23 00:37:00 +02:00
committed by Dmitry Baryshkov
parent 8fd6f64ddb
commit 5372db09f4
3 changed files with 54 additions and 33 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
View File

@@ -12,9 +12,6 @@
#include "dsi.h"
#define dsi_phy_write_udelay(offset, data, delay_us) { writel((data), (offset)); udelay(delay_us); }
#define dsi_phy_write_ndelay(offset, data, delay_ns) { writel((data), (offset)); ndelay(delay_ns); }
struct msm_dsi_phy_ops {
int (*pll_init)(struct msm_dsi_phy *phy);
int (*enable)(struct msm_dsi_phy *phy,

3
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
View File

@@ -374,7 +374,8 @@ static void pll_14nm_software_reset(struct dsi_pll_14nm *pll_14nm)
writel(0, cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL);
/* pll sw reset */
dsi_phy_write_udelay(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x20, 10);
writel(0x20, cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1);
udelay(10);
wmb(); /* make sure register committed */
writel(0, cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1);

81
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
View File

@@ -104,9 +104,10 @@ static void pll_28nm_software_reset(struct dsi_pll_28nm *pll_28nm)
* Add HW recommended delays after toggling the software
* reset bit off and back on.
*/
dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG,
DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET, 1);
dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG, 0x00, 1);
writel(DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET, base + REG_DSI_28nm_PHY_PLL_TEST_CFG);
udelay(1);
writel(0, base + REG_DSI_28nm_PHY_PLL_TEST_CFG);
udelay(1);
}
/*
@@ -303,21 +304,25 @@ static int _dsi_pll_28nm_vco_prepare_hpm(struct dsi_pll_28nm *pll_28nm)
* Add necessary delays recommended by hardware.
*/
val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B;
dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 1);
writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG);
udelay(1);
val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B;
dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200);
writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG);
udelay(200);
val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B;
dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500);
writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG);
udelay(500);
val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE;
dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600);
writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG);
udelay(600);
for (i = 0; i < 2; i++) {
/* DSI Uniphy lock detect setting */
dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2,
0x0c, 100);
writel(0x0c, base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2);
udelay(100);
writel(0x0d, base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2);
/* poll for PLL ready status */
@@ -333,22 +338,28 @@ static int _dsi_pll_28nm_vco_prepare_hpm(struct dsi_pll_28nm *pll_28nm)
* Add necessary delays recommended by hardware.
*/
val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B;
dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 1);
writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG);
udelay(1);
val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B;
dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200);
writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG);
udelay(200);
val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B;
dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 250);
writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG);
udelay(250);
val &= ~DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B;
dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200);
writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG);
udelay(200);
val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B;
dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500);
writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG);
udelay(500);
val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE;
dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600);
writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG);
udelay(600);
}
if (unlikely(!locked))
@@ -399,20 +410,23 @@ static int dsi_pll_28nm_vco_prepare_8226(struct clk_hw *hw)
writel(0x34, base + REG_DSI_28nm_PHY_PLL_CAL_CFG1);
val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B;
dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200);
writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG);
udelay(200);
val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B;
dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200);
writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG);
udelay(200);
val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B;
val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE;
dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600);
writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG);
udelay(600);
for (i = 0; i < 7; i++) {
/* DSI Uniphy lock detect setting */
writel(0x0d, base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2);
dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2,
0x0c, 100);
writel(0x0c, base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2);
udelay(100);
writel(0x0d, base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2);
/* poll for PLL ready status */
@@ -427,15 +441,18 @@ static int dsi_pll_28nm_vco_prepare_8226(struct clk_hw *hw)
* PLL power up sequence.
* Add necessary delays recommended by hardware.
*/
dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_PWRGEN_CFG, 0x00, 50);
writel(0x00, base + REG_DSI_28nm_PHY_PLL_PWRGEN_CFG);
udelay(50);
val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B;
val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B;
dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 100);
writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG);
udelay(100);
val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B;
val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE;
dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600);
writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG);
udelay(600);
}
if (unlikely(!locked))
@@ -466,21 +483,27 @@ static int dsi_pll_28nm_vco_prepare_lp(struct clk_hw *hw)
* PLL power up sequence.
* Add necessary delays recommended by hardware.
*/
dsi_phy_write_ndelay(base + REG_DSI_28nm_PHY_PLL_CAL_CFG1, 0x34, 500);
writel(0x34, base + REG_DSI_28nm_PHY_PLL_CAL_CFG1);
ndelay(500);
val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B;
dsi_phy_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500);
writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG);
ndelay(500);
val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B;
dsi_phy_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500);
writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG);
ndelay(500);
val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B |
DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE;
dsi_phy_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500);
writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG);
ndelay(500);
/* DSI PLL toggle lock detect setting */
dsi_phy_write_ndelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x04, 500);
dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x05, 512);
writel(0x04, base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2);
ndelay(500);
writel(0x05, base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2);
udelay(512);
locked = pll_28nm_poll_for_ready(pll_28nm, max_reads, timeout_us);