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arm64: dts: qcom: sm7280: remove assigned-clock-rate property for mdp clk

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Drop the assigned clock rate property and vote on the mdp clock as per
calculated value during the usecase.

This patch is dependent on the patch ("drm/msm/disp/dpu1: set mdp clk
to the maximum frequency in opp table during probe") [1].

[1] https://lore.kernel.org/r/1647269217-14064-2-git-send-email-quic_vpolimer@quicinc.com/

Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1647919631-14447-3-git-send-email-quic_vpolimer@quicinc.com
This commit is contained in:
Vinod Polimera
2022-03-22 08:57:08 +05:30
committed by Bjorn Andersson
parent f2906aa863
commit 5241fd7fee
1 changed files with 2 additions and 7 deletions
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9
arch/arm64/boot/dts/qcom/sc7280.dtsi
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@@ -3426,9 +3426,6 @@ mdss: display-subsystem@ae00000 {
"ahb",
"core";
assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
assigned-clock-rates = <300000000>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
@@ -3462,11 +3459,9 @@ mdss_mdp: display-controller@ae01000 {
"lut",
"core",
"vsync";
assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_VSYNC_CLK>,
assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>;
assigned-clock-rates = <300000000>,
<19200000>,
assigned-clock-rates = <19200000>,
<19200000>;
operating-points-v2 = <&mdp_opp_table>;
power-domains = <&rpmhpd SC7280_CX>;