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net/mlx5: HWS, Rightsize bwc matcher priority

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The bwc layer was clamping the matcher priority from 32 bits to 16 bits.
This didn't show up until a matcher was resized, since the initial
native matcher was created using the correct 32 bit value.

The fix also reorders fields to avoid some padding.

Fixes: 2111bb970c ("net/mlx5: HWS, added backward-compatible API handling")
Signed-off-by: Vlad Dogaru <vdogaru@nvidia.com>
Reviewed-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
Reviewed-by: Mark Bloch <mbloch@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Link: https://patch.msgid.link/1741644104-97767-3-git-send-email-tariqt@nvidia.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
This commit is contained in:
Vlad Dogaru
2025-03-11 00:01:40 +02:00
committed by Paolo Abeni
parent 03ebae1992
commit 521992337f
1 changed files with 1 additions and 1 deletions
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2
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.h
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@@ -24,8 +24,8 @@ struct mlx5hws_bwc_matcher {
struct mlx5hws_matcher *matcher;
struct mlx5hws_match_template *mt;
struct mlx5hws_action_template *at[MLX5HWS_BWC_MATCHER_ATTACH_AT_NUM];
u32 priority;
u8 num_of_at;
u16 priority;
u8 size_log;
atomic_t num_of_rules;
struct list_head *rules;