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perf list: Add IBM z17 event descriptions
Update IBM z17 counter description using document SA23-2260-08: "The Load-Program-Parameter and the CPU-Measurement Facilities" released in May 2025 to include counter definitions for IBM z17 counter sets: * Basic counter set * Problem/user counter set * Crypto counter set. Use document SA23-2261-09: "The CPU-Measurement Facility Extended Counters Definition for z10, z196/z114, zEC12/zBC12, z13/z13s, z14, z15, z16 and z17" released on April 2025 to include counter definitions for IBM z17 * Extended counter set * MT-Diagnostic counter set. Use document SA22-7832-14: "z/Architecture Principles of Operation." released in April 2025 to include counter definitions for IBM z17 * PAI-Crypto counter set * PAI-Extention counter set. Use document "CPU MF Formulas and Updates April 2025" released in April 2025 to include metric calculations. Signed-off-by: Thomas Richter <tmricht@linux.ibm.com> Acked-by: Sumanth Korikkar <sumanthk@linux.ibm.com> Reviewed-by: Ian Rogers <irogers@google.com> Link: https://lore.kernel.org/r/20250623132731.899525-1-tmricht@linux.ibm.com Signed-off-by: Namhyung Kim <namhyung@kernel.org>
This commit is contained in:
Thomas Richter
committed by
Namhyung Kim
Namhyung Kim
parent
1fdf938168
commit
508b228942
58
tools/perf/pmu-events/arch/s390/cf_z17/basic.json
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58
tools/perf/pmu-events/arch/s390/cf_z17/basic.json
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@@ -0,0 +1,58 @@
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[
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{
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"Unit": "CPU-M-CF",
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"EventCode": "0",
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"EventName": "CPU_CYCLES",
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"BriefDescription": "Cycle Count",
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"PublicDescription": "This counter counts the total number of CPU cycles, excluding the number of cycles while the CPU is in the wait state."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "1",
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"EventName": "INSTRUCTIONS",
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"BriefDescription": "Instruction Count",
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"PublicDescription": "This counter counts the total number of instructions executed by the CPU."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "2",
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"EventName": "L1I_DIR_WRITES",
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"BriefDescription": "Level-1 I-Cache Directory Write Count",
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"PublicDescription": "This counter counts the total number of level-1 instruction-cache or unified-cache directory writes."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "3",
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"EventName": "L1I_PENALTY_CYCLES",
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"BriefDescription": "Level-1 I-Cache Penalty Cycle Count",
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"PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 instruction cache or unified cache."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "4",
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"EventName": "L1D_DIR_WRITES",
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"BriefDescription": "Level-1 D-Cache Directory Write Count",
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"PublicDescription": "This counter counts the total number of level-1 data-cache directory writes."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "5",
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"EventName": "L1D_PENALTY_CYCLES",
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"BriefDescription": "Level-1 D-Cache Penalty Cycle Count",
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"PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 data cache."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "32",
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"EventName": "PROBLEM_STATE_CPU_CYCLES",
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"BriefDescription": "Problem-State Cycle Count",
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"PublicDescription": "This counter counts the total number of CPU cycles when the CPU is in the problem state, excluding the number of cycles while the CPU is in the wait state."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "33",
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"EventName": "PROBLEM_STATE_INSTRUCTIONS",
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"BriefDescription": "Problem-State Instruction Count",
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"PublicDescription": "This counter counts the total number of instructions executed by the CPU while in the problem state."
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}
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]
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142
tools/perf/pmu-events/arch/s390/cf_z17/crypto6.json
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142
tools/perf/pmu-events/arch/s390/cf_z17/crypto6.json
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@@ -0,0 +1,142 @@
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[
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{
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"Unit": "CPU-M-CF",
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"EventCode": "64",
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"EventName": "PRNG_FUNCTIONS",
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"BriefDescription": "PRNG Function Count",
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"PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions issued by the CPU."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "65",
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"EventName": "PRNG_CYCLES",
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"BriefDescription": "PRNG Cycle Count",
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"PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES/SHA coprocessor is busy performing the pseudorandom- number-generation functions issued by the CPU."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "66",
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"EventName": "PRNG_BLOCKED_FUNCTIONS",
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"BriefDescription": "PRNG Blocked Function Count",
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"PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions that are issued by the CPU and are blocked because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "67",
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"EventName": "PRNG_BLOCKED_CYCLES",
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"BriefDescription": "PRNG Blocked Cycle Count",
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"PublicDescription": "This counter counts the total number of CPU cycles blocked for the pseudorandom-number-generation functions issued by the CPU because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "68",
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"EventName": "SHA_FUNCTIONS",
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"BriefDescription": "SHA Function Count",
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"PublicDescription": "This counter counts the total number of the SHA functions issued by the CPU."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "69",
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"EventName": "SHA_CYCLES",
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"BriefDescription": "SHA Cycle Count",
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"PublicDescription": "This counter counts the total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "70",
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"EventName": "SHA_BLOCKED_FUNCTIONS",
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"BriefDescription": "SHA Blocked Function Count",
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"PublicDescription": "This counter counts the total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "71",
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"EventName": "SHA_BLOCKED_CYCLES",
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"BriefDescription": "SHA Blocked Cycle Count",
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"PublicDescription": "This counter counts the total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "72",
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"EventName": "DEA_FUNCTIONS",
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"BriefDescription": "DEA Function Count",
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"PublicDescription": "This counter counts the total number of the DEA functions issued by the CPU."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "73",
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"EventName": "DEA_CYCLES",
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"BriefDescription": "DEA Cycle Count",
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"PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "74",
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"EventName": "DEA_BLOCKED_FUNCTIONS",
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"BriefDescription": "DEA Blocked Function Count",
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"PublicDescription": "This counter counts the total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "75",
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"EventName": "DEA_BLOCKED_CYCLES",
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"BriefDescription": "DEA Blocked Cycle Count",
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"PublicDescription": "This counter counts the total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "76",
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"EventName": "AES_FUNCTIONS",
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"BriefDescription": "AES Function Count",
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"PublicDescription": "This counter counts the total number of the AES functions issued by the CPU."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "77",
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"EventName": "AES_CYCLES",
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"BriefDescription": "AES Cycle Count",
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"PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "78",
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"EventName": "AES_BLOCKED_FUNCTIONS",
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"BriefDescription": "AES Blocked Function Count",
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"PublicDescription": "This counter counts the total number of the AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "79",
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"EventName": "AES_BLOCKED_CYCLES",
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"BriefDescription": "AES Blocked Cycle Count",
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"PublicDescription": "This counter counts the total number of CPU cycles blocked for the AES functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "80",
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"EventName": "ECC_FUNCTION_COUNT",
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"BriefDescription": "ECC Function Count",
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"PublicDescription": "This counter counts the total number of the elliptic-curve cryptography (ECC) functions issued by the CPU."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "81",
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"EventName": "ECC_CYCLES_COUNT",
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"BriefDescription": "ECC Cycles Count",
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"PublicDescription": "This counter counts the total number of CPU cycles when the ECC coprocessor is busy performing the elliptic-curve cryptography (ECC) functions issued by the CPU."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "82",
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"EventName": "ECC_BLOCKED_FUNCTION_COUNT",
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"BriefDescription": "Ecc Blocked Function Count",
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"PublicDescription": "This counter counts the total number of the elliptic-curve cryptography (ECC) functions that are issued by the CPU and are blocked because the ECC coprocessor is busy performing a function issued by another CPU."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "83",
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"EventName": "ECC_BLOCKED_CYCLES_COUNT",
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"BriefDescription": "ECC Blocked Cycles Count",
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"PublicDescription": "This counter counts the total number of CPU cycles blocked for the elliptic-curve cryptography (ECC) functions issued by the CPU because the ECC coprocessor is busy performing a function issued by another CPU."
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}
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]
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541
tools/perf/pmu-events/arch/s390/cf_z17/extended.json
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541
tools/perf/pmu-events/arch/s390/cf_z17/extended.json
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@@ -0,0 +1,541 @@
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[
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{
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"Unit": "CPU-M-CF",
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"EventCode": "128",
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"EventName": "L1D_RO_EXCL_WRITES",
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"BriefDescription": "L1D Read-only Exclusive Writes",
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"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "129",
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"EventName": "DTLB2_WRITES",
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"BriefDescription": "DTLB2 Writes",
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"PublicDescription": "A translation has been written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the Level-1 Data cache. This is a replacement for what was provided for the DTLB on z13 and prior machines."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "130",
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"EventName": "DTLB2_MISSES",
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"BriefDescription": "DTLB2 Misses",
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"PublicDescription": "A TLB2 miss is in progress for a request made by the Level-1 Data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on this cycle. This is a replacement for what was provided for the DTLB on z13 and prior machines."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "131",
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"EventName": "CRSTE_1MB_WRITES",
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"BriefDescription": "One Megabyte CRSTE writes",
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"PublicDescription": "A translation entry was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "132",
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"EventName": "DTLB2_GPAGE_WRITES",
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"BriefDescription": "DTLB2 Two-Gigabyte Page Writes",
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"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "134",
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"EventName": "ITLB2_WRITES",
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"BriefDescription": "ITLB2 Writes",
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"PublicDescription": "A translation entry has been written into the Translation Lookaside Buffer 2 (TLB2) and the request was made by the Level-1 Instruction cache. This is a replacement for what was provided for the ITLB on z13 and prior machines."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "135",
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"EventName": "ITLB2_MISSES",
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"BriefDescription": "ITLB2 Misses",
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"PublicDescription": "A TLB2 miss is in progress for a request made by the Level-1 Instruction cache. Incremented by one for every TLB2 miss in progress for the Level-1 Instruction cache in a cycle. This is a replacement for what was provided for the ITLB on z13 and prior machines."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "137",
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"EventName": "TLB2_PTE_WRITES",
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"BriefDescription": "TLB2 Page Table Entry Writes",
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"PublicDescription": "A translation entry was written into the Page Table Entry array in the Level-2 TLB."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "138",
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"EventName": "TLB2_CRSTE_WRITES",
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"BriefDescription": "TLB2 Combined Region and Segment Entry Writes",
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"PublicDescription": "Translation entries were written into the Combined Region and Segment Table Entry array and the Page Table Entry array in the Level-2 TLB."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "139",
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"EventName": "TLB2_ENGINES_BUSY",
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"BriefDescription": "TLB2 Engines Busy",
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"PublicDescription": "The number of Level-2 TLB translation engines busy in a cycle."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "140",
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"EventName": "TX_C_TEND",
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"BriefDescription": "Completed TEND instructions in constrained TX mode",
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"PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "141",
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"EventName": "TX_NC_TEND",
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"BriefDescription": "Completed TEND instructions in non-constrained TX mode",
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"PublicDescription": "A TEND instruction has completed in a non-constrained transactional-execution mode."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "143",
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"EventName": "L1C_TLB2_MISSES",
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"BriefDescription": "L1C TLB2 Misses",
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"PublicDescription": "Increments by one for any cycle where a Level-1 cache or Level-2 TLB miss is in progress."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "145",
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"EventName": "DCW_REQ",
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"BriefDescription": "Directory Write Level 1 Data Cache from L2-Cache",
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"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "146",
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"EventName": "DCW_REQ_IV",
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"BriefDescription": "Directory Write Level 1 Data Cache from L2-Cache with Intervention",
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"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache with intervention."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "147",
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"EventName": "DCW_REQ_CHIP_HIT",
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"BriefDescription": "Directory Write Level 1 Data Cache from L2-Cache with Chip HP Hit",
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"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache after using chip level horizontal persistence, Chip-HP hit."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "148",
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"EventName": "DCW_REQ_DRAWER_HIT",
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"BriefDescription": "Directory Write Level 1 Data Cache from L2-Cache with Drawer HP Hit",
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"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "149",
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"EventName": "DCW_ON_CHIP",
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"BriefDescription": "Directory Write Level 1 Data Cache from On-Chip L2-Cache",
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"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "150",
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"EventName": "DCW_ON_CHIP_IV",
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"BriefDescription": "Directory Write Level 1 Data Cache from On-Chip L2-Cache with Intervention",
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"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache with intervention."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "151",
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"EventName": "DCW_ON_CHIP_CHIP_HIT",
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"BriefDescription": "Directory Write Level 1 Data Cache from On-Chip L2-Cache with Chip HP Hit",
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"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache after using chip level horizontal persistence, Chip-HP hit."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "152",
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"EventName": "DCW_ON_CHIP_DRAWER_HIT",
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"BriefDescription": "Directory Write Level 1 Data Cache from On-Chip L2-Cache with Drawer HP Hit",
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"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "153",
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"EventName": "DCW_ON_MODULE",
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"BriefDescription": "Directory Write Level 1 Data Cache from On-Module L2-Cache",
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"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Module Level-2 cache."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "154",
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"EventName": "DCW_ON_DRAWER",
|
||||
"BriefDescription": "Directory Write Level 1 Data Cache from On-Drawer L2-Cache",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "155",
|
||||
"EventName": "DCW_OFF_DRAWER",
|
||||
"BriefDescription": "Directory Write Level 1 Data Cache from Off-Drawer L2-Cache",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "156",
|
||||
"EventName": "DCW_ON_CHIP_MEMORY",
|
||||
"BriefDescription": "Directory Write Level 1 Cache from On-Chip Memory",
|
||||
"PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from On-Chip memory."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "157",
|
||||
"EventName": "DCW_ON_MODULE_MEMORY",
|
||||
"BriefDescription": "Directory Write Level 1 Cache from On-Module Memory",
|
||||
"PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from On-Module memory."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "158",
|
||||
"EventName": "DCW_ON_DRAWER_MEMORY",
|
||||
"BriefDescription": "Directory Write Level 1 Cache from On-Drawer Memory",
|
||||
"PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer memory."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "159",
|
||||
"EventName": "DCW_OFF_DRAWER_MEMORY",
|
||||
"BriefDescription": "Directory Write Level 1 Cache from Off-Drawer Memory",
|
||||
"PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from Off-Drawer memory."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "160",
|
||||
"EventName": "IDCW_ON_MODULE_IV",
|
||||
"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Module Memory L2-Cache with Intervention",
|
||||
"PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache with intervention."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "161",
|
||||
"EventName": "IDCW_ON_MODULE_CHIP_HIT",
|
||||
"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Module Memory L2-Cache with Chip Hit",
|
||||
"PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache after using chip level horizontal persistence, Chip-HP hit."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "162",
|
||||
"EventName": "IDCW_ON_MODULE_DRAWER_HIT",
|
||||
"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Module Memory L2-Cache with Drawer Hit",
|
||||
"PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "163",
|
||||
"EventName": "IDCW_ON_DRAWER_IV",
|
||||
"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Drawer L2-Cache with Intervention",
|
||||
"PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache with intervention."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "164",
|
||||
"EventName": "IDCW_ON_DRAWER_CHIP_HIT",
|
||||
"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Drawer L2-Cache with Chip Hit",
|
||||
"PublicDescription": "A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache after using chip level horizontal persistence, Chip-HP hit."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "165",
|
||||
"EventName": "IDCW_ON_DRAWER_DRAWER_HIT",
|
||||
"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Drawer L2-Cache with Drawer Hit",
|
||||
"PublicDescription": "A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "166",
|
||||
"EventName": "IDCW_OFF_DRAWER_IV",
|
||||
"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from Off-Drawer L2-Cache with Intervention",
|
||||
"PublicDescription": "A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache with intervention."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "167",
|
||||
"EventName": "IDCW_OFF_DRAWER_CHIP_HIT",
|
||||
"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from Off-Drawer L2-Cache with Chip Hit",
|
||||
"PublicDescription": "A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache after using chip level horizontal persistence, Chip-HP hit."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "168",
|
||||
"EventName": "IDCW_OFF_DRAWER_DRAWER_HIT",
|
||||
"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from Off-Drawer L2-Cache with Drawer Hit",
|
||||
"PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "169",
|
||||
"EventName": "ICW_REQ",
|
||||
"BriefDescription": "Directory Write Level 1 Instruction Cache from L2-Cache",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced the requestors Level-2 cache."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "170",
|
||||
"EventName": "ICW_REQ_IV",
|
||||
"BriefDescription": "Directory Write Level 1 Instruction Cache from L2-Cache with Intervention",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestors Level-2 cache with intervention."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "171",
|
||||
"EventName": "ICW_REQ_CHIP_HIT",
|
||||
"BriefDescription": "Directory Write Level 1 Instruction Cache from L2-Cache with Chip HP Hit",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestors Level-2 cache after using chip level horizontal persistence, Chip-HP hit."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "172",
|
||||
"EventName": "ICW_REQ_DRAWER_HIT",
|
||||
"BriefDescription": "Directory Write Level 1 Instruction Cache from L2-Cache with Drawer HP Hit",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestors Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "173",
|
||||
"EventName": "ICW_ON_CHIP",
|
||||
"BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip L2-Cache",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip Level-2 cache."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "174",
|
||||
"EventName": "ICW_ON_CHIP_IV",
|
||||
"BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip L2-Cache with Intervention",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip Level-2 cache with intervention."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "175",
|
||||
"EventName": "ICW_ON_CHIP_CHIP_HIT",
|
||||
"BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip L2-Cache with Chip HP Hit",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip Level-2 cache after using chip level horizontal persistence, Chip-HP hit."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "176",
|
||||
"EventName": "ICW_ON_CHIP_DRAWER_HIT",
|
||||
"BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip L2-Cache with Drawer HP Hit",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip level 2 cache after using drawer level horizontal persistence, Drawer-HP hit."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "177",
|
||||
"EventName": "ICW_ON_MODULE",
|
||||
"BriefDescription": "Directory Write Level 1 Instruction Cache from On-Module L2-Cache",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "178",
|
||||
"EventName": "ICW_ON_DRAWER",
|
||||
"BriefDescription": "Directory Write Level 1 Instruction Cache from On-Drawer L2-Cache",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "179",
|
||||
"EventName": "ICW_OFF_DRAWER",
|
||||
"BriefDescription": "Directory Write Level 1 Instruction Cache from Off-Drawer L2-Cache",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "202",
|
||||
"EventName": "CYCLES_SAMETHRD",
|
||||
"BriefDescription": "CPU is not in wait state and CPU is running by itself",
|
||||
"PublicDescription": "The number of cycles the CPU is not in wait state and the CPU is running by itself on the Core."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "203",
|
||||
"EventName": "CYCLES_DIFFTHRD",
|
||||
"BriefDescription": "CPU is not in wait state and CPU is running by another thread",
|
||||
"PublicDescription": "The number of cycles the CPU is not in wait state and the CPU is running with another thread on the Core."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "204",
|
||||
"EventName": "INST_SAMETHRD",
|
||||
"BriefDescription": "Instructions executed on CPU by itself",
|
||||
"PublicDescription": "The number of instructions executed on the CPU and the CPU is running by itself on the Core."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "205",
|
||||
"EventName": "INST_DIFFTHRD",
|
||||
"BriefDescription": "Instructions executed on CPU by another thread",
|
||||
"PublicDescription": "The number of instructions executed on the CPU and the CPU is running with another thread on the Core."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "206",
|
||||
"EventName": "WRONG_BRANCH_PREDICTION",
|
||||
"BriefDescription": "Incorrect branch prediction on core",
|
||||
"PublicDescription": "A count of the number of branches that were predicted incorrectly by the branch prediction logic in the Core. This includes incorrectly predicted branches that are executed in Firmware. Examples of instructions implemented in Firmware are complicated instructions like MVCL (Move Character Long) and PC (Program Call)."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "225",
|
||||
"EventName": "VX_BCD_EXECUTION_SLOTS",
|
||||
"BriefDescription": "Count finished vector arithmetic Binary Coded Decimal instructions",
|
||||
"PublicDescription": "Count of floating point execution slots used for finished vector arithmetic Binary Coded Decimal instructions. Instructions: VAP, VSP, VMP, VMSP, VDP, VSDP, VRP, VLIP, VSRP, VPSOP, VCP, VTP, VPKZ, VUPKZ, VCVB, VCVBG, VCVD, VCVDG, VSCHP, VSCSHP, VCSPH, VCLZDP, VPKZR, VSRPR, VUPKZH, VUPKZL, VTZ, VUPH, VUPL, VCVBX, VCVDX."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "226",
|
||||
"EventName": "DECIMAL_INSTRUCTIONS",
|
||||
"BriefDescription": "Decimal instruction dispatched",
|
||||
"PublicDescription": "Decimal instruction dispatched. Instructions: CVB, CVD, AP, CP, DP, ED, EDMK, MP, SRP, SP, ZAP, TP."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "232",
|
||||
"EventName": "LAST_HOST_TRANSLATIONS",
|
||||
"BriefDescription": "Last host translation done",
|
||||
"PublicDescription": "Last Host Translation done."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "244",
|
||||
"EventName": "TX_NC_TABORT",
|
||||
"BriefDescription": "Aborted transactions in unconstrained TX mode",
|
||||
"PublicDescription": "A transaction abort has occurred in a non-constrained transactional-execution mode."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "245",
|
||||
"EventName": "TX_C_TABORT_NO_SPECIAL",
|
||||
"BriefDescription": "Aborted transactions in constrained TX mode",
|
||||
"PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "246",
|
||||
"EventName": "TX_C_TABORT_SPECIAL",
|
||||
"BriefDescription": "Aborted transactions in constrained TX mode using special completion logic",
|
||||
"PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "248",
|
||||
"EventName": "DFLT_ACCESS",
|
||||
"BriefDescription": "Cycles CPU spent obtaining access to Deflate unit",
|
||||
"PublicDescription": "Cycles CPU spent obtaining access to Deflate unit."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "253",
|
||||
"EventName": "DFLT_CYCLES",
|
||||
"BriefDescription": "Cycles CPU is using Deflate unit",
|
||||
"PublicDescription": "Cycles CPU is using Deflate unit."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "256",
|
||||
"EventName": "SORTL",
|
||||
"BriefDescription": "Count SORTL instructions",
|
||||
"PublicDescription": "Increments by one for every SORT LISTS (SORTL) instruction executed."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "265",
|
||||
"EventName": "DFLT_CC",
|
||||
"BriefDescription": "Increments DEFLATE CONVERSION CALL",
|
||||
"PublicDescription": "Increments by one for every DEFLATE CONVERSION CALL (DFLTCC) instruction executed."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "266",
|
||||
"EventName": "DFLT_CCFINISH",
|
||||
"BriefDescription": "Increments completed DEFLATE CONVERSION CALL",
|
||||
"PublicDescription": "Increments by one for every DEFLATE CONVERSION CALL (DFLTCC) instruction executed that ended in Condition Codes 0, 1 or 2."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "267",
|
||||
"EventName": "NNPA_INVOCATIONS",
|
||||
"BriefDescription": "NNPA Total invocations",
|
||||
"PublicDescription": "Increments by one for every NEURAL NETWORK PROCESSING ASSIST (NNPA) instruction executed."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "268",
|
||||
"EventName": "NNPA_COMPLETIONS",
|
||||
"BriefDescription": "NNPA Total completions",
|
||||
"PublicDescription": "Increments by one for every NEURAL NETWORK PROCESSING ASSIST (NNPA) instruction executed that ended in Condition Code 0."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "269",
|
||||
"EventName": "NNPA_WAIT_LOCK",
|
||||
"BriefDescription": "Cycles spent obtaining NNPA lock",
|
||||
"PublicDescription": "Cycles CPU spent obtaining access to IBM Z Integrated Accelerator for AI."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "270",
|
||||
"EventName": "NNPA_HOLD_LOCK",
|
||||
"BriefDescription": "Cycles spent holding NNPA lock",
|
||||
"PublicDescription": "Cycles CPU is using IBM Z Integrated Accelerator for AI."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "272",
|
||||
"EventName": "NNPA_INST_ONCHIP",
|
||||
"BriefDescription": "NNPA instructions used on-chip Integrated Accelerator",
|
||||
"PublicDescription": "A NEURAL NETWORK PROCESSING ASSIST (NNPA) instruction has used the Local On-Chip IBM Z Integrated Accelerator for AI during its execution"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "273",
|
||||
"EventName": "NNPA_INST_OFFCHIP",
|
||||
"BriefDescription": "NNPA instructions used off-chip Integrated Accelerator",
|
||||
"PublicDescription": "A NEURAL NETWORK PROCESSING ASSIST (NNPA) instruction has used an Off-Chip IBM Z Integrated Accelerator for AI during its execution."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "274",
|
||||
"EventName": "NNPA_INST_DIFF",
|
||||
"BriefDescription": "NNPA instructions used different Integrated Accelerator",
|
||||
"PublicDescription": "A NEURAL NETWORK PROCESSING ASSIST (NNPA) instruction has used a different IBM Z Integrated Accelerator for AI since it was last executed."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "276",
|
||||
"EventName": "NNPA_4K_PREFETCH",
|
||||
"BriefDescription": "Number of 4K prefetches for Integated Accelerator",
|
||||
"PublicDescription": "Number of 4K prefetches done for a remote IBM Z Integated Accelerator for AI."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "277",
|
||||
"EventName": "NNPA_COMPL_LOCK",
|
||||
"BriefDescription": "A Perform Locked Operation has completed",
|
||||
"PublicDescription": "A PERFORM LOCKED OPERATION (PLO) has completed."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "278",
|
||||
"EventName": "NNPA_RETRY_LOCK",
|
||||
"BriefDescription": "A Perform Locked Operation has been retried",
|
||||
"PublicDescription": "A PERFORM LOCKED OPERATION (PLO) has been retried and the CPU did not use any special logic to allow the PLO to complete."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "279",
|
||||
"EventName": "NNPA_RETRY_LOCK_WITH_PLO",
|
||||
"BriefDescription": "A Perform Locked Operation has been retried using special logic",
|
||||
"PublicDescription": "A PERFORM LOCKED OPERATION (PLO) has been retried and the CPU is using special logic to allow PLO to complete."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "448",
|
||||
"EventName": "MT_DIAG_CYCLES_ONE_THR_ACTIVE",
|
||||
"BriefDescription": "Cycle count with one thread active",
|
||||
"PublicDescription": "Cycle count with one thread active"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "449",
|
||||
"EventName": "MT_DIAG_CYCLES_TWO_THR_ACTIVE",
|
||||
"BriefDescription": "Cycle count with two threads active",
|
||||
"PublicDescription": "Cycle count with two threads active"
|
||||
}
|
||||
]
|
||||
1213
tools/perf/pmu-events/arch/s390/cf_z17/pai_crypto.json
Normal file
1213
tools/perf/pmu-events/arch/s390/cf_z17/pai_crypto.json
Normal file
File diff suppressed because it is too large
Load Diff
261
tools/perf/pmu-events/arch/s390/cf_z17/pai_ext.json
Normal file
261
tools/perf/pmu-events/arch/s390/cf_z17/pai_ext.json
Normal file
@@ -0,0 +1,261 @@
|
||||
[
|
||||
{
|
||||
"Unit": "PAI-EXT",
|
||||
"EventCode": "6144",
|
||||
"EventName": "NNPA_ALL",
|
||||
"BriefDescription": "NNPA ALL",
|
||||
"PublicDescription": "Sums of all non zero NNPA counters"
|
||||
},
|
||||
{
|
||||
"Unit": "PAI-EXT",
|
||||
"EventCode": "6145",
|
||||
"EventName": "NNPA_ADD",
|
||||
"BriefDescription": "NNPA ADD function",
|
||||
"PublicDescription": "NNPA-ADD function ending with CC=0"
|
||||
},
|
||||
{
|
||||
"Unit": "PAI-EXT",
|
||||
"EventCode": "6146",
|
||||
"EventName": "NNPA_SUB",
|
||||
"BriefDescription": "NNPA SUB function",
|
||||
"PublicDescription": "NNPA-SUB function ending with CC=0"
|
||||
},
|
||||
{
|
||||
"Unit": "PAI-EXT",
|
||||
"EventCode": "6147",
|
||||
"EventName": "NNPA_MUL",
|
||||
"BriefDescription": "NNPA MUL function",
|
||||
"PublicDescription": "NNPA-MUL function ending with CC=0"
|
||||
},
|
||||
{
|
||||
"Unit": "PAI-EXT",
|
||||
"EventCode": "6148",
|
||||
"EventName": "NNPA_DIV",
|
||||
"BriefDescription": "NNPA_DIV function",
|
||||
"PublicDescription": "NNPA-DIV function ending with CC=0"
|
||||
},
|
||||
{
|
||||
"Unit": "PAI-EXT",
|
||||
"EventCode": "6149",
|
||||
"EventName": "NNPA_MIN",
|
||||
"BriefDescription": "NNPA MIN function",
|
||||
"PublicDescription": "NNPA-MIN function ending with CC=0"
|
||||
},
|
||||
{
|
||||
"Unit": "PAI-EXT",
|
||||
"EventCode": "6150",
|
||||
"EventName": "NNPA_MAX",
|
||||
"BriefDescription": "NNPA MAX function",
|
||||
"PublicDescription": "NNPA-MAX function ending with CC=0"
|
||||
},
|
||||
{
|
||||
"Unit": "PAI-EXT",
|
||||
"EventCode": "6151",
|
||||
"EventName": "NNPA_LOG",
|
||||
"BriefDescription": "NNPA LOG function",
|
||||
"PublicDescription": "NNPA Log function ending with CC=0"
|
||||
},
|
||||
{
|
||||
"Unit": "PAI-EXT",
|
||||
"EventCode": "6152",
|
||||
"EventName": "NNPA_EXP",
|
||||
"BriefDescription": "NNPA EXP function",
|
||||
"PublicDescription": "NNPA-EXP function ending with CC=0"
|
||||
},
|
||||
{
|
||||
"Unit": "PAI-EXT",
|
||||
"EventCode": "6153",
|
||||
"EventName": "NNPA_IBM_RESERVED_9",
|
||||
"BriefDescription": "Reserved for IBM use",
|
||||
"PublicDescription": "Reserved for IBM use"
|
||||
},
|
||||
{
|
||||
"Unit": "PAI-EXT",
|
||||
"EventCode": "6154",
|
||||
"EventName": "NNPA_RELU",
|
||||
"BriefDescription": "NNPA RELU function",
|
||||
"PublicDescription": "NNPA-RELU function ending with CC=0"
|
||||
},
|
||||
{
|
||||
"Unit": "PAI-EXT",
|
||||
"EventCode": "6155",
|
||||
"EventName": "NNPA_TANH",
|
||||
"BriefDescription": "NNPA TANH function",
|
||||
"PublicDescription": "NNPA-TANH function ending with CC=0"
|
||||
},
|
||||
{
|
||||
"Unit": "PAI-EXT",
|
||||
"EventCode": "6156",
|
||||
"EventName": "NNPA_SIGMOID",
|
||||
"BriefDescription": "NNPA SIGMOID function",
|
||||
"PublicDescription": "NNPA-SIGMOID function ending with CC=0"
|
||||
},
|
||||
{
|
||||
"Unit": "PAI-EXT",
|
||||
"EventCode": "6157",
|
||||
"EventName": "NNPA_SOFTMAX",
|
||||
"BriefDescription": "NNPA SOFTMAX function",
|
||||
"PublicDescription": "NNPA-SOFTMAX function ending with CC=0"
|
||||
},
|
||||
{
|
||||
"Unit": "PAI-EXT",
|
||||
"EventCode": "6158",
|
||||
"EventName": "NNPA_BATCHNORM",
|
||||
"BriefDescription": "NNPA BATCHNORM function",
|
||||
"PublicDescription": "NNPA-BATCHNORM function ending with CC=0"
|
||||
},
|
||||
{
|
||||
"Unit": "PAI-EXT",
|
||||
"EventCode": "6159",
|
||||
"EventName": "NNPA_MAXPOOL2D",
|
||||
"BriefDescription": "NNPA MAXPOOL2D function",
|
||||
"PublicDescription": "NNPA-MAXPOOL2D function ending with CC=0"
|
||||
},
|
||||
{
|
||||
"Unit": "PAI-EXT",
|
||||
"EventCode": "6160",
|
||||
"EventName": "NNPA_AVGPOOL2D",
|
||||
"BriefDescription": "NNPA_AVGPOOL2D function",
|
||||
"PublicDescription": "NNPA-AVGPOOL2D function ending with CC=0"
|
||||
},
|
||||
{
|
||||
"Unit": "PAI-EXT",
|
||||
"EventCode": "6161",
|
||||
"EventName": "NNPA_LSTMACT",
|
||||
"BriefDescription": "NNPA LSTMACT function",
|
||||
"PublicDescription": "NNPA-LSTMACT function ending with CC=0"
|
||||
},
|
||||
{
|
||||
"Unit": "PAI-EXT",
|
||||
"EventCode": "6162",
|
||||
"EventName": "NNPA_GRUACT",
|
||||
"BriefDescription": "NNPA GRUACT function",
|
||||
"PublicDescription": "NNPA-GRUACT function ending with CC=0"
|
||||
},
|
||||
{
|
||||
"Unit": "PAI-EXT",
|
||||
"EventCode": "6163",
|
||||
"EventName": "NNPA_CONVOLUTION",
|
||||
"BriefDescription": "NNPA CONVOLUTION function",
|
||||
"PublicDescription": "NNPA-CONVOLUTION function ending with CC=0"
|
||||
},
|
||||
{
|
||||
"Unit": "PAI-EXT",
|
||||
"EventCode": "6164",
|
||||
"EventName": "NNPA_MATMUL_OP",
|
||||
"BriefDescription": "NNPA MATMUL OP function",
|
||||
"PublicDescription": "NNPA-MATMUL-OP function ending with CC=0"
|
||||
},
|
||||
{
|
||||
"Unit": "PAI-EXT",
|
||||
"EventCode": "6165",
|
||||
"EventName": "NNPA_MATMUL_OP_BCAST23",
|
||||
"BriefDescription": "NNPA MATMUL OP BCAST23 function",
|
||||
"PublicDescription": "NNPA-MATMUL-OP-BCAST23 function ending with CC=0"
|
||||
},
|
||||
{
|
||||
"Unit": "PAI-EXT",
|
||||
"EventCode": "6166",
|
||||
"EventName": "NNPA_SMALLBATCH",
|
||||
"BriefDescription": "NNPA Counter 22",
|
||||
"PublicDescription": "NNPA function with conditions as described in Principles of Operation"
|
||||
},
|
||||
{
|
||||
"Unit": "PAI-EXT",
|
||||
"EventCode": "6167",
|
||||
"EventName": "NNPA_LARGEDIM",
|
||||
"BriefDescription": "NNPA Counter 23",
|
||||
"PublicDescription": "NNPA function with conditions as described in Principles of Operation"
|
||||
},
|
||||
{
|
||||
"Unit": "PAI-EXT",
|
||||
"EventCode": "6168",
|
||||
"EventName": "NNPA_SMALLTENSOR",
|
||||
"BriefDescription": "NNPA Counter 24",
|
||||
"PublicDescription": "NNPA function with conditions as described in Principles of Operation"
|
||||
},
|
||||
{
|
||||
"Unit": "PAI-EXT",
|
||||
"EventCode": "6169",
|
||||
"EventName": "NNPA_1MFRAME",
|
||||
"BriefDescription": "NNPA Counter 25",
|
||||
"PublicDescription": "NNPA function with conditions as described in Principles of Operation"
|
||||
},
|
||||
{
|
||||
"Unit": "PAI-EXT",
|
||||
"EventCode": "6170",
|
||||
"EventName": "NNPA_2GFRAME",
|
||||
"BriefDescription": "NNPA Counter 26",
|
||||
"PublicDescription": "NNPA function with conditions as described in Principles of Operation"
|
||||
},
|
||||
{
|
||||
"Unit": "PAI-EXT",
|
||||
"EventCode": "6171",
|
||||
"EventName": "NNPA_ACCESSEXCEPT",
|
||||
"BriefDescription": "NNPA Counter 27",
|
||||
"PublicDescription": "NNPA function with conditions as described in Principles of Operation"
|
||||
},
|
||||
{
|
||||
"Unit": "PAI-EXT",
|
||||
"EventCode": "6172",
|
||||
"EventName": "NNPA_TRANSFORM",
|
||||
"BriefDescription": "NNPA-TRANSFORM function",
|
||||
"PublicDescription": "NNPA-TRANSFORM function ending with CC=0"
|
||||
},
|
||||
{
|
||||
"Unit": "PAI-EXT",
|
||||
"EventCode": "6173",
|
||||
"EventName": "NNPA_GELU",
|
||||
"BriefDescription": "NNPA-GELU function",
|
||||
"PublicDescription": "NNPA-GELU function ending with CC=0"
|
||||
},
|
||||
{
|
||||
"Unit": "PAI-EXT",
|
||||
"EventCode": "6174",
|
||||
"EventName": "NNPA_MOMENTS",
|
||||
"BriefDescription": "NNPA-MOMENTS function",
|
||||
"PublicDescription": "NNPA-MOMENTS function ending with CC=0"
|
||||
},
|
||||
{
|
||||
"Unit": "PAI-EXT",
|
||||
"EventCode": "6175",
|
||||
"EventName": "NNPA_LAYERNORM",
|
||||
"BriefDescription": "NNPA-LAYERNORM function",
|
||||
"PublicDescription": "NNPA-LAYERNORM function ending with CC=0"
|
||||
},
|
||||
{
|
||||
"Unit": "PAI-EXT",
|
||||
"EventCode": "6176",
|
||||
"EventName": "NNPA_MATMUL_OP_BCAST1",
|
||||
"BriefDescription": "NNPA-MATMUL_OP_BCAST1 function",
|
||||
"PublicDescription": "NNPA-MATMUL-OP-BCAST1 function ending with CC=0"
|
||||
},
|
||||
{
|
||||
"Unit": "PAI-EXT",
|
||||
"EventCode": "6177",
|
||||
"EventName": "NNPA_SQRT",
|
||||
"BriefDescription": "NNPA-SQRT function",
|
||||
"PublicDescription": "NNPA-SQRT function ending with CC=0"
|
||||
},
|
||||
{
|
||||
"Unit": "PAI-EXT",
|
||||
"EventCode": "6178",
|
||||
"EventName": "NNPA_INVSQRT",
|
||||
"BriefDescription": "NNPA-INVSQRT function",
|
||||
"PublicDescription": "NNPA-INVSQRT function ending with CC=0"
|
||||
},
|
||||
{
|
||||
"Unit": "PAI-EXT",
|
||||
"EventCode": "6179",
|
||||
"EventName": "NNPA_NORM",
|
||||
"BriefDescription": "NNPA-NORM function",
|
||||
"PublicDescription": "NNPA-NORM function ending with CC=0"
|
||||
},
|
||||
{
|
||||
"Unit": "PAI-EXT",
|
||||
"EventCode": "6180",
|
||||
"EventName": "NNPA_REDUCE",
|
||||
"BriefDescription": "NNPA-REDUCE function",
|
||||
"PublicDescription": "NNPA-REDUCE function ending with CC=0"
|
||||
}
|
||||
]
|
||||
72
tools/perf/pmu-events/arch/s390/cf_z17/transaction.json
Normal file
72
tools/perf/pmu-events/arch/s390/cf_z17/transaction.json
Normal file
@@ -0,0 +1,72 @@
|
||||
[
|
||||
{
|
||||
"BriefDescription": "Transaction count",
|
||||
"MetricName": "transaction",
|
||||
"MetricExpr": "TX_C_TEND + TX_NC_TEND + TX_NC_TABORT + TX_C_TABORT_SPECIAL + TX_C_TABORT_NO_SPECIAL if has_event(TX_C_TEND) else 0"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles per Instruction",
|
||||
"MetricName": "cpi",
|
||||
"MetricExpr": "CPU_CYCLES / INSTRUCTIONS if has_event(INSTRUCTIONS) else 0"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Problem State Instruction Ratio",
|
||||
"MetricName": "prbstate",
|
||||
"MetricExpr": "(PROBLEM_STATE_INSTRUCTIONS / INSTRUCTIONS) * 100 if has_event(INSTRUCTIONS) else 0"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Level One Miss per 100 Instructions",
|
||||
"MetricName": "l1mp",
|
||||
"MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * 100 if has_event(INSTRUCTIONS) else 0"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Percentage sourced from Level 2 cache",
|
||||
"MetricName": "l2p",
|
||||
"MetricExpr": "((DCW_REQ + DCW_REQ_IV + ICW_REQ + ICW_REQ_IV) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(DCW_REQ) else 0"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Percentage sourced from Level 3 on same chip cache",
|
||||
"MetricName": "l3p",
|
||||
"MetricExpr": "((DCW_REQ_CHIP_HIT + DCW_ON_CHIP + DCW_ON_CHIP_IV + DCW_ON_CHIP_CHIP_HIT + ICW_REQ_CHIP_HIT + ICW_ON_CHIP + ICW_ON_CHIP_IV + ICW_ON_CHIP_CHIP_HIT) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(DCW_REQ_CHIP_HIT) else 0"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Percentage sourced from Level 4 Local cache on same drawer",
|
||||
"MetricName": "l4lp",
|
||||
"MetricExpr": "((DCW_REQ_DRAWER_HIT + DCW_ON_CHIP_DRAWER_HIT + DCW_ON_MODULE + DCW_ON_DRAWER + IDCW_ON_MODULE_IV + IDCW_ON_MODULE_CHIP_HIT + IDCW_ON_MODULE_DRAWER_HIT + IDCW_ON_DRAWER_IV + IDCW_ON_DRAWER_CHIP_HIT + IDCW_ON_DRAWER_DRAWER_HIT + ICW_REQ_DRAWER_HIT + ICW_ON_CHIP_DRAWER_HIT + ICW_ON_MODULE + ICW_ON_DRAWER) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(DCW_REQ_DRAWER_HIT) else 0"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Percentage sourced from Level 4 Remote cache on different book",
|
||||
"MetricName": "l4rp",
|
||||
"MetricExpr": "((DCW_OFF_DRAWER + IDCW_OFF_DRAWER_IV + IDCW_OFF_DRAWER_CHIP_HIT + IDCW_OFF_DRAWER_DRAWER_HIT + ICW_OFF_DRAWER) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(DCW_OFF_DRAWER) else 0"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Percentage sourced from memory",
|
||||
"MetricName": "memp",
|
||||
"MetricExpr": "((DCW_ON_CHIP_MEMORY + DCW_ON_MODULE_MEMORY + DCW_ON_DRAWER_MEMORY + DCW_OFF_DRAWER_MEMORY) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(DCW_ON_CHIP_MEMORY) else 0"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Cycles per Instructions from Finite cache/memory",
|
||||
"MetricName": "finite_cpi",
|
||||
"MetricExpr": "L1C_TLB2_MISSES / INSTRUCTIONS if has_event(L1C_TLB2_MISSES) else 0"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Estimated Instruction Complexity CPI infinite Level 1",
|
||||
"MetricName": "est_cpi",
|
||||
"MetricExpr": "(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB2_MISSES / INSTRUCTIONS) if has_event(INSTRUCTIONS) else 0"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Estimated Sourcing Cycles per Level 1 Miss",
|
||||
"MetricName": "scpl1m",
|
||||
"MetricExpr": "L1C_TLB2_MISSES / (L1I_DIR_WRITES + L1D_DIR_WRITES) if has_event(L1C_TLB2_MISSES) else 0"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Estimated TLB CPU percentage of Total CPU",
|
||||
"MetricName": "tlb_percent",
|
||||
"MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / CPU_CYCLES) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) * 100 if has_event(CPU_CYCLES) else 0"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "Estimated Cycles per TLB Miss",
|
||||
"MetricName": "tlb_miss",
|
||||
"MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / (DTLB2_WRITES + ITLB2_WRITES)) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) if has_event(DTLB2_MISSES) else 0"
|
||||
}
|
||||
]
|
||||
@@ -6,3 +6,4 @@ Family-model,Version,Filename,EventType
|
||||
^IBM.390[67].*[13]\.[1-5].[[:xdigit:]]+$,3,cf_z14,core
|
||||
^IBM.856[12].*3\.6.[[:xdigit:]]+$,3,cf_z15,core
|
||||
^IBM.393[12].*$,3,cf_z16,core
|
||||
^IBM.917[56].*$,3,cf_z17,core
|
||||
|
||||
|
Reference in New Issue
Block a user