mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-05-16 00:51:51 -04:00
Merge tag 'soc-late-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull more SoC updates from Arnd Bergmann: "These are the contents that arrived during the easter vacation and didn't make it into the last 7.0 bugfixes or the first set of branches for the merge window. Aside from a reset controller bugfix and an update to the MAINTAINERS entry, this is all devicetree changes. The Marvell devicetree updates contain the usual minor updates and bugfixes, along with a two larger but trivial patches to drop unused dtsi files, the single broadcom fix addresses a build time warning introduced during the merge window. The freescale, amlogic, and apple changes missed the last fixes branch for 7.0" * tag 'soc-late-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (38 commits) arm64: dts: meson-gxl-p230: fix ethernet PHY interrupt number arm64: dts: amlogic: meson-axg: Add missing cache information to cpu0 arm64: dts: amlogic: t7: khadas-vim4: fix board model name arm64: dts: amlogic: Fix GIC register ranges for Amlogic T7 arm64: dts: amlogic: t7: khadas-vim4: fix memory layout for 8GB RAM arm64: dts: amlogic: s6: Drop CPU masks from GICv3 PPI interrupts Documentation/process: maintainer-soc: Document purpose of defconfigs Documentation/process: maintainer-soc: Trim from trivial ask-DT ARM: dts: bcm4709: fix bus range assignment arm64: dts: apple: Fix spelling error dt-bindings: Update Sasha Finkelstein's email address mailmap: Update Sasha Finkelstein's email address arm64: dts: marvell: armada-37xx: swap PHYs' order in USB3 controller node arm64: dts: marvell: armada-37xx: use 'usb2-phy' in USB3 controller's phy-names arm64: dts: imx8mm-tqma8mqml: Correct PAD settings for PMIC_nINT arm64: dts: imx8mn-tqma8mqnl: Correct PAD settings for PMIC_nINT arm64: dts: imx8mm-emtop-som: Correct PAD settings for PMIC_nINT reset: amlogic: t7: Fix null reset ops arm64: dts: imx8mp-data-modul-edm-sbc: Correct PAD settings for PMIC_nINT arm64: dts: imx8mp-dhcom-som: Correct PAD settings for PMIC_nINT ...
This commit is contained in:
Linus Torvalds
1
.mailmap
1
.mailmap
@@ -743,6 +743,7 @@ Sarangdhar Joshi <spjoshi@codeaurora.org>
|
||||
Saravana Kannan <saravanak@kernel.org> <skannan@codeaurora.org>
|
||||
Saravana Kannan <saravanak@kernel.org> <saravanak@google.com>
|
||||
Sascha Hauer <s.hauer@pengutronix.de>
|
||||
Sasha Finkelstein <k@chaosmail.tech> <fnkl.kernel@gmail.com>
|
||||
Sahitya Tummala <quic_stummala@quicinc.com> <stummala@codeaurora.org>
|
||||
Sathishkumar Muruganandam <quic_murugana@quicinc.com> <murugana@codeaurora.org>
|
||||
Satya Priya <quic_skakitap@quicinc.com> <quic_c_skakit@quicinc.com> <skakit@codeaurora.org>
|
||||
|
||||
@@ -21,6 +21,17 @@ properties:
|
||||
- const: marvell,armada-ap806-dual
|
||||
- const: marvell,armada-ap806
|
||||
|
||||
- description:
|
||||
Falcon (DB-98CX85x0) Development board COM Express Carrier plus
|
||||
Armada 7020 SoC COM Express CPU module
|
||||
items:
|
||||
- const: marvell,armada7020-falcon-carrier
|
||||
- const: marvell,db-falcon-carrier
|
||||
- const: marvell,armada7020-cpu-module
|
||||
- const: marvell,armada7020
|
||||
- const: marvell,armada-ap806-dual
|
||||
- const: marvell,armada-ap806
|
||||
|
||||
- description: Armada 7040 SoC
|
||||
items:
|
||||
- enum:
|
||||
|
||||
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: Apple pre-DCP display controller MIPI interface
|
||||
|
||||
maintainers:
|
||||
- Sasha Finkelstein <fnkl.kernel@gmail.com>
|
||||
- Sasha Finkelstein <k@chaosmail.tech>
|
||||
|
||||
description:
|
||||
The MIPI controller part of the pre-DCP Apple display controller
|
||||
|
||||
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: Apple pre-DCP display controller
|
||||
|
||||
maintainers:
|
||||
- Sasha Finkelstein <fnkl.kernel@gmail.com>
|
||||
- Sasha Finkelstein <k@chaosmail.tech>
|
||||
|
||||
description:
|
||||
A secondary display controller used to drive the "touchbar" on
|
||||
|
||||
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: Apple "Summit" display panel
|
||||
|
||||
maintainers:
|
||||
- Sasha Finkelstein <fnkl.kernel@gmail.com>
|
||||
- Sasha Finkelstein <k@chaosmail.tech>
|
||||
|
||||
description:
|
||||
An OLED panel used as a touchbar on certain Apple laptops.
|
||||
|
||||
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: Apple SoC GPU
|
||||
|
||||
maintainers:
|
||||
- Sasha Finkelstein <fnkl.kernel@gmail.com>
|
||||
- Sasha Finkelstein <k@chaosmail.tech>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: Apple touchscreens attached using the Z2 protocol
|
||||
|
||||
maintainers:
|
||||
- Sasha Finkelstein <fnkl.kernel@gmail.com>
|
||||
- Sasha Finkelstein <k@chaosmail.tech>
|
||||
|
||||
description: A series of touschscreen controllers used in Apple products
|
||||
|
||||
|
||||
@@ -9,7 +9,7 @@ title: Apple SPMI NVMEM
|
||||
description: Exports a series of SPMI registers as NVMEM cells
|
||||
|
||||
maintainers:
|
||||
- Sasha Finkelstein <fnkl.kernel@gmail.com>
|
||||
- Sasha Finkelstein <k@chaosmail.tech>
|
||||
|
||||
allOf:
|
||||
- $ref: nvmem.yaml#
|
||||
|
||||
@@ -8,7 +8,7 @@ title: Apple FPWM controller
|
||||
|
||||
maintainers:
|
||||
- asahi@lists.linux.dev
|
||||
- Sasha Finkelstein <fnkl.kernel@gmail.com>
|
||||
- Sasha Finkelstein <k@chaosmail.tech>
|
||||
|
||||
description: PWM controller used for keyboard backlight on ARM Macs
|
||||
|
||||
|
||||
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: Apple SPMI controller
|
||||
|
||||
maintainers:
|
||||
- Sasha Finkelstein <fnkl.kernel@gmail.com>
|
||||
- Sasha Finkelstein <k@chaosmail.tech>
|
||||
|
||||
description: A SPMI controller present on most Apple SoCs
|
||||
|
||||
|
||||
@@ -169,8 +169,6 @@ more information on the validation of devicetrees.
|
||||
For new platforms, or additions to existing ones, ``make dtbs_check`` should not
|
||||
add any new warnings. For RISC-V and Samsung SoC, ``make dtbs_check W=1`` is
|
||||
required to not add any new warnings.
|
||||
If in any doubt about a devicetree change, reach out to the devicetree
|
||||
maintainers.
|
||||
|
||||
Branches and Pull Requests
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
@@ -209,3 +207,13 @@ The subject line of a pull request should begin with "[GIT PULL]" and made using
|
||||
a signed tag, rather than a branch. This tag should contain a short description
|
||||
summarising the changes in the pull request. For more detail on sending pull
|
||||
requests, please see Documentation/maintainer/pull-requests.rst.
|
||||
|
||||
Defconfigs purpose
|
||||
~~~~~~~~~~~~~~~~~~
|
||||
|
||||
Defconfigs are primarily used by the kernel developers, because distros have
|
||||
their own configs. A change adding new CONFIG options to a defconfig should
|
||||
explain why the kernel developers in general would want such option, e.g. by
|
||||
providing a name of an upstream-supported machine/board using that new option.
|
||||
This implies that enabling options in defconfig for non-upstream machines shall
|
||||
not be accepted.
|
||||
|
||||
@@ -8706,7 +8706,7 @@ F: include/linux/host1x.h
|
||||
F: include/uapi/drm/tegra_drm.h
|
||||
|
||||
DRM DRIVERS FOR PRE-DCP APPLE DISPLAY OUTPUT
|
||||
M: Sasha Finkelstein <fnkl.kernel@gmail.com>
|
||||
M: Sasha Finkelstein <k@chaosmail.tech>
|
||||
R: Janne Grunau <j@jannau.net>
|
||||
L: dri-devel@lists.freedesktop.org
|
||||
L: asahi@lists.linux.dev
|
||||
|
||||
@@ -139,7 +139,6 @@ &pcie_bridge1 {
|
||||
pcie@0,0 {
|
||||
device_type = "pci";
|
||||
reg = <0x0000 0 0 0 0>;
|
||||
bus-range = <0x01 0xff>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
@@ -1,148 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Device Tree Include file for Marvell Armada 380 SoC.
|
||||
*
|
||||
* Copyright (C) 2014 Marvell
|
||||
*
|
||||
* Lior Amsalem <alior@marvell.com>
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*/
|
||||
|
||||
#include "armada-38x.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 380 family SoC";
|
||||
compatible = "marvell,armada380";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enable-method = "marvell,armada-380-smp";
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
internal-regs {
|
||||
pinctrl@18000 {
|
||||
compatible = "marvell,mv88f6810-pinctrl";
|
||||
};
|
||||
};
|
||||
|
||||
pcie {
|
||||
compatible = "marvell,armada-370-pcie";
|
||||
status = "disabled";
|
||||
device_type = "pci";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
msi-parent = <&mpic>;
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
ranges =
|
||||
<0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
|
||||
0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
|
||||
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
|
||||
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
|
||||
0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
|
||||
0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
|
||||
0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
|
||||
0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
|
||||
0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
|
||||
0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */>;
|
||||
|
||||
/* x1 port */
|
||||
pcie@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
interrupt-names = "intx";
|
||||
interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x1 0 1 0>;
|
||||
bus-range = <0x00 0xff>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie1_intc 0>,
|
||||
<0 0 0 2 &pcie1_intc 1>,
|
||||
<0 0 0 3 &pcie1_intc 2>,
|
||||
<0 0 0 4 &pcie1_intc 3>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 8>;
|
||||
status = "disabled";
|
||||
|
||||
pcie1_intc: interrupt-controller {
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
/* x1 port */
|
||||
pcie@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82001000 0 0x40000 0 0x2000>;
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
interrupt-names = "intx";
|
||||
interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x2 0 1 0>;
|
||||
bus-range = <0x00 0xff>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie2_intc 0>,
|
||||
<0 0 0 2 &pcie2_intc 1>,
|
||||
<0 0 0 3 &pcie2_intc 2>,
|
||||
<0 0 0 4 &pcie2_intc 3>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 5>;
|
||||
status = "disabled";
|
||||
|
||||
pcie2_intc: interrupt-controller {
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
/* x1 port */
|
||||
pcie@3,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82001800 0 0x44000 0 0x2000>;
|
||||
reg = <0x1800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
interrupt-names = "intx";
|
||||
interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x3 0 1 0>;
|
||||
bus-range = <0x00 0xff>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie3_intc 0>,
|
||||
<0 0 0 2 &pcie3_intc 1>,
|
||||
<0 0 0 3 &pcie3_intc 2>,
|
||||
<0 0 0 4 &pcie3_intc 3>;
|
||||
marvell,pcie-port = <2>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 6>;
|
||||
status = "disabled";
|
||||
|
||||
pcie3_intc: interrupt-controller {
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -53,10 +53,10 @@ pwrc: power-controller {
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
psci {
|
||||
@@ -84,7 +84,7 @@ gic: interrupt-controller@ff200000 {
|
||||
interrupt-controller;
|
||||
reg = <0x0 0xff200000 0 0x10000>,
|
||||
<0x0 0xff240000 0 0x80000>;
|
||||
interrupts = <GIC_PPI 9 0xf04>;
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
apb: bus@fe000000 {
|
||||
|
||||
@@ -8,7 +8,7 @@
|
||||
#include "amlogic-t7.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Khadas vim4";
|
||||
model = "Khadas VIM4";
|
||||
compatible = "khadas,vim4", "amlogic,a311d2", "amlogic,t7";
|
||||
|
||||
aliases {
|
||||
@@ -17,7 +17,9 @@ aliases {
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x2 0x0>; /* 8 GB */
|
||||
reg = <0x0 0x0 0x0 0xE0000000
|
||||
0x1 0x0 0x0 0xE0000000
|
||||
0x2 0x0 0x0 0x40000000>; /* 8 GB */
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
|
||||
@@ -213,7 +213,9 @@ gic: interrupt-controller@fff01000 {
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0x0 0xfff01000 0 0x1000>,
|
||||
<0x0 0xfff02000 0 0x0100>;
|
||||
<0x0 0xfff02000 0 0x2000>,
|
||||
<0x0 0xfff04000 0 0x2000>,
|
||||
<0x0 0xfff06000 0 0x2000>;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
};
|
||||
|
||||
|
||||
@@ -72,6 +72,12 @@ cpu0: cpu@0 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0 0x0>;
|
||||
enable-method = "psci";
|
||||
d-cache-line-size = <32>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-sets = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
i-cache-size = <0x8000>;
|
||||
i-cache-sets = <32>;
|
||||
next-level-cache = <&l2>;
|
||||
clocks = <&scpi_dvfs 0>;
|
||||
dynamic-power-coefficient = <140>;
|
||||
|
||||
@@ -84,7 +84,8 @@ external_phy: ethernet-phy@0 {
|
||||
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
|
||||
|
||||
interrupt-parent = <&gpio_intc>;
|
||||
interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
|
||||
/* MAC_INTR on GPIOZ_15 */
|
||||
interrupts = <25 IRQ_TYPE_LEVEL_LOW>;
|
||||
eee-broken-1000t;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
//
|
||||
// Devicetree include for common spi-nor nvram flash.
|
||||
//
|
||||
// Apple uses a consistent configiguration for the nvram on all known M1* and
|
||||
// Apple uses a consistent configuration for the nvram on all known M1* and
|
||||
// M2* devices.
|
||||
//
|
||||
// Copyright The Asahi Linux Contributors
|
||||
|
||||
@@ -60,7 +60,7 @@ pmic@25 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pmic>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <3 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
regulators {
|
||||
buck1: BUCK1 {
|
||||
@@ -194,7 +194,7 @@ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
|
||||
|
||||
pinctrl_pmic: emtop-pmic-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
|
||||
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
|
||||
>;
|
||||
};
|
||||
|
||||
|
||||
@@ -292,7 +292,7 @@ pinctrl_i2c1_gpio: i2c1gpiogrp {
|
||||
};
|
||||
|
||||
pinctrl_pmic: pmicgrp {
|
||||
fsl,pins = <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x94>;
|
||||
fsl,pins = <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x1d4>;
|
||||
};
|
||||
|
||||
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
|
||||
|
||||
@@ -283,7 +283,7 @@ pinctrl_i2c1_gpio: i2c1gpiogrp {
|
||||
};
|
||||
|
||||
pinctrl_pmic: pmicgrp {
|
||||
fsl,pins = <MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x84>;
|
||||
fsl,pins = <MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x1c4>;
|
||||
};
|
||||
|
||||
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
|
||||
|
||||
@@ -903,7 +903,7 @@ MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x41
|
||||
|
||||
pinctrl_pmic: aristainetos3-pmic-grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
|
||||
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0
|
||||
>;
|
||||
};
|
||||
|
||||
|
||||
@@ -1001,7 +1001,7 @@ MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_PDM_BIT_STREAM00 0x0
|
||||
pinctrl_pmic: pmic-grp {
|
||||
fsl,pins = <
|
||||
/* PMIC_nINT */
|
||||
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x40000090
|
||||
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0
|
||||
>;
|
||||
};
|
||||
|
||||
|
||||
@@ -440,7 +440,7 @@ MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c3
|
||||
|
||||
pinctrl_pmic: pmicirqgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
|
||||
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0
|
||||
>;
|
||||
};
|
||||
|
||||
|
||||
@@ -499,7 +499,7 @@ MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x140
|
||||
|
||||
pinctrl_pmic: pmicgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
|
||||
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0
|
||||
>;
|
||||
};
|
||||
|
||||
|
||||
@@ -241,7 +241,7 @@ MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3
|
||||
|
||||
pinctrl_pmic: pmicgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
|
||||
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0
|
||||
>;
|
||||
};
|
||||
|
||||
|
||||
@@ -989,7 +989,7 @@ MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x22
|
||||
pinctrl_pmic: dhcom-pmic-grp {
|
||||
fsl,pins = <
|
||||
/* PMIC_nINT */
|
||||
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x40000090
|
||||
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0
|
||||
>;
|
||||
};
|
||||
|
||||
|
||||
@@ -563,7 +563,7 @@ MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x41 /* PCIE RST */
|
||||
|
||||
pinctrl_pmic: pmicirqgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
|
||||
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0
|
||||
>;
|
||||
};
|
||||
|
||||
|
||||
@@ -132,7 +132,7 @@ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
|
||||
|
||||
pinctrl_pmic: pmicgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x41
|
||||
MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x1c0
|
||||
>;
|
||||
};
|
||||
|
||||
|
||||
@@ -356,7 +356,7 @@ MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3
|
||||
|
||||
pinctrl_pmic: pmicgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
|
||||
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0
|
||||
>;
|
||||
};
|
||||
|
||||
|
||||
@@ -296,7 +296,7 @@ MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3
|
||||
|
||||
pinctrl_pmic: pmicirqgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x41
|
||||
MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x1c0
|
||||
>;
|
||||
};
|
||||
|
||||
|
||||
@@ -174,7 +174,7 @@ pmic: pmic@25 {
|
||||
pinctrl-0 = <&pmic_pins>;
|
||||
pinctrl-names = "default";
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <3 GPIO_ACTIVE_LOW>;
|
||||
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
|
||||
nxp,i2c-lt-enable;
|
||||
|
||||
regulators {
|
||||
@@ -417,7 +417,7 @@ MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x160
|
||||
|
||||
pmic_pins: pinctrl-pmic-grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
|
||||
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0
|
||||
>;
|
||||
};
|
||||
|
||||
|
||||
@@ -275,7 +275,7 @@ pmic@25 {
|
||||
reg = <0x25>;
|
||||
pinctrl-0 = <&pinctrl_pmic>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <3 GPIO_ACTIVE_LOW>;
|
||||
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
/*
|
||||
* i.MX 8M Plus Data Sheet for Consumer Products
|
||||
@@ -739,7 +739,7 @@ MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x40 /* NFC_INT */
|
||||
|
||||
pinctrl_pmic: pmic-grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x40 /* #PMIC_INT */
|
||||
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 /* #PMIC_INT */
|
||||
>;
|
||||
};
|
||||
|
||||
|
||||
@@ -82,7 +82,6 @@ &sdhci0 {
|
||||
mmc-ddr-1_8v;
|
||||
mmc-hs400-1_8v;
|
||||
sd-uhs-sdr104;
|
||||
marvell,xenon-emmc;
|
||||
marvell,xenon-tun-count = <9>;
|
||||
marvell,pad-type = "fixed-1-8v";
|
||||
vqmmc-supply = <&vsdc_reg>;
|
||||
|
||||
@@ -78,7 +78,6 @@ &sdhci0 {
|
||||
bus-width = <8>;
|
||||
mmc-ddr-1_8v;
|
||||
mmc-hs400-1_8v;
|
||||
marvell,xenon-emmc;
|
||||
marvell,xenon-tun-count = <9>;
|
||||
marvell,pad-type = "fixed-1-8v";
|
||||
|
||||
|
||||
@@ -15,6 +15,11 @@
|
||||
#include "armada-372x.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
ethernet0 = ð0;
|
||||
ethernet1 = ð1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
@@ -156,7 +161,7 @@ ð1 {
|
||||
&usb3 {
|
||||
status = "okay";
|
||||
phys = <&usb2_utmi_otg_phy>;
|
||||
phy-names = "usb2-utmi-otg-phy";
|
||||
phy-names = "usb2-phy";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
|
||||
@@ -369,11 +369,10 @@ usb3: usb@58000 {
|
||||
compatible = "marvell,armada3700-xhci",
|
||||
"generic-xhci";
|
||||
reg = <0x58000 0x4000>;
|
||||
marvell,usb-misc-reg = <&usb32_syscon>;
|
||||
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&sb_periph_clk 12>;
|
||||
phys = <&comphy0 0>, <&usb2_utmi_otg_phy>;
|
||||
phy-names = "usb3-phy", "usb2-utmi-otg-phy";
|
||||
phys = <&usb2_utmi_otg_phy>, <&comphy0 0>;
|
||||
phy-names = "usb2-phy", "usb3-phy";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@@ -393,10 +392,9 @@ usb32_syscon: system-controller@5d800 {
|
||||
usb2: usb@5e000 {
|
||||
compatible = "marvell,armada-3700-ehci";
|
||||
reg = <0x5e000 0x1000>;
|
||||
marvell,usb-misc-reg = <&usb2_syscon>;
|
||||
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
phys = <&usb2_utmi_host_phy>;
|
||||
phy-names = "usb2-utmi-host-phy";
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@@ -534,7 +532,6 @@ firmware {
|
||||
armada-3700-rwtm {
|
||||
compatible = "marvell,armada-3700-rwtm-firmware";
|
||||
mboxes = <&rwtm 0>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -70,7 +70,7 @@ &cp0_eth0 {
|
||||
|
||||
&cp0_eth1 {
|
||||
status = "okay";
|
||||
phy = <&phy0>;
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
|
||||
@@ -1,20 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2016 Marvell Technology Group Ltd.
|
||||
*
|
||||
* Device Tree file for the Armada 8020 SoC, made of an AP806 Dual and
|
||||
* two CP110.
|
||||
*/
|
||||
|
||||
#include "armada-ap806-dual.dtsi"
|
||||
#include "armada-80x0.dtsi"
|
||||
|
||||
/* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock
|
||||
* in CP master is not connected (by package) to the oscillator. So
|
||||
* disable it. However, the RTC clock in CP slave is connected to the
|
||||
* oscillator so this one is let enabled.
|
||||
*/
|
||||
|
||||
&cp0_rtc {
|
||||
status = "disabled";
|
||||
};
|
||||
@@ -1,96 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2023 Marvell International Ltd.
|
||||
*
|
||||
* Device tree for the CN9130-DB Com Express CPU module board.
|
||||
*/
|
||||
|
||||
#include "cn9130-db.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada CN9130-DB COM EXPRESS type 7 CPU module board";
|
||||
compatible = "marvell,cn9130-cpu-module", "marvell,cn9130",
|
||||
"marvell,armada-ap807-quad", "marvell,armada-ap807";
|
||||
|
||||
};
|
||||
|
||||
&ap0_reg_sd_vccq {
|
||||
regulator-max-microvolt = <1800000>;
|
||||
states = <1800000 0x1 1800000 0x0>;
|
||||
/delete-property/ gpios;
|
||||
};
|
||||
|
||||
&cp0_reg_usb3_vbus0 {
|
||||
/delete-property/ gpio;
|
||||
};
|
||||
|
||||
&cp0_reg_usb3_vbus1 {
|
||||
/delete-property/ gpio;
|
||||
};
|
||||
|
||||
&cp0_reg_sd_vcc {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cp0_reg_sd_vccq {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cp0_sdhci0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cp0_eth0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cp0_eth1 {
|
||||
status = "okay";
|
||||
phy = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
&cp0_eth2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cp0_mdio {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&cp0_ge_mdio_pins>;
|
||||
phy0: ethernet-phy@0 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_syscon0 {
|
||||
cp0_pinctrl: pinctrl {
|
||||
compatible = "marvell,cp115-standalone-pinctrl";
|
||||
|
||||
cp0_ge_mdio_pins: ge-mdio-pins {
|
||||
marvell,pins = "mpp40", "mpp41";
|
||||
marvell,function = "ge";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_sdhci0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cp0_spi1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_usb3_0 {
|
||||
status = "okay";
|
||||
usb-phy = <&cp0_usb3_0_phy0>;
|
||||
phy-names = "usb";
|
||||
/delete-property/ phys;
|
||||
};
|
||||
|
||||
&cp0_usb3_1 {
|
||||
status = "okay";
|
||||
usb-phy = <&cp0_usb3_0_phy1>;
|
||||
phy-names = "usb";
|
||||
/delete-property/ phys;
|
||||
};
|
||||
@@ -42,6 +42,7 @@ static const struct meson_reset_param meson_s4_param = {
|
||||
};
|
||||
|
||||
static const struct meson_reset_param t7_param = {
|
||||
.reset_ops = &meson_reset_ops,
|
||||
.reset_num = 224,
|
||||
.reset_offset = 0x0,
|
||||
.level_offset = 0x40,
|
||||
|
||||
Reference in New Issue
Block a user