mirrors/linux
2
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2026-05-07 19:49:33 -04:00
Code Issues Packages Projects Releases Wiki Activity

arm64: dts: rockchip: split rk3568 device tree

Browse Source 
In preparation for the rk3566 inclusion, split apart the rk3568 specific
nodes into a separate device tree.
This allows us to create the rk3566 device tree without deleting nodes.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Link: https://lore.kernel.org/r/20210710151034.32857-3-pgwipeout@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Peter Geis
2021-07-10 11:10:32 -04:00
committed by Heiko Stuebner
parent 4e50d2173b
commit 5067f459e5
2 changed files with 48 additions and 36 deletions
Download Patch File Download Diff File Expand all files Collapse all files

48
arch/arm64/boot/dts/rockchip/rk3568.dtsi Normal file
View File

@@ -0,0 +1,48 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
*/
#include "rk356x.dtsi"
/ {
compatible = "rockchip,rk3568";
qos_pcie3x1: qos@fe190080 {
compatible = "rockchip,rk3568-qos", "syscon";
reg = <0x0 0xfe190080 0x0 0x20>;
};
qos_pcie3x2: qos@fe190100 {
compatible = "rockchip,rk3568-qos", "syscon";
reg = <0x0 0xfe190100 0x0 0x20>;
};
qos_sata0: qos@fe190200 {
compatible = "rockchip,rk3568-qos", "syscon";
reg = <0x0 0xfe190200 0x0 0x20>;
};
};
&cpu0_opp_table {
opp-1992000000 {
opp-hz = /bits/ 64 <1992000000>;
opp-microvolt = <1150000 1150000 1150000>;
};
};
&power {
power-domain@RK3568_PD_PIPE {
reg = <RK3568_PD_PIPE>;
clocks = <&cru PCLK_PIPE>;
pm_qos = <&qos_pcie2x1>,
<&qos_pcie3x1>,
<&qos_pcie3x2>,
<&qos_sata0>,
<&qos_sata1>,
<&qos_sata2>,
<&qos_usb3_0>,
<&qos_usb3_1>;
#power-domain-cells = <0>;
};
};

36
arch/arm64/boot/dts/rockchip/rk356x.dtsi
View File

@@ -13,8 +13,6 @@
#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "rockchip,rk3568";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
@@ -121,11 +119,6 @@ opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <1050000 1050000 1150000>;
};
opp-1992000000 {
opp-hz = /bits/ 64 <1992000000>;
opp-microvolt = <1150000 1150000 1150000>;
};
};
firmware {
@@ -334,20 +327,6 @@ power-domain@RK3568_PD_RKVENC {
<&qos_rkvenc_wr_m0>;
#power-domain-cells = <0>;
};
power-domain@RK3568_PD_PIPE {
reg = <RK3568_PD_PIPE>;
clocks = <&cru PCLK_PIPE>;
pm_qos = <&qos_pcie2x1>,
<&qos_pcie3x1>,
<&qos_pcie3x2>,
<&qos_sata0>,
<&qos_sata1>,
<&qos_sata2>,
<&qos_usb3_0>,
<&qos_usb3_1>;
#power-domain-cells = <0>;
};
};
};
@@ -445,21 +424,6 @@ qos_pcie2x1: qos@fe190000 {
reg = <0x0 0xfe190000 0x0 0x20>;
};
qos_pcie3x1: qos@fe190080 {
compatible = "rockchip,rk3568-qos", "syscon";
reg = <0x0 0xfe190080 0x0 0x20>;
};
qos_pcie3x2: qos@fe190100 {
compatible = "rockchip,rk3568-qos", "syscon";
reg = <0x0 0xfe190100 0x0 0x20>;
};
qos_sata0: qos@fe190200 {
compatible = "rockchip,rk3568-qos", "syscon";
reg = <0x0 0xfe190200 0x0 0x20>;
};
qos_sata1: qos@fe190280 {
compatible = "rockchip,rk3568-qos", "syscon";
reg = <0x0 0xfe190280 0x0 0x20>;