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cxl: Add helper to detect top of CXL device topology
Add a helper to replace the open code detection of CXL device hierarchy root, or the host bridge. The helper will be used for delayed downstream port (dport) creation. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Li Ming <ming.li@zohomail.com> Reviewed-by: Dan Williams <dan.j.williams@intel.com> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Reviewed-by: Robert Richter <rrichter@amd.com> Tested-by: Robert Richter <rrichter@amd.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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@@ -33,6 +33,15 @@
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static DEFINE_IDA(cxl_port_ida);
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static DEFINE_XARRAY(cxl_root_buses);
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/*
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* The terminal device in PCI is NULL and @platform_bus
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* for platform devices (for cxl_test)
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*/
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static bool is_cxl_host_bridge(struct device *dev)
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{
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return (!dev || dev == &platform_bus);
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}
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int cxl_num_decoders_committed(struct cxl_port *port)
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{
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lockdep_assert_held(&cxl_rwsem.region);
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@@ -1541,7 +1550,7 @@ static int add_port_attach_ep(struct cxl_memdev *cxlmd,
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resource_size_t component_reg_phys;
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int rc;
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if (!dparent) {
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if (is_cxl_host_bridge(dparent)) {
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/*
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* The iteration reached the topology root without finding the
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* CXL-root 'cxl_port' on a previous iteration, fail for now to
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@@ -1629,11 +1638,7 @@ int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd)
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struct device *uport_dev;
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struct cxl_dport *dport;
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/*
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* The terminal "grandparent" in PCI is NULL and @platform_bus
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* for platform devices
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*/
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if (!dport_dev || dport_dev == &platform_bus)
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if (is_cxl_host_bridge(dport_dev))
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return 0;
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uport_dev = dport_dev->parent;
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