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tty: serial: samsung: prepare for different IO types
GS101's Connectivity Peripheral blocks (peric0/1 blocks) which include the I3C and USI (I2C, SPI, UART) only allow 32-bit register accesses. If using 8-bit register accesses, a SError Interrupt is raised causing the system unusable. Instead of specifying the reg-io-width = 4 everywhere, for each node, the requirement should be deduced from the compatible. Prepare the samsung tty driver to allow IO types different than UPIO_MEM. ``struct uart_port::iotype`` is an unsigned char where all its 8 bits are exposed to uapi. We can't make NULL checks on it to verify if it's set, thus always set it from the driver's data. Use u8 for the ``iotype`` member of ``struct s3c24xx_uart_info`` to emphasize that the iotype is an 8 bit mask. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20240119104526.1221243-4-tudor.ambarus@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
committed by
Greg Kroah-Hartman
parent
1d3f02abd5
commit
4f6f9a3f8f
@@ -84,6 +84,7 @@ struct s3c24xx_uart_info {
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unsigned long clksel_mask;
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unsigned long clksel_shift;
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unsigned long ucon_mask;
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u8 iotype;
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/* uart port features */
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@@ -1741,7 +1742,6 @@ static void s3c24xx_serial_init_port_default(int index) {
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spin_lock_init(&port->lock);
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port->iotype = UPIO_MEM;
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port->uartclk = 0;
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port->fifosize = 16;
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port->flags = UPF_BOOT_AUTOCONF;
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@@ -1988,6 +1988,8 @@ static int s3c24xx_serial_probe(struct platform_device *pdev)
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break;
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}
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ourport->port.iotype = ourport->info->iotype;
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if (np) {
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of_property_read_u32(np,
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"samsung,uart-fifosize", &ourport->port.fifosize);
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@@ -2398,6 +2400,7 @@ static const struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
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.name = "Samsung S3C6400 UART",
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.type = TYPE_S3C6400,
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.port_type = PORT_S3C6400,
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.iotype = UPIO_MEM,
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.fifosize = 64,
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.has_divslot = 1,
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.rx_fifomask = S3C2440_UFSTAT_RXMASK,
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@@ -2427,6 +2430,7 @@ static const struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
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.name = "Samsung S5PV210 UART",
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.type = TYPE_S3C6400,
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.port_type = PORT_S3C6400,
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.iotype = UPIO_MEM,
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.has_divslot = 1,
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.rx_fifomask = S5PV210_UFSTAT_RXMASK,
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.rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
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@@ -2456,6 +2460,7 @@ static const struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
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.name = "Samsung Exynos UART", \
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.type = TYPE_S3C6400, \
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.port_type = PORT_S3C6400, \
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.iotype = UPIO_MEM, \
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.has_divslot = 1, \
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.rx_fifomask = S5PV210_UFSTAT_RXMASK, \
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.rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \
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@@ -2516,6 +2521,7 @@ static const struct s3c24xx_serial_drv_data s5l_serial_drv_data = {
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.name = "Apple S5L UART",
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.type = TYPE_APPLE_S5L,
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.port_type = PORT_8250,
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.iotype = UPIO_MEM,
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.fifosize = 16,
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.rx_fifomask = S3C2410_UFSTAT_RXMASK,
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.rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
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@@ -2545,6 +2551,7 @@ static const struct s3c24xx_serial_drv_data artpec8_serial_drv_data = {
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.name = "Axis ARTPEC-8 UART",
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.type = TYPE_S3C6400,
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.port_type = PORT_S3C6400,
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.iotype = UPIO_MEM,
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.fifosize = 64,
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.has_divslot = 1,
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.rx_fifomask = S5PV210_UFSTAT_RXMASK,
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