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ARM: dts: imx35: Align pin config nodes with bindings

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Bindings expect pin configuration nodes in pinctrl to match certain
naming and not be part of another fake node:

pinctrl@30330000: '...' does not match any of the regexes: 'grp$', 'pinctrl-[0-9]+'

Drop the wrapping node and adjust the names to have "grp" prefix.
Diff looks big but this should have no functional impact, use e.g.
git show -w to view the diff.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Marek Vasut
2024-10-17 23:11:19 +02:00
committed by Shawn Guo
parent 54736ab4d9
commit 4f3a5cbc79
4 changed files with 91 additions and 97 deletions
Download Patch File Download Diff File Expand all files Collapse all files

62
arch/arm/boot/dts/nxp/imx/imx35-eukrea-cpuimx35.dtsi
View File

@@ -44,40 +44,38 @@ tsc2007: tsc2007@48 {
};
&iomuxc {
imx35-eukrea {
pinctrl_fec: fecgrp {
fsl,pins = <
MX35_PAD_FEC_TX_CLK__FEC_TX_CLK 0x80000000
MX35_PAD_FEC_RX_CLK__FEC_RX_CLK 0x80000000
MX35_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000
MX35_PAD_FEC_COL__FEC_COL 0x80000000
MX35_PAD_FEC_RDATA0__FEC_RDATA_0 0x80000000
MX35_PAD_FEC_TDATA0__FEC_TDATA_0 0x80000000
MX35_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
MX35_PAD_FEC_MDC__FEC_MDC 0x80000000
MX35_PAD_FEC_MDIO__FEC_MDIO 0x80000000
MX35_PAD_FEC_TX_ERR__FEC_TX_ERR 0x80000000
MX35_PAD_FEC_RX_ERR__FEC_RX_ERR 0x80000000
MX35_PAD_FEC_CRS__FEC_CRS 0x80000000
MX35_PAD_FEC_RDATA1__FEC_RDATA_1 0x80000000
MX35_PAD_FEC_TDATA1__FEC_TDATA_1 0x80000000
MX35_PAD_FEC_RDATA2__FEC_RDATA_2 0x80000000
MX35_PAD_FEC_TDATA2__FEC_TDATA_2 0x80000000
MX35_PAD_FEC_RDATA3__FEC_RDATA_3 0x80000000
MX35_PAD_FEC_TDATA3__FEC_TDATA_3 0x80000000
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX35_PAD_FEC_TX_CLK__FEC_TX_CLK 0x80000000
MX35_PAD_FEC_RX_CLK__FEC_RX_CLK 0x80000000
MX35_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000
MX35_PAD_FEC_COL__FEC_COL 0x80000000
MX35_PAD_FEC_RDATA0__FEC_RDATA_0 0x80000000
MX35_PAD_FEC_TDATA0__FEC_TDATA_0 0x80000000
MX35_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
MX35_PAD_FEC_MDC__FEC_MDC 0x80000000
MX35_PAD_FEC_MDIO__FEC_MDIO 0x80000000
MX35_PAD_FEC_TX_ERR__FEC_TX_ERR 0x80000000
MX35_PAD_FEC_RX_ERR__FEC_RX_ERR 0x80000000
MX35_PAD_FEC_CRS__FEC_CRS 0x80000000
MX35_PAD_FEC_RDATA1__FEC_RDATA_1 0x80000000
MX35_PAD_FEC_TDATA1__FEC_TDATA_1 0x80000000
MX35_PAD_FEC_RDATA2__FEC_RDATA_2 0x80000000
MX35_PAD_FEC_TDATA2__FEC_TDATA_2 0x80000000
MX35_PAD_FEC_RDATA3__FEC_RDATA_3 0x80000000
MX35_PAD_FEC_TDATA3__FEC_TDATA_3 0x80000000
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX35_PAD_I2C1_CLK__I2C1_SCL 0x80000000
MX35_PAD_I2C1_DAT__I2C1_SDA 0x80000000
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX35_PAD_I2C1_CLK__I2C1_SCL 0x80000000
MX35_PAD_I2C1_DAT__I2C1_SDA 0x80000000
>;
};
pinctrl_tsc2007_1: tsc2007grp-1 {
fsl,pins = <MX35_PAD_ATA_DA2__GPIO3_2 0x80000000>;
};
pinctrl_tsc2007_1: tsc2007-1-grp {
fsl,pins = <MX35_PAD_ATA_DA2__GPIO3_2 0x80000000>;
};
};

88
arch/arm/boot/dts/nxp/imx/imx35-eukrea-mbimxsd35-baseboard.dts
View File

@@ -69,57 +69,55 @@ tlv320aic23: codec@1a {
};
&iomuxc {
imx35-eukrea {
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS 0x80000000
MX35_PAD_STXD4__AUDMUX_AUD4_TXD 0x80000000
MX35_PAD_SRXD4__AUDMUX_AUD4_RXD 0x80000000
MX35_PAD_SCK4__AUDMUX_AUD4_TXC 0x80000000
>;
};
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS 0x80000000
MX35_PAD_STXD4__AUDMUX_AUD4_TXD 0x80000000
MX35_PAD_SRXD4__AUDMUX_AUD4_RXD 0x80000000
MX35_PAD_SCK4__AUDMUX_AUD4_TXC 0x80000000
>;
};
pinctrl_bp1: bp1grp {
fsl,pins = <MX35_PAD_LD19__GPIO3_25 0x80000000>;
};
pinctrl_bp1: bp1grp {
fsl,pins = <MX35_PAD_LD19__GPIO3_25 0x80000000>;
};
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <
MX35_PAD_SD1_CMD__ESDHC1_CMD 0x80000000
MX35_PAD_SD1_CLK__ESDHC1_CLK 0x80000000
MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000
MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000
MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000
MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000
MX35_PAD_LD18__GPIO3_24 0x80000000 /* CD */
>;
};
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <
MX35_PAD_SD1_CMD__ESDHC1_CMD 0x80000000
MX35_PAD_SD1_CLK__ESDHC1_CLK 0x80000000
MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000
MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000
MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000
MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000
MX35_PAD_LD18__GPIO3_24 0x80000000 /* CD */
>;
};
pinctrl_led1: led1grp {
fsl,pins = <MX35_PAD_LD23__GPIO3_29 0x80000000>;
};
pinctrl_led1: led1grp {
fsl,pins = <MX35_PAD_LD23__GPIO3_29 0x80000000>;
};
pinctrl_reg_lcd_3v3: reg-lcd-3v3 {
fsl,pins = <MX35_PAD_D3_CLS__GPIO1_4 0x80000000>;
};
pinctrl_reg_lcd_3v3: reg-lcd-3v3grp {
fsl,pins = <MX35_PAD_D3_CLS__GPIO1_4 0x80000000>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX35_PAD_TXD1__UART1_TXD_MUX 0x1c5
MX35_PAD_RXD1__UART1_RXD_MUX 0x1c5
MX35_PAD_CTS1__UART1_CTS 0x1c5
MX35_PAD_RTS1__UART1_RTS 0x1c5
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX35_PAD_TXD1__UART1_TXD_MUX 0x1c5
MX35_PAD_RXD1__UART1_RXD_MUX 0x1c5
MX35_PAD_CTS1__UART1_CTS 0x1c5
MX35_PAD_RTS1__UART1_RTS 0x1c5
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX35_PAD_RXD2__UART2_RXD_MUX 0x1c5
MX35_PAD_TXD2__UART2_TXD_MUX 0x1c5
MX35_PAD_RTS2__UART2_RTS 0x1c5
MX35_PAD_CTS2__UART2_CTS 0x1c5
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX35_PAD_RXD2__UART2_RXD_MUX 0x1c5
MX35_PAD_TXD2__UART2_TXD_MUX 0x1c5
MX35_PAD_RTS2__UART2_RTS 0x1c5
MX35_PAD_CTS2__UART2_CTS 0x1c5
>;
};
};

36
arch/arm/boot/dts/nxp/imx/imx35-pdk.dts
View File

@@ -24,26 +24,24 @@ &esdhc1 {
};
&iomuxc {
imx35-pdk {
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <
MX35_PAD_SD1_CMD__ESDHC1_CMD 0x80000000
MX35_PAD_SD1_CLK__ESDHC1_CLK 0x80000000
MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000
MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000
MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000
MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000
>;
};
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <
MX35_PAD_SD1_CMD__ESDHC1_CMD 0x80000000
MX35_PAD_SD1_CLK__ESDHC1_CLK 0x80000000
MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000
MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000
MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000
MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX35_PAD_TXD1__UART1_TXD_MUX 0x1c5
MX35_PAD_RXD1__UART1_RXD_MUX 0x1c5
MX35_PAD_CTS1__UART1_CTS 0x1c5
MX35_PAD_RTS1__UART1_RTS 0x1c5
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX35_PAD_TXD1__UART1_TXD_MUX 0x1c5
MX35_PAD_RXD1__UART1_RXD_MUX 0x1c5
MX35_PAD_CTS1__UART1_CTS 0x1c5
MX35_PAD_RTS1__UART1_RTS 0x1c5
>;
};
};

2
arch/arm/boot/dts/nxp/imx/imx35.dtsi
View File

@@ -156,7 +156,7 @@ kpp: kpp@43fa8000 {
status = "disabled";
};
iomuxc: iomuxc@43fac000 {
iomuxc: pinctrl@43fac000 {
compatible = "fsl,imx35-iomuxc";
reg = <0x43fac000 0x4000>;
};