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drm/i915/psr: Allow SCL=0 on platforms with always-on VRR TG

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For Legacy timing generator, if there are no panel replay/sel_update or
other SRD constraints, the Set context latency (SCL) window should be
at least 1.

However, for VRR timing generator the SCL window can be 0. It has other
guardband constraints, but that are checked during guardband computation.

Allow SCL to be 0 for platforms that have VRR TG always on.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://patch.msgid.link/20260517142753.2813959-3-ankit.k.nautiyal@intel.com
This commit is contained in:
Ankit Nautiyal
2026-05-17 19:57:53 +05:30
parent d69da4f92d
commit 4f1cab2e48
1 changed files with 3 additions and 0 deletions
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3
drivers/gpu/drm/i915/display/intel_psr.c
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@@ -1519,6 +1519,9 @@ int _intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state
needs_panel_replay)
return 0;
if (intel_vrr_always_use_vrr_tg(display))
return 0;
return 1;
}