From 4f1cab2e4863d96ce13b8d94151f4848e38c3d5b Mon Sep 17 00:00:00 2001 From: Ankit Nautiyal Date: Sun, 17 May 2026 19:57:53 +0530 Subject: [PATCH] drm/i915/psr: Allow SCL=0 on platforms with always-on VRR TG MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For Legacy timing generator, if there are no panel replay/sel_update or other SRD constraints, the Set context latency (SCL) window should be at least 1. However, for VRR timing generator the SCL window can be 0. It has other guardband constraints, but that are checked during guardband computation. Allow SCL to be 0 for platforms that have VRR TG always on. Signed-off-by: Ankit Nautiyal Reviewed-by: Suraj Kandpal Reviewed-by: Jouni Högander Link: https://patch.msgid.link/20260517142753.2813959-3-ankit.k.nautiyal@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 6d3801cb0612..9382ad1e01d8 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1519,6 +1519,9 @@ int _intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state needs_panel_replay) return 0; + if (intel_vrr_always_use_vrr_tg(display)) + return 0; + return 1; }