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octeontx2-af: use dynamic interrupt vectors for CN10K

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This patch updates the driver to use a dynamic number of vectors instead
of a hard-coded value. This change accommodates the CN10KB, which has 2
vectors, unlike the previously supported chips that have 3 vectors.

Signed-off-by: Srujana Challa <schalla@marvell.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Srujana Challa
2024-08-29 13:39:33 +05:30
committed by David S. Miller
parent 43d0035b2c
commit 4ebe78e15b
3 changed files with 80 additions and 20 deletions
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5
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
View File

@@ -1856,8 +1856,9 @@ struct cpt_flt_eng_info_req {
struct cpt_flt_eng_info_rsp {
struct mbox_msghdr hdr;
u64 flt_eng_map[CPT_10K_AF_INT_VEC_RVU];
u64 rcvrd_eng_map[CPT_10K_AF_INT_VEC_RVU];
#define CPT_AF_MAX_FLT_INT_VECS 3
u64 flt_eng_map[CPT_AF_MAX_FLT_INT_VECS];
u64 rcvrd_eng_map[CPT_AF_MAX_FLT_INT_VECS];
u64 rsvd;
};

89
drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
View File

@@ -19,6 +19,9 @@
/* Length of initial context fetch in 128 byte words */
#define CPT_CTX_ILEN 1ULL
/* Interrupt vector count of CPT RVU and RAS interrupts */
#define CPT_10K_AF_RVU_RAS_INT_VEC_CNT 2
#define cpt_get_eng_sts(e_min, e_max, rsp, etype) \
({ \
u64 free_sts = 0, busy_sts = 0; \
@@ -37,6 +40,41 @@
(_rsp)->free_sts_##etype = free_sts; \
})
#define MAX_AE GENMASK_ULL(47, 32)
#define MAX_IE GENMASK_ULL(31, 16)
#define MAX_SE GENMASK_ULL(15, 0)
static u16 cpt_max_engines_get(struct rvu *rvu)
{
u16 max_ses, max_ies, max_aes;
u64 reg;
reg = rvu_read64(rvu, BLKADDR_CPT0, CPT_AF_CONSTANTS1);
max_ses = FIELD_GET(MAX_SE, reg);
max_ies = FIELD_GET(MAX_IE, reg);
max_aes = FIELD_GET(MAX_AE, reg);
return max_ses + max_ies + max_aes;
}
/* Number of flt interrupt vectors are depends on number of engines that the
* chip has. Each flt vector represents 64 engines.
*/
static int cpt_10k_flt_nvecs_get(struct rvu *rvu, u16 max_engs)
{
int flt_vecs;
flt_vecs = DIV_ROUND_UP(max_engs, 64);
if (flt_vecs > CPT_10K_AF_INT_VEC_FLT_MAX) {
dev_warn_once(rvu->dev, "flt_vecs:%d exceeds the max vectors:%d\n",
flt_vecs, CPT_10K_AF_INT_VEC_FLT_MAX);
flt_vecs = CPT_10K_AF_INT_VEC_FLT_MAX;
}
return flt_vecs;
}
static irqreturn_t cpt_af_flt_intr_handler(int vec, void *ptr)
{
struct rvu_block *block = ptr;
@@ -150,17 +188,26 @@ static void cpt_10k_unregister_interrupts(struct rvu_block *block, int off)
{
struct rvu *rvu = block->rvu;
int blkaddr = block->addr;
int i;
int i, flt_vecs;
u16 max_engs;
u8 nr;
max_engs = cpt_max_engines_get(rvu);
flt_vecs = cpt_10k_flt_nvecs_get(rvu, max_engs);
/* Disable all CPT AF interrupts */
rvu_write64(rvu, blkaddr, CPT_AF_FLTX_INT_ENA_W1C(0), ~0ULL);
rvu_write64(rvu, blkaddr, CPT_AF_FLTX_INT_ENA_W1C(1), ~0ULL);
rvu_write64(rvu, blkaddr, CPT_AF_FLTX_INT_ENA_W1C(2), 0xFFFF);
for (i = CPT_10K_AF_INT_VEC_FLT0; i < flt_vecs; i++) {
nr = (max_engs > 64) ? 64 : max_engs;
max_engs -= nr;
rvu_write64(rvu, blkaddr, CPT_AF_FLTX_INT_ENA_W1C(i),
INTR_MASK(nr));
}
rvu_write64(rvu, blkaddr, CPT_AF_RVU_INT_ENA_W1C, 0x1);
rvu_write64(rvu, blkaddr, CPT_AF_RAS_INT_ENA_W1C, 0x1);
for (i = 0; i < CPT_10K_AF_INT_VEC_CNT; i++)
/* CPT AF interrupt vectors are flt_int, rvu_int and ras_int. */
for (i = 0; i < flt_vecs + CPT_10K_AF_RVU_RAS_INT_VEC_CNT; i++)
if (rvu->irq_allocated[off + i]) {
free_irq(pci_irq_vector(rvu->pdev, off + i), block);
rvu->irq_allocated[off + i] = false;
@@ -206,12 +253,18 @@ void rvu_cpt_unregister_interrupts(struct rvu *rvu)
static int cpt_10k_register_interrupts(struct rvu_block *block, int off)
{
int rvu_intr_vec, ras_intr_vec;
struct rvu *rvu = block->rvu;
int blkaddr = block->addr;
irq_handler_t flt_fn;
int i, ret;
int i, ret, flt_vecs;
u16 max_engs;
u8 nr;
for (i = CPT_10K_AF_INT_VEC_FLT0; i < CPT_10K_AF_INT_VEC_RVU; i++) {
max_engs = cpt_max_engines_get(rvu);
flt_vecs = cpt_10k_flt_nvecs_get(rvu, max_engs);
for (i = CPT_10K_AF_INT_VEC_FLT0; i < flt_vecs; i++) {
sprintf(&rvu->irq_name[(off + i) * NAME_SIZE], "CPTAF FLT%d", i);
switch (i) {
@@ -229,20 +282,24 @@ static int cpt_10k_register_interrupts(struct rvu_block *block, int off)
flt_fn, &rvu->irq_name[(off + i) * NAME_SIZE]);
if (ret)
goto err;
if (i == CPT_10K_AF_INT_VEC_FLT2)
rvu_write64(rvu, blkaddr, CPT_AF_FLTX_INT_ENA_W1S(i), 0xFFFF);
else
rvu_write64(rvu, blkaddr, CPT_AF_FLTX_INT_ENA_W1S(i), ~0ULL);
nr = (max_engs > 64) ? 64 : max_engs;
max_engs -= nr;
rvu_write64(rvu, blkaddr, CPT_AF_FLTX_INT_ENA_W1S(i),
INTR_MASK(nr));
}
ret = rvu_cpt_do_register_interrupt(block, off + CPT_10K_AF_INT_VEC_RVU,
rvu_intr_vec = flt_vecs;
ras_intr_vec = rvu_intr_vec + 1;
ret = rvu_cpt_do_register_interrupt(block, off + rvu_intr_vec,
rvu_cpt_af_rvu_intr_handler,
"CPTAF RVU");
if (ret)
goto err;
rvu_write64(rvu, blkaddr, CPT_AF_RVU_INT_ENA_W1S, 0x1);
ret = rvu_cpt_do_register_interrupt(block, off + CPT_10K_AF_INT_VEC_RAS,
ret = rvu_cpt_do_register_interrupt(block, off + ras_intr_vec,
rvu_cpt_af_ras_intr_handler,
"CPTAF RAS");
if (ret)
@@ -921,13 +978,17 @@ int rvu_mbox_handler_cpt_flt_eng_info(struct rvu *rvu, struct cpt_flt_eng_info_r
struct rvu_block *block;
unsigned long flags;
int blkaddr, vec;
int flt_vecs;
u16 max_engs;
blkaddr = validate_and_get_cpt_blkaddr(req->blkaddr);
if (blkaddr < 0)
return blkaddr;
block = &rvu->hw->block[blkaddr];
for (vec = 0; vec < CPT_10K_AF_INT_VEC_RVU; vec++) {
max_engs = cpt_max_engines_get(rvu);
flt_vecs = cpt_10k_flt_nvecs_get(rvu, max_engs);
for (vec = 0; vec < flt_vecs; vec++) {
spin_lock_irqsave(&rvu->cpt_intr_lock, flags);
rsp->flt_eng_map[vec] = block->cpt_flt_eng_map[vec];
rsp->rcvrd_eng_map[vec] = block->cpt_rcvrd_eng_map[vec];

6
drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h
View File

@@ -71,13 +71,11 @@ enum cpt_af_int_vec_e {
CPT_AF_INT_VEC_CNT = 0x4,
};
enum cpt_10k_af_int_vec_e {
enum cpt_cn10k_flt_int_vec_e {
CPT_10K_AF_INT_VEC_FLT0 = 0x0,
CPT_10K_AF_INT_VEC_FLT1 = 0x1,
CPT_10K_AF_INT_VEC_FLT2 = 0x2,
CPT_10K_AF_INT_VEC_RVU = 0x3,
CPT_10K_AF_INT_VEC_RAS = 0x4,
CPT_10K_AF_INT_VEC_CNT = 0x5,
CPT_10K_AF_INT_VEC_FLT_MAX = 0x3,
};
/* NPA Admin function Interrupt Vector Enumeration */