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arm64: dts: ti: k3-am642-sk: Enable USB Super-Speed HOST port
Enable USB Super-Speed HOST port. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20210603142251.14563-5-kishon@ti.com
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committed by
Nishanth Menon
parent
354065bed2
commit
4e8aa4e355
@@ -5,6 +5,8 @@
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/dts-v1/;
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#include <dt-bindings/mux/ti-serdes.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/net/ti-dp83867.h>
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#include "k3-am642.dtsi"
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@@ -85,6 +87,12 @@ AM64X_IOPAD(0x0298, PIN_INPUT, 0) /* (D19) MMC1_SDCD */
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>;
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};
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main_usb0_pins_default: main-usb0-pins-default {
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pinctrl-single,pins = <
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AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
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>;
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};
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main_i2c1_pins_default: main-i2c1-pins-default {
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pinctrl-single,pins = <
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AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
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@@ -235,6 +243,33 @@ &sdhci1 {
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disable-wp;
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};
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&serdes_ln_ctrl {
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idle-states = <AM64_SERDES0_LANE0_USB>;
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};
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&serdes0 {
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serdes0_usb_link: phy@0 {
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reg = <0>;
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cdns,num-lanes = <1>;
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#phy-cells = <0>;
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cdns,phy-type = <PHY_TYPE_USB3>;
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resets = <&serdes_wiz0 1>;
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};
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};
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&usbss0 {
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ti,vbus-divider;
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};
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&usb0 {
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dr_mode = "host";
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maximum-speed = "super-speed";
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pinctrl-names = "default";
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pinctrl-0 = <&main_usb0_pins_default>;
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phys = <&serdes0_usb_link>;
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phy-names = "cdns3,usb3-phy";
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};
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&cpsw3g {
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pinctrl-names = "default";
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pinctrl-0 = <&mdio1_pins_default
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