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arm64: dts: intel: agilex5: Add simple-bus node on top of dma controller node

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Move dma-controller node under simple-bus node to allow bus node specific
property able to be properly defined. This is require to fulfill Agilex5
bus limitation that is limited to 40-addressable-bit.

Update the compatible string for the DMA controller nodes in the Agilex5
device tree from the generic "snps,axi-dma-1.01a" to the platform-specific
"altr,agilex5-axi-dma". Add fallback capability to ensure driver is able
to initialize properly.

This change enables the use of platform-specific features and constraints
in the driver, such as setting a 40-bit DMA addressable mask through
dma-ranges, which is required for Agilex5. It also aligns with the updated
device tree bindings and driver support for this compatible string.

Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
This commit is contained in:
Khairul Anuar Romli
2025-12-29 11:49:02 +08:00
committed by Dinh Nguyen
parent e0f489a52a
commit 4e6e93dfd5
1 changed files with 43 additions and 35 deletions
Download Patch File Download Diff File Expand all files Collapse all files

78
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
View File

@@ -324,42 +324,50 @@ ocram: sram@0 {
#size-cells = <1>;
};
dmac0: dma-controller@10db0000 {
compatible = "snps,axi-dma-1.01a";
reg = <0x10db0000 0x500>;
clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,
<&clkmgr AGILEX5_L4_MP_CLK>;
clock-names = "core-clk", "cfgr-clk";
interrupt-parent = <&intc>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
dma-channels = <4>;
snps,dma-masters = <1>;
snps,data-width = <2>;
snps,block-size = <32767 32767 32767 32767>;
snps,priority = <0 1 2 3>;
snps,axi-max-burst-len = <8>;
iommus = <&smmu 8>;
dma-coherent;
};
dma: dma-bus@10db0000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <2>;
ranges = <0x00 0x10db0000 0x00 0x20000>;
dma-ranges = <0x00 0x00 0x100 0x00>;
dmac1: dma-controller@10dc0000 {
compatible = "snps,axi-dma-1.01a";
reg = <0x10dc0000 0x500>;
clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,
<&clkmgr AGILEX5_L4_MP_CLK>;
clock-names = "core-clk", "cfgr-clk";
interrupt-parent = <&intc>;
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
dma-channels = <4>;
snps,dma-masters = <1>;
snps,data-width = <2>;
snps,block-size = <32767 32767 32767 32767>;
snps,priority = <0 1 2 3>;
snps,axi-max-burst-len = <8>;
iommus = <&smmu 9>;
dma-coherent;
dmac0: dma-controller@0 {
compatible = "altr,agilex5-axi-dma",
"snps,axi-dma-1.01a";
reg = <0x0 0x0 0x500>;
clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,
<&clkmgr AGILEX5_L4_MP_CLK>;
clock-names = "core-clk", "cfgr-clk";
interrupt-parent = <&intc>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
dma-channels = <4>;
snps,dma-masters = <1>;
snps,data-width = <2>;
snps,block-size = <32767 32767 32767 32767>;
snps,priority = <0 1 2 3>;
snps,axi-max-burst-len = <8>;
iommus = <&smmu 8>;
};
dmac1: dma-controller@10000 {
compatible = "altr,agilex5-axi-dma",
"snps,axi-dma-1.01a";
reg = <0x10000 0x0 0x500>;
clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,
<&clkmgr AGILEX5_L4_MP_CLK>;
clock-names = "core-clk", "cfgr-clk";
interrupt-parent = <&intc>;
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
dma-channels = <4>;
snps,dma-masters = <1>;
snps,data-width = <2>;
snps,block-size = <32767 32767 32767 32767>;
snps,priority = <0 1 2 3>;
snps,axi-max-burst-len = <8>;
iommus = <&smmu 9>;
};
};
rst: rstmgr@10d11000 {