mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-05-02 07:29:12 -04:00
Merge tag 'samsung-clk-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung
Pull Samsung clk driver updates from Krzysztof Kozlowski: - Exynos850: Add clock for Thermal Management Unit - Exynos7885: Fix duplicated ID in the header, add missing TOP PLLs and add clocks for USB block in the FSYS clock controller - ExynosAutov9: Add DPUM clock controller - ExynosAutov920: Add new (first) clock controllers: TOP and PERIC0 (and a bit more complete bindings) * tag 'samsung-clk-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: clk: samsung: add top clock support for ExynosAuto v920 SoC clk: samsung: clk-pll: Add support for pll_531x dt-bindings: clock: add ExynosAuto v920 SoC CMU bindings clk: samsung: exynos7885: Add USB related clocks to CMU_FSYS clk: samsung: clk-pll: Add support for pll_1418x clk: samsung: exynosautov9: add dpum clock support dt-bindings: clock: exynosautov9: add dpum clock clk: samsung: exynos7885: Add missing MUX clocks from PLLs in CMU_TOP clk: samsung: exynos7885: Update CLKS_NR_FSYS after bindings fix dt-bindings: clock: exynos7885: Add indices for USB clocks dt-bindings: clock: exynos7885: Add CMU_TOP PLL MUX indices dt-bindings: clock: exynos7885: Fix duplicated binding clk: samsung: exynos850: Add TMU clock dt-bindings: clock: exynos850: Add TMU clock
This commit is contained in:
Stephen Boyd
@@ -35,6 +35,7 @@ properties:
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- samsung,exynosautov9-cmu-top
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- samsung,exynosautov9-cmu-busmc
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- samsung,exynosautov9-cmu-core
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- samsung,exynosautov9-cmu-dpum
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- samsung,exynosautov9-cmu-fsys0
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- samsung,exynosautov9-cmu-fsys1
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- samsung,exynosautov9-cmu-fsys2
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@@ -109,6 +110,24 @@ allOf:
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- const: oscclk
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- const: dout_clkcmu_core_bus
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynosautov9-cmu-dpum
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (26 MHz)
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- description: DPU Main bus clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: bus
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- if:
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properties:
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compatible:
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@@ -0,0 +1,162 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/samsung,exynosautov920-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Samsung ExynosAuto v920 SoC clock controller
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maintainers:
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- Sunyeal Hong <sunyeal.hong@samsung.com>
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- Chanwoo Choi <cw00.choi@samsung.com>
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- Krzysztof Kozlowski <krzk@kernel.org>
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- Sylwester Nawrocki <s.nawrocki@samsung.com>
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description: |
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ExynosAuto v920 clock controller is comprised of several CMU units, generating
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clocks for different domains. Those CMU units are modeled as separate device
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tree nodes, and might depend on each other. Root clocks in that clock tree are
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two external clocks:: OSCCLK/XTCXO (38.4 MHz) and RTCCLK/XrtcXTI (32768 Hz).
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The external OSCCLK must be defined as fixed-rate clock in dts.
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CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
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dividers; all other clocks of function blocks (other CMUs) are usually
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derived from CMU_TOP.
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume. All clocks available for usage
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in clock consumer nodes are defined as preprocessor macros in
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'include/dt-bindings/clock/samsung,exynosautov920.h' header.
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properties:
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compatible:
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enum:
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- samsung,exynosautov920-cmu-top
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- samsung,exynosautov920-cmu-peric0
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- samsung,exynosautov920-cmu-peric1
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- samsung,exynosautov920-cmu-misc
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- samsung,exynosautov920-cmu-hsi0
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- samsung,exynosautov920-cmu-hsi1
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clocks:
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minItems: 1
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maxItems: 4
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clock-names:
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minItems: 1
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maxItems: 4
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"#clock-cells":
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const: 1
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reg:
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maxItems: 1
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynosautov920-cmu-top
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (38.4 MHz)
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clock-names:
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items:
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- const: oscclk
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- if:
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properties:
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compatible:
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contains:
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enum:
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- samsung,exynosautov920-cmu-peric0
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- samsung,exynosautov920-cmu-peric1
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (38.4 MHz)
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- description: CMU_PERICn NOC clock (from CMU_TOP)
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- description: CMU_PERICn IP clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: noc
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- const: ip
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- if:
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properties:
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compatible:
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enum:
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- samsung,exynosautov920-cmu-misc
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- samsung,exynosautov920-cmu-hsi0
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (38.4 MHz)
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- description: CMU_MISC/CMU_HSI0 NOC clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: noc
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynosautov920-cmu-hsi1
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (38.4 MHz)
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- description: CMU_HSI1 NOC clock (from CMU_TOP)
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- description: CMU_HSI1 USBDRD clock (from CMU_TOP)
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- description: CMU_HSI1 MMC_CARD clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: noc
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- const: usbdrd
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- const: mmc_card
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required:
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- compatible
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- "#clock-cells"
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- clocks
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- clock-names
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- reg
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additionalProperties: false
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examples:
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# Clock controller node for CMU_PERIC0
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- |
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#include <dt-bindings/clock/samsung,exynosautov920.h>
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cmu_peric0: clock-controller@10800000 {
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compatible = "samsung,exynosautov920-cmu-peric0";
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reg = <0x10800000 0x8000>;
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#clock-cells = <1>;
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clocks = <&xtcxo>,
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<&cmu_top DOUT_CLKCMU_PERIC0_NOC>,
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<&cmu_top DOUT_CLKCMU_PERIC0_IP>;
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clock-names = "oscclk",
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"noc",
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"ip";
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};
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...
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@@ -21,6 +21,7 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o
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obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7885.o
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obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o
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obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov9.o
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obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov920.o
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obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-gs101.o
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obj-$(CONFIG_S3C64XX_COMMON_CLK) += clk-s3c64xx.o
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obj-$(CONFIG_S5PV210_COMMON_CLK) += clk-s5pv210.o clk-s5pv210-audss.o
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@@ -17,10 +17,10 @@
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#include "clk-exynos-arm64.h"
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/* NOTE: Must be equal to the last clock ID increased by one */
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#define CLKS_NR_TOP (CLK_GOUT_FSYS_USB30DRD + 1)
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#define CLKS_NR_TOP (CLK_MOUT_SHARED1_PLL + 1)
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#define CLKS_NR_CORE (CLK_GOUT_TREX_P_CORE_PCLK_P_CORE + 1)
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#define CLKS_NR_PERI (CLK_GOUT_WDT1_PCLK + 1)
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#define CLKS_NR_FSYS (CLK_GOUT_MMC_SDIO_SDCLKIN + 1)
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#define CLKS_NR_FSYS (CLK_FSYS_USB30DRD_REF_CLK + 1)
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/* ---- CMU_TOP ------------------------------------------------------------- */
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@@ -162,6 +162,10 @@ static const struct samsung_pll_clock top_pll_clks[] __initconst = {
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NULL),
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};
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/* List of parent clocks for Muxes in CMU_TOP */
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PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" };
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PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" };
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/* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */
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PNAME(mout_core_bus_p) = { "dout_shared0_div2", "dout_shared1_div2",
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"dout_shared0_div3", "dout_shared0_div3" };
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@@ -189,6 +193,12 @@ PNAME(mout_fsys_mmc_sdio_p) = { "dout_shared0_div2", "dout_shared1_div2" };
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PNAME(mout_fsys_usb30drd_p) = { "dout_shared0_div4", "dout_shared1_div4" };
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static const struct samsung_mux_clock top_mux_clks[] __initconst = {
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/* TOP */
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MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,
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PLL_CON0_PLL_SHARED0, 4, 1),
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MUX(CLK_MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p,
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PLL_CON0_PLL_SHARED1, 4, 1),
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/* CORE */
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MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p,
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CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
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@@ -232,17 +242,17 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = {
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static const struct samsung_div_clock top_div_clks[] __initconst = {
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/* TOP */
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DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "fout_shared0_pll",
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DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "mout_shared0_pll",
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CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
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DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "fout_shared0_pll",
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DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll",
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CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
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DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2",
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CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
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DIV(CLK_DOUT_SHARED0_DIV5, "dout_shared0_div5", "fout_shared0_pll",
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DIV(CLK_DOUT_SHARED0_DIV5, "dout_shared0_div5", "mout_shared0_pll",
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CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 3),
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DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "fout_shared1_pll",
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DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll",
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CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
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DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "fout_shared1_pll",
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DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll",
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CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
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DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2",
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CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
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@@ -676,30 +686,56 @@ static const struct samsung_cmu_info core_cmu_info __initconst = {
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/* ---- CMU_FSYS ------------------------------------------------------------ */
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/* Register Offset definitions for CMU_FSYS (0x13400000) */
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#define PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER 0x0100
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#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER 0x0120
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#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER 0x0140
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#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER 0x0160
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#define PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER 0x0180
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#define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK 0x2030
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#define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN 0x2034
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#define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK 0x2038
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#define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN 0x203c
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#define CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK 0x2040
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#define CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN 0x2044
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#define PLL_LOCKTIME_PLL_USB 0x0000
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#define PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER 0x0100
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#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER 0x0120
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#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER 0x0140
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#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER 0x0160
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#define PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER 0x0180
|
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#define PLL_CON0_PLL_USB 0x01a0
|
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#define CLK_CON_GAT_CLK_FSYS_USB20PHY_CLKCORE 0x200c
|
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#define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK 0x2030
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#define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN 0x2034
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#define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK 0x2038
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#define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN 0x203c
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#define CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK 0x2040
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#define CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN 0x2044
|
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#define CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_20PHYCTRL 0x2068
|
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#define CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_30PHYCTRL_0 0x206c
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#define CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_30PHYCTRL_1 0x2070
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#define CLK_CON_GAT_GOUT_FSYS_USB30DRD_BUS_CLK_EARLY 0x2074
|
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#define CLK_CON_GAT_GOUT_FSYS_USB30DRD_REF_CLK 0x2078
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static const unsigned long fsys_clk_regs[] __initconst = {
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PLL_LOCKTIME_PLL_USB,
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PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER,
|
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PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER,
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PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER,
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PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER,
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PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER,
|
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PLL_CON0_PLL_USB,
|
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CLK_CON_GAT_CLK_FSYS_USB20PHY_CLKCORE,
|
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CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK,
|
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CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN,
|
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CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK,
|
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CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN,
|
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CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK,
|
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CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN,
|
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CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_20PHYCTRL,
|
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CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_30PHYCTRL_0,
|
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CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_30PHYCTRL_1,
|
||||
CLK_CON_GAT_GOUT_FSYS_USB30DRD_BUS_CLK_EARLY,
|
||||
CLK_CON_GAT_GOUT_FSYS_USB30DRD_REF_CLK,
|
||||
};
|
||||
|
||||
static const struct samsung_pll_rate_table pll_usb_rate_table[] __initconst = {
|
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PLL_35XX_RATE(26 * MHZ, 50000000U, 400, 13, 4),
|
||||
};
|
||||
|
||||
static const struct samsung_pll_clock fsys_pll_clks[] __initconst = {
|
||||
PLL(pll_1418x, CLK_FOUT_USB_PLL, "fout_usb_pll", "oscclk",
|
||||
PLL_LOCKTIME_PLL_USB, PLL_CON0_PLL_USB,
|
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pll_usb_rate_table),
|
||||
};
|
||||
|
||||
/* List of parent clocks for Muxes in CMU_FSYS */
|
||||
@@ -708,6 +744,7 @@ PNAME(mout_fsys_mmc_card_user_p) = { "oscclk", "dout_fsys_mmc_card" };
|
||||
PNAME(mout_fsys_mmc_embd_user_p) = { "oscclk", "dout_fsys_mmc_embd" };
|
||||
PNAME(mout_fsys_mmc_sdio_user_p) = { "oscclk", "dout_fsys_mmc_sdio" };
|
||||
PNAME(mout_fsys_usb30drd_user_p) = { "oscclk", "dout_fsys_usb30drd" };
|
||||
PNAME(mout_usb_pll_p) = { "oscclk", "fout_usb_pll" };
|
||||
|
||||
static const struct samsung_mux_clock fsys_mux_clks[] __initconst = {
|
||||
MUX(CLK_MOUT_FSYS_BUS_USER, "mout_fsys_bus_user", mout_fsys_bus_user_p,
|
||||
@@ -721,12 +758,16 @@ static const struct samsung_mux_clock fsys_mux_clks[] __initconst = {
|
||||
MUX_F(CLK_MOUT_FSYS_MMC_SDIO_USER, "mout_fsys_mmc_sdio_user",
|
||||
mout_fsys_mmc_sdio_user_p, PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER,
|
||||
4, 1, CLK_SET_RATE_PARENT, 0),
|
||||
MUX_F(CLK_MOUT_FSYS_USB30DRD_USER, "mout_fsys_usb30drd_user",
|
||||
MUX(CLK_MOUT_FSYS_USB30DRD_USER, "mout_fsys_usb30drd_user",
|
||||
mout_fsys_usb30drd_user_p, PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER,
|
||||
4, 1, CLK_SET_RATE_PARENT, 0),
|
||||
4, 1),
|
||||
nMUX_F(CLK_MOUT_USB_PLL, "mout_usb_pll", mout_usb_pll_p,
|
||||
PLL_CON0_PLL_USB, 4, 1, CLK_SET_RATE_PARENT, 0),
|
||||
};
|
||||
|
||||
static const struct samsung_gate_clock fsys_gate_clks[] __initconst = {
|
||||
GATE(CLK_FSYS_USB20PHY_CLKCORE, "clk_fsys_usb20phy_clkcore", "mout_usb_pll",
|
||||
CLK_CON_GAT_CLK_FSYS_USB20PHY_CLKCORE, 21, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(CLK_GOUT_MMC_CARD_ACLK, "gout_mmc_card_aclk", "mout_fsys_bus_user",
|
||||
CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK, 21, 0, 0),
|
||||
GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin",
|
||||
@@ -742,9 +783,21 @@ static const struct samsung_gate_clock fsys_gate_clks[] __initconst = {
|
||||
GATE(CLK_GOUT_MMC_SDIO_SDCLKIN, "gout_mmc_sdio_sdclkin",
|
||||
"mout_fsys_mmc_sdio_user", CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN,
|
||||
21, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(CLK_FSYS_USB30DRD_ACLK_20PHYCTRL, "clk_fsys_usb30drd_aclk_20phyctrl",
|
||||
"mout_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_20PHYCTRL, 21, 0, 0),
|
||||
GATE(CLK_FSYS_USB30DRD_ACLK_30PHYCTRL_0, "clk_fsys_usb30drd_aclk_30phyctrl_0",
|
||||
"mout_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_30PHYCTRL_0, 21, 0, 0),
|
||||
GATE(CLK_FSYS_USB30DRD_ACLK_30PHYCTRL_1, "clk_fsys_usb30drd_aclk_30phyctrl_1",
|
||||
"mout_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_30PHYCTRL_1, 21, 0, 0),
|
||||
GATE(CLK_FSYS_USB30DRD_BUS_CLK_EARLY, "clk_fsys_usb30drd_bus_clk_early",
|
||||
"mout_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_USB30DRD_BUS_CLK_EARLY, 21, 0, 0),
|
||||
GATE(CLK_FSYS_USB30DRD_REF_CLK, "clk_fsys_usb30drd_ref_clk", "mout_fsys_usb30drd_user",
|
||||
CLK_CON_GAT_GOUT_FSYS_USB30DRD_REF_CLK, 21, 0, 0),
|
||||
};
|
||||
|
||||
static const struct samsung_cmu_info fsys_cmu_info __initconst = {
|
||||
.pll_clks = fsys_pll_clks,
|
||||
.nr_pll_clks = ARRAY_SIZE(fsys_pll_clks),
|
||||
.mux_clks = fsys_mux_clks,
|
||||
.nr_mux_clks = ARRAY_SIZE(fsys_mux_clks),
|
||||
.gate_clks = fsys_gate_clks,
|
||||
|
||||
@@ -28,7 +28,7 @@
|
||||
#define CLKS_NR_HSI (CLK_GOUT_HSI_CMU_HSI_PCLK + 1)
|
||||
#define CLKS_NR_IS (CLK_GOUT_IS_SYSREG_PCLK + 1)
|
||||
#define CLKS_NR_MFCMSCL (CLK_GOUT_MFCMSCL_SYSREG_PCLK + 1)
|
||||
#define CLKS_NR_PERI (CLK_GOUT_WDT1_PCLK + 1)
|
||||
#define CLKS_NR_PERI (CLK_GOUT_BUSIF_TMU_PCLK + 1)
|
||||
#define CLKS_NR_CORE (CLK_GOUT_SPDMA_CORE_ACLK + 1)
|
||||
#define CLKS_NR_DPU (CLK_GOUT_DPU_SYSREG_PCLK + 1)
|
||||
|
||||
@@ -1921,6 +1921,7 @@ static const struct samsung_cmu_info mfcmscl_cmu_info __initconst = {
|
||||
#define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0 0x200c
|
||||
#define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1 0x2010
|
||||
#define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2 0x2014
|
||||
#define CLK_CON_GAT_GOUT_PERI_BUSIF_TMU_PCLK 0x2018
|
||||
#define CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK 0x2020
|
||||
#define CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK 0x2024
|
||||
#define CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK 0x2028
|
||||
@@ -1957,6 +1958,7 @@ static const unsigned long peri_clk_regs[] __initconst = {
|
||||
CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0,
|
||||
CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1,
|
||||
CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2,
|
||||
CLK_CON_GAT_GOUT_PERI_BUSIF_TMU_PCLK,
|
||||
CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK,
|
||||
CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK,
|
||||
CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK,
|
||||
@@ -2068,6 +2070,9 @@ static const struct samsung_gate_clock peri_gate_clks[] __initconst = {
|
||||
GATE(CLK_GOUT_GPIO_PERI_PCLK, "gout_gpio_peri_pclk",
|
||||
"mout_peri_bus_user",
|
||||
CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(CLK_GOUT_BUSIF_TMU_PCLK, "gout_busif_tmu_pclk",
|
||||
"mout_peri_bus_user",
|
||||
CLK_CON_GAT_GOUT_PERI_BUSIF_TMU_PCLK, 21, 0, 0),
|
||||
};
|
||||
|
||||
static const struct samsung_cmu_info peri_cmu_info __initconst = {
|
||||
|
||||
@@ -20,6 +20,7 @@
|
||||
#define CLKS_NR_TOP (GOUT_CLKCMU_PERIS_BUS + 1)
|
||||
#define CLKS_NR_BUSMC (CLK_GOUT_BUSMC_SPDMA_PCLK + 1)
|
||||
#define CLKS_NR_CORE (CLK_GOUT_CORE_CMU_CORE_PCLK + 1)
|
||||
#define CLKS_NR_DPUM (CLK_GOUT_DPUM_SYSMMU_D3_CLK + 1)
|
||||
#define CLKS_NR_FSYS0 (CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK + 1)
|
||||
#define CLKS_NR_FSYS1 (CLK_GOUT_FSYS1_USB30_1_ACLK + 1)
|
||||
#define CLKS_NR_FSYS2 (CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO + 1)
|
||||
@@ -1076,6 +1077,85 @@ static const struct samsung_cmu_info core_cmu_info __initconst = {
|
||||
.clk_name = "dout_clkcmu_core_bus",
|
||||
};
|
||||
|
||||
/* ---- CMU_DPUM ---------------------------------------------------------- */
|
||||
|
||||
/* Register Offset definitions for CMU_DPUM (0x18c00000) */
|
||||
#define PLL_CON0_MUX_CLKCMU_DPUM_BUS_USER 0x0600
|
||||
#define CLK_CON_DIV_DIV_CLK_DPUM_BUSP 0x1800
|
||||
#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DECON 0x202c
|
||||
#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DMA 0x2030
|
||||
#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DPP 0x2034
|
||||
#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D0_DPUM_IPCLKPORT_CLK_S1 0x207c
|
||||
#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D1_DPUM_IPCLKPORT_CLK_S1 0x2084
|
||||
#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D2_DPUM_IPCLKPORT_CLK_S1 0x208c
|
||||
#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D3_DPUM_IPCLKPORT_CLK_S1 0x2094
|
||||
|
||||
static const unsigned long dpum_clk_regs[] __initconst = {
|
||||
PLL_CON0_MUX_CLKCMU_DPUM_BUS_USER,
|
||||
CLK_CON_DIV_DIV_CLK_DPUM_BUSP,
|
||||
CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DECON,
|
||||
CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DMA,
|
||||
CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DPP,
|
||||
CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D0_DPUM_IPCLKPORT_CLK_S1,
|
||||
CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D1_DPUM_IPCLKPORT_CLK_S1,
|
||||
CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D2_DPUM_IPCLKPORT_CLK_S1,
|
||||
CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D3_DPUM_IPCLKPORT_CLK_S1,
|
||||
};
|
||||
|
||||
PNAME(mout_dpum_bus_user_p) = { "oscclk", "dout_clkcmu_dpum_bus" };
|
||||
|
||||
static const struct samsung_mux_clock dpum_mux_clks[] __initconst = {
|
||||
MUX(CLK_MOUT_DPUM_BUS_USER, "mout_dpum_bus_user",
|
||||
mout_dpum_bus_user_p, PLL_CON0_MUX_CLKCMU_DPUM_BUS_USER, 4, 1),
|
||||
};
|
||||
|
||||
static const struct samsung_div_clock dpum_div_clks[] __initconst = {
|
||||
DIV(CLK_DOUT_DPUM_BUSP, "dout_dpum_busp", "mout_dpum_bus_user",
|
||||
CLK_CON_DIV_DIV_CLK_DPUM_BUSP, 0, 3),
|
||||
};
|
||||
|
||||
static const struct samsung_gate_clock dpum_gate_clks[] __initconst = {
|
||||
GATE(CLK_GOUT_DPUM_ACLK_DECON, "gout_dpum_decon_aclk",
|
||||
"mout_dpum_bus_user",
|
||||
CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DECON, 21,
|
||||
0, 0),
|
||||
GATE(CLK_GOUT_DPUM_ACLK_DMA, "gout_dpum_dma_aclk", "mout_dpum_bus_user",
|
||||
CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DMA, 21,
|
||||
0, 0),
|
||||
GATE(CLK_GOUT_DPUM_ACLK_DPP, "gout_dpum_dpp_aclk", "mout_dpum_bus_user",
|
||||
CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DPP, 21,
|
||||
0, 0),
|
||||
GATE(CLK_GOUT_DPUM_SYSMMU_D0_CLK, "gout_dpum_sysmmu_d0_clk",
|
||||
"mout_dpum_bus_user",
|
||||
CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D0_DPUM_IPCLKPORT_CLK_S1, 21,
|
||||
0, 0),
|
||||
GATE(CLK_GOUT_DPUM_SYSMMU_D1_CLK, "gout_dpum_sysmmu_d1_clk",
|
||||
"mout_dpum_bus_user",
|
||||
CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D1_DPUM_IPCLKPORT_CLK_S1, 21,
|
||||
0, 0),
|
||||
GATE(CLK_GOUT_DPUM_SYSMMU_D2_CLK, "gout_dpum_sysmmu_d2_clk",
|
||||
"mout_dpum_bus_user",
|
||||
CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D2_DPUM_IPCLKPORT_CLK_S1, 21,
|
||||
0, 0),
|
||||
GATE(CLK_GOUT_DPUM_SYSMMU_D3_CLK, "gout_dpum_sysmmu_d3_clk",
|
||||
"mout_dpum_bus_user",
|
||||
CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D3_DPUM_IPCLKPORT_CLK_S1, 21,
|
||||
0, 0),
|
||||
};
|
||||
|
||||
static const struct samsung_cmu_info dpum_cmu_info __initconst = {
|
||||
.mux_clks = dpum_mux_clks,
|
||||
.nr_mux_clks = ARRAY_SIZE(dpum_mux_clks),
|
||||
.div_clks = dpum_div_clks,
|
||||
.nr_div_clks = ARRAY_SIZE(dpum_div_clks),
|
||||
.gate_clks = dpum_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(dpum_gate_clks),
|
||||
.nr_clk_ids = CLKS_NR_DPUM,
|
||||
.clk_regs = dpum_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(dpum_clk_regs),
|
||||
.clk_name = "bus",
|
||||
};
|
||||
|
||||
/* ---- CMU_FSYS0 ---------------------------------------------------------- */
|
||||
|
||||
/* Register Offset definitions for CMU_FSYS2 (0x17700000) */
|
||||
@@ -2085,6 +2165,9 @@ static const struct of_device_id exynosautov9_cmu_of_match[] = {
|
||||
}, {
|
||||
.compatible = "samsung,exynosautov9-cmu-core",
|
||||
.data = &core_cmu_info,
|
||||
}, {
|
||||
.compatible = "samsung,exynosautov9-cmu-dpum",
|
||||
.data = &dpum_cmu_info,
|
||||
}, {
|
||||
.compatible = "samsung,exynosautov9-cmu-fsys0",
|
||||
.data = &fsys0_cmu_info,
|
||||
|
||||
1173
drivers/clk/samsung/clk-exynosautov920.c
Normal file
1173
drivers/clk/samsung/clk-exynosautov920.c
Normal file
File diff suppressed because it is too large
Load Diff
@@ -430,6 +430,9 @@ static const struct clk_ops samsung_pll36xx_clk_min_ops = {
|
||||
#define PLL0822X_LOCK_STAT_SHIFT (29)
|
||||
#define PLL0822X_ENABLE_SHIFT (31)
|
||||
|
||||
/* PLL1418x is similar to PLL0822x, except that MDIV is one bit smaller */
|
||||
#define PLL1418X_MDIV_MASK (0x1FF)
|
||||
|
||||
static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
@@ -438,7 +441,10 @@ static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw,
|
||||
u64 fvco = parent_rate;
|
||||
|
||||
pll_con3 = readl_relaxed(pll->con_reg);
|
||||
mdiv = (pll_con3 >> PLL0822X_MDIV_SHIFT) & PLL0822X_MDIV_MASK;
|
||||
if (pll->type != pll_1418x)
|
||||
mdiv = (pll_con3 >> PLL0822X_MDIV_SHIFT) & PLL0822X_MDIV_MASK;
|
||||
else
|
||||
mdiv = (pll_con3 >> PLL0822X_MDIV_SHIFT) & PLL1418X_MDIV_MASK;
|
||||
pdiv = (pll_con3 >> PLL0822X_PDIV_SHIFT) & PLL0822X_PDIV_MASK;
|
||||
sdiv = (pll_con3 >> PLL0822X_SDIV_SHIFT) & PLL0822X_SDIV_MASK;
|
||||
|
||||
@@ -456,7 +462,12 @@ static int samsung_pll0822x_set_rate(struct clk_hw *hw, unsigned long drate,
|
||||
{
|
||||
const struct samsung_pll_rate_table *rate;
|
||||
struct samsung_clk_pll *pll = to_clk_pll(hw);
|
||||
u32 pll_con3;
|
||||
u32 mdiv_mask, pll_con3;
|
||||
|
||||
if (pll->type != pll_1418x)
|
||||
mdiv_mask = PLL0822X_MDIV_MASK;
|
||||
else
|
||||
mdiv_mask = PLL1418X_MDIV_MASK;
|
||||
|
||||
/* Get required rate settings from table */
|
||||
rate = samsung_get_pll_settings(pll, drate);
|
||||
@@ -468,7 +479,7 @@ static int samsung_pll0822x_set_rate(struct clk_hw *hw, unsigned long drate,
|
||||
|
||||
/* Change PLL PMS values */
|
||||
pll_con3 = readl_relaxed(pll->con_reg);
|
||||
pll_con3 &= ~((PLL0822X_MDIV_MASK << PLL0822X_MDIV_SHIFT) |
|
||||
pll_con3 &= ~((mdiv_mask << PLL0822X_MDIV_SHIFT) |
|
||||
(PLL0822X_PDIV_MASK << PLL0822X_PDIV_SHIFT) |
|
||||
(PLL0822X_SDIV_MASK << PLL0822X_SDIV_SHIFT));
|
||||
pll_con3 |= (rate->mdiv << PLL0822X_MDIV_SHIFT) |
|
||||
@@ -1261,6 +1272,47 @@ static const struct clk_ops samsung_pll2650xx_clk_min_ops = {
|
||||
.recalc_rate = samsung_pll2650xx_recalc_rate,
|
||||
};
|
||||
|
||||
/*
|
||||
* PLL531X Clock Type
|
||||
*/
|
||||
/* Maximum lock time can be 500 * PDIV cycles */
|
||||
#define PLL531X_LOCK_FACTOR (500)
|
||||
#define PLL531X_MDIV_MASK (0x3FF)
|
||||
#define PLL531X_PDIV_MASK (0x3F)
|
||||
#define PLL531X_SDIV_MASK (0x7)
|
||||
#define PLL531X_FDIV_MASK (0xFFFFFFFF)
|
||||
#define PLL531X_MDIV_SHIFT (16)
|
||||
#define PLL531X_PDIV_SHIFT (8)
|
||||
#define PLL531X_SDIV_SHIFT (0)
|
||||
|
||||
static unsigned long samsung_pll531x_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct samsung_clk_pll *pll = to_clk_pll(hw);
|
||||
u32 pdiv, sdiv, fdiv, pll_con0, pll_con8;
|
||||
u64 mdiv, fout = parent_rate;
|
||||
|
||||
pll_con0 = readl_relaxed(pll->con_reg);
|
||||
pll_con8 = readl_relaxed(pll->con_reg + 20);
|
||||
mdiv = (pll_con0 >> PLL531X_MDIV_SHIFT) & PLL531X_MDIV_MASK;
|
||||
pdiv = (pll_con0 >> PLL531X_PDIV_SHIFT) & PLL531X_PDIV_MASK;
|
||||
sdiv = (pll_con0 >> PLL531X_SDIV_SHIFT) & PLL531X_SDIV_MASK;
|
||||
fdiv = (pll_con8 & PLL531X_FDIV_MASK);
|
||||
|
||||
if (fdiv >> 31)
|
||||
mdiv--;
|
||||
|
||||
fout *= (mdiv << 24) + (fdiv >> 8);
|
||||
do_div(fout, (pdiv << sdiv));
|
||||
fout >>= 24;
|
||||
|
||||
return (unsigned long)fout;
|
||||
}
|
||||
|
||||
static const struct clk_ops samsung_pll531x_clk_ops = {
|
||||
.recalc_rate = samsung_pll531x_recalc_rate,
|
||||
};
|
||||
|
||||
static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
|
||||
const struct samsung_pll_clock *pll_clk)
|
||||
{
|
||||
@@ -1317,6 +1369,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
|
||||
init.ops = &samsung_pll35xx_clk_ops;
|
||||
break;
|
||||
case pll_1417x:
|
||||
case pll_1418x:
|
||||
case pll_0818x:
|
||||
case pll_0822x:
|
||||
case pll_0516x:
|
||||
@@ -1394,6 +1447,9 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
|
||||
else
|
||||
init.ops = &samsung_pll2650xx_clk_ops;
|
||||
break;
|
||||
case pll_531x:
|
||||
init.ops = &samsung_pll531x_clk_ops;
|
||||
break;
|
||||
default:
|
||||
pr_warn("%s: Unknown pll type for pll clk %s\n",
|
||||
__func__, pll_clk->name);
|
||||
|
||||
@@ -30,6 +30,7 @@ enum samsung_pll_type {
|
||||
pll_2650x,
|
||||
pll_2650xx,
|
||||
pll_1417x,
|
||||
pll_1418x,
|
||||
pll_1450x,
|
||||
pll_1451x,
|
||||
pll_1452x,
|
||||
@@ -41,6 +42,7 @@ enum samsung_pll_type {
|
||||
pll_0516x,
|
||||
pll_0517x,
|
||||
pll_0518x,
|
||||
pll_531x,
|
||||
};
|
||||
|
||||
#define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \
|
||||
|
||||
@@ -69,6 +69,8 @@
|
||||
#define CLK_GOUT_FSYS_MMC_EMBD 58
|
||||
#define CLK_GOUT_FSYS_MMC_SDIO 59
|
||||
#define CLK_GOUT_FSYS_USB30DRD 60
|
||||
#define CLK_MOUT_SHARED0_PLL 61
|
||||
#define CLK_MOUT_SHARED1_PLL 62
|
||||
|
||||
/* CMU_CORE */
|
||||
#define CLK_MOUT_CORE_BUS_USER 1
|
||||
@@ -132,16 +134,24 @@
|
||||
#define CLK_GOUT_WDT1_PCLK 43
|
||||
|
||||
/* CMU_FSYS */
|
||||
#define CLK_MOUT_FSYS_BUS_USER 1
|
||||
#define CLK_MOUT_FSYS_MMC_CARD_USER 2
|
||||
#define CLK_MOUT_FSYS_MMC_EMBD_USER 3
|
||||
#define CLK_MOUT_FSYS_MMC_SDIO_USER 4
|
||||
#define CLK_MOUT_FSYS_USB30DRD_USER 4
|
||||
#define CLK_GOUT_MMC_CARD_ACLK 5
|
||||
#define CLK_GOUT_MMC_CARD_SDCLKIN 6
|
||||
#define CLK_GOUT_MMC_EMBD_ACLK 7
|
||||
#define CLK_GOUT_MMC_EMBD_SDCLKIN 8
|
||||
#define CLK_GOUT_MMC_SDIO_ACLK 9
|
||||
#define CLK_GOUT_MMC_SDIO_SDCLKIN 10
|
||||
#define CLK_MOUT_FSYS_BUS_USER 1
|
||||
#define CLK_MOUT_FSYS_MMC_CARD_USER 2
|
||||
#define CLK_MOUT_FSYS_MMC_EMBD_USER 3
|
||||
#define CLK_MOUT_FSYS_MMC_SDIO_USER 4
|
||||
#define CLK_GOUT_MMC_CARD_ACLK 5
|
||||
#define CLK_GOUT_MMC_CARD_SDCLKIN 6
|
||||
#define CLK_GOUT_MMC_EMBD_ACLK 7
|
||||
#define CLK_GOUT_MMC_EMBD_SDCLKIN 8
|
||||
#define CLK_GOUT_MMC_SDIO_ACLK 9
|
||||
#define CLK_GOUT_MMC_SDIO_SDCLKIN 10
|
||||
#define CLK_MOUT_FSYS_USB30DRD_USER 11
|
||||
#define CLK_MOUT_USB_PLL 12
|
||||
#define CLK_FOUT_USB_PLL 13
|
||||
#define CLK_FSYS_USB20PHY_CLKCORE 14
|
||||
#define CLK_FSYS_USB30DRD_ACLK_20PHYCTRL 15
|
||||
#define CLK_FSYS_USB30DRD_ACLK_30PHYCTRL_0 16
|
||||
#define CLK_FSYS_USB30DRD_ACLK_30PHYCTRL_1 17
|
||||
#define CLK_FSYS_USB30DRD_BUS_CLK_EARLY 18
|
||||
#define CLK_FSYS_USB30DRD_REF_CLK 19
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_7885_H */
|
||||
|
||||
@@ -358,6 +358,7 @@
|
||||
#define CLK_GOUT_UART_PCLK 32
|
||||
#define CLK_GOUT_WDT0_PCLK 33
|
||||
#define CLK_GOUT_WDT1_PCLK 34
|
||||
#define CLK_GOUT_BUSIF_TMU_PCLK 35
|
||||
|
||||
/* CMU_CORE */
|
||||
#define CLK_MOUT_CORE_BUS_USER 1
|
||||
|
||||
@@ -179,6 +179,17 @@
|
||||
#define CLK_GOUT_CORE_CCI_PCLK 4
|
||||
#define CLK_GOUT_CORE_CMU_CORE_PCLK 5
|
||||
|
||||
/* CMU_DPUM */
|
||||
#define CLK_MOUT_DPUM_BUS_USER 1
|
||||
#define CLK_DOUT_DPUM_BUSP 2
|
||||
#define CLK_GOUT_DPUM_ACLK_DECON 3
|
||||
#define CLK_GOUT_DPUM_ACLK_DMA 4
|
||||
#define CLK_GOUT_DPUM_ACLK_DPP 5
|
||||
#define CLK_GOUT_DPUM_SYSMMU_D0_CLK 6
|
||||
#define CLK_GOUT_DPUM_SYSMMU_D1_CLK 7
|
||||
#define CLK_GOUT_DPUM_SYSMMU_D2_CLK 8
|
||||
#define CLK_GOUT_DPUM_SYSMMU_D3_CLK 9
|
||||
|
||||
/* CMU_FSYS0 */
|
||||
#define CLK_MOUT_FSYS0_BUS_USER 1
|
||||
#define CLK_MOUT_FSYS0_PCIE_USER 2
|
||||
|
||||
191
include/dt-bindings/clock/samsung,exynosautov920.h
Normal file
191
include/dt-bindings/clock/samsung,exynosautov920.h
Normal file
@@ -0,0 +1,191 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2024 Samsung Electronics Co., Ltd.
|
||||
* Author: Sunyeal Hong <sunyeal.hong@samsung.com>
|
||||
*
|
||||
* Device Tree binding constants for ExynosAuto v920 clock controller.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_EXYNOSAUTOV920_H
|
||||
#define _DT_BINDINGS_CLOCK_EXYNOSAUTOV920_H
|
||||
|
||||
/* CMU_TOP */
|
||||
#define FOUT_SHARED0_PLL 1
|
||||
#define FOUT_SHARED1_PLL 2
|
||||
#define FOUT_SHARED2_PLL 3
|
||||
#define FOUT_SHARED3_PLL 4
|
||||
#define FOUT_SHARED4_PLL 5
|
||||
#define FOUT_SHARED5_PLL 6
|
||||
#define FOUT_MMC_PLL 7
|
||||
|
||||
/* MUX in CMU_TOP */
|
||||
#define MOUT_SHARED0_PLL 8
|
||||
#define MOUT_SHARED1_PLL 9
|
||||
#define MOUT_SHARED2_PLL 10
|
||||
#define MOUT_SHARED3_PLL 11
|
||||
#define MOUT_SHARED4_PLL 12
|
||||
#define MOUT_SHARED5_PLL 13
|
||||
#define MOUT_MMC_PLL 14
|
||||
#define MOUT_CLKCMU_CMU_BOOST 15
|
||||
#define MOUT_CLKCMU_CMU_CMUREF 16
|
||||
#define MOUT_CLKCMU_ACC_NOC 17
|
||||
#define MOUT_CLKCMU_ACC_ORB 18
|
||||
#define MOUT_CLKCMU_APM_NOC 19
|
||||
#define MOUT_CLKCMU_AUD_CPU 20
|
||||
#define MOUT_CLKCMU_AUD_NOC 21
|
||||
#define MOUT_CLKCMU_CPUCL0_SWITCH 22
|
||||
#define MOUT_CLKCMU_CPUCL0_CLUSTER 23
|
||||
#define MOUT_CLKCMU_CPUCL0_DBG 24
|
||||
#define MOUT_CLKCMU_CPUCL1_SWITCH 25
|
||||
#define MOUT_CLKCMU_CPUCL1_CLUSTER 26
|
||||
#define MOUT_CLKCMU_CPUCL2_SWITCH 27
|
||||
#define MOUT_CLKCMU_CPUCL2_CLUSTER 28
|
||||
#define MOUT_CLKCMU_DNC_NOC 29
|
||||
#define MOUT_CLKCMU_DPTX_NOC 30
|
||||
#define MOUT_CLKCMU_DPTX_DPGTC 31
|
||||
#define MOUT_CLKCMU_DPTX_DPOSC 32
|
||||
#define MOUT_CLKCMU_DPUB_NOC 33
|
||||
#define MOUT_CLKCMU_DPUB_DSIM 34
|
||||
#define MOUT_CLKCMU_DPUF0_NOC 35
|
||||
#define MOUT_CLKCMU_DPUF1_NOC 36
|
||||
#define MOUT_CLKCMU_DPUF2_NOC 37
|
||||
#define MOUT_CLKCMU_DSP_NOC 38
|
||||
#define MOUT_CLKCMU_G3D_SWITCH 39
|
||||
#define MOUT_CLKCMU_G3D_NOCP 40
|
||||
#define MOUT_CLKCMU_GNPU_NOC 41
|
||||
#define MOUT_CLKCMU_HSI0_NOC 42
|
||||
#define MOUT_CLKCMU_HSI1_NOC 43
|
||||
#define MOUT_CLKCMU_HSI1_USBDRD 44
|
||||
#define MOUT_CLKCMU_HSI1_MMC_CARD 45
|
||||
#define MOUT_CLKCMU_HSI2_NOC 46
|
||||
#define MOUT_CLKCMU_HSI2_NOC_UFS 47
|
||||
#define MOUT_CLKCMU_HSI2_UFS_EMBD 48
|
||||
#define MOUT_CLKCMU_HSI2_ETHERNET 49
|
||||
#define MOUT_CLKCMU_ISP_NOC 50
|
||||
#define MOUT_CLKCMU_M2M_NOC 51
|
||||
#define MOUT_CLKCMU_M2M_JPEG 52
|
||||
#define MOUT_CLKCMU_MFC_MFC 53
|
||||
#define MOUT_CLKCMU_MFC_WFD 54
|
||||
#define MOUT_CLKCMU_MFD_NOC 55
|
||||
#define MOUT_CLKCMU_MIF_SWITCH 56
|
||||
#define MOUT_CLKCMU_MIF_NOCP 57
|
||||
#define MOUT_CLKCMU_MISC_NOC 58
|
||||
#define MOUT_CLKCMU_NOCL0_NOC 59
|
||||
#define MOUT_CLKCMU_NOCL1_NOC 60
|
||||
#define MOUT_CLKCMU_NOCL2_NOC 61
|
||||
#define MOUT_CLKCMU_PERIC0_NOC 62
|
||||
#define MOUT_CLKCMU_PERIC0_IP 63
|
||||
#define MOUT_CLKCMU_PERIC1_NOC 64
|
||||
#define MOUT_CLKCMU_PERIC1_IP 65
|
||||
#define MOUT_CLKCMU_SDMA_NOC 66
|
||||
#define MOUT_CLKCMU_SNW_NOC 67
|
||||
#define MOUT_CLKCMU_SSP_NOC 68
|
||||
#define MOUT_CLKCMU_TAA_NOC 69
|
||||
|
||||
/* DIV in CMU_TOP */
|
||||
#define DOUT_SHARED0_DIV1 70
|
||||
#define DOUT_SHARED0_DIV2 71
|
||||
#define DOUT_SHARED0_DIV3 72
|
||||
#define DOUT_SHARED0_DIV4 73
|
||||
#define DOUT_SHARED1_DIV1 74
|
||||
#define DOUT_SHARED1_DIV2 75
|
||||
#define DOUT_SHARED1_DIV3 76
|
||||
#define DOUT_SHARED1_DIV4 77
|
||||
#define DOUT_SHARED2_DIV1 78
|
||||
#define DOUT_SHARED2_DIV2 79
|
||||
#define DOUT_SHARED2_DIV3 80
|
||||
#define DOUT_SHARED2_DIV4 81
|
||||
#define DOUT_SHARED3_DIV1 82
|
||||
#define DOUT_SHARED3_DIV2 83
|
||||
#define DOUT_SHARED3_DIV3 84
|
||||
#define DOUT_SHARED3_DIV4 85
|
||||
#define DOUT_SHARED4_DIV1 86
|
||||
#define DOUT_SHARED4_DIV2 87
|
||||
#define DOUT_SHARED4_DIV3 88
|
||||
#define DOUT_SHARED4_DIV4 89
|
||||
#define DOUT_SHARED5_DIV1 90
|
||||
#define DOUT_SHARED5_DIV2 91
|
||||
#define DOUT_SHARED5_DIV3 92
|
||||
#define DOUT_SHARED5_DIV4 93
|
||||
#define DOUT_CLKCMU_CMU_BOOST 94
|
||||
#define DOUT_CLKCMU_ACC_NOC 95
|
||||
#define DOUT_CLKCMU_ACC_ORB 96
|
||||
#define DOUT_CLKCMU_APM_NOC 97
|
||||
#define DOUT_CLKCMU_AUD_CPU 98
|
||||
#define DOUT_CLKCMU_AUD_NOC 99
|
||||
#define DOUT_CLKCMU_CPUCL0_SWITCH 100
|
||||
#define DOUT_CLKCMU_CPUCL0_CLUSTER 101
|
||||
#define DOUT_CLKCMU_CPUCL0_DBG 102
|
||||
#define DOUT_CLKCMU_CPUCL1_SWITCH 103
|
||||
#define DOUT_CLKCMU_CPUCL1_CLUSTER 104
|
||||
#define DOUT_CLKCMU_CPUCL2_SWITCH 105
|
||||
#define DOUT_CLKCMU_CPUCL2_CLUSTER 106
|
||||
#define DOUT_CLKCMU_DNC_NOC 107
|
||||
#define DOUT_CLKCMU_DPTX_NOC 108
|
||||
#define DOUT_CLKCMU_DPTX_DPGTC 109
|
||||
#define DOUT_CLKCMU_DPTX_DPOSC 110
|
||||
#define DOUT_CLKCMU_DPUB_NOC 111
|
||||
#define DOUT_CLKCMU_DPUB_DSIM 112
|
||||
#define DOUT_CLKCMU_DPUF0_NOC 113
|
||||
#define DOUT_CLKCMU_DPUF1_NOC 114
|
||||
#define DOUT_CLKCMU_DPUF2_NOC 115
|
||||
#define DOUT_CLKCMU_DSP_NOC 116
|
||||
#define DOUT_CLKCMU_G3D_SWITCH 117
|
||||
#define DOUT_CLKCMU_G3D_NOCP 118
|
||||
#define DOUT_CLKCMU_GNPU_NOC 119
|
||||
#define DOUT_CLKCMU_HSI0_NOC 120
|
||||
#define DOUT_CLKCMU_HSI1_NOC 121
|
||||
#define DOUT_CLKCMU_HSI1_USBDRD 122
|
||||
#define DOUT_CLKCMU_HSI1_MMC_CARD 123
|
||||
#define DOUT_CLKCMU_HSI2_NOC 124
|
||||
#define DOUT_CLKCMU_HSI2_NOC_UFS 125
|
||||
#define DOUT_CLKCMU_HSI2_UFS_EMBD 126
|
||||
#define DOUT_CLKCMU_HSI2_ETHERNET 127
|
||||
#define DOUT_CLKCMU_ISP_NOC 128
|
||||
#define DOUT_CLKCMU_M2M_NOC 129
|
||||
#define DOUT_CLKCMU_M2M_JPEG 130
|
||||
#define DOUT_CLKCMU_MFC_MFC 131
|
||||
#define DOUT_CLKCMU_MFC_WFD 132
|
||||
#define DOUT_CLKCMU_MFD_NOC 133
|
||||
#define DOUT_CLKCMU_MIF_NOCP 134
|
||||
#define DOUT_CLKCMU_MISC_NOC 135
|
||||
#define DOUT_CLKCMU_NOCL0_NOC 136
|
||||
#define DOUT_CLKCMU_NOCL1_NOC 137
|
||||
#define DOUT_CLKCMU_NOCL2_NOC 138
|
||||
#define DOUT_CLKCMU_PERIC0_NOC 139
|
||||
#define DOUT_CLKCMU_PERIC0_IP 140
|
||||
#define DOUT_CLKCMU_PERIC1_NOC 141
|
||||
#define DOUT_CLKCMU_PERIC1_IP 142
|
||||
#define DOUT_CLKCMU_SDMA_NOC 143
|
||||
#define DOUT_CLKCMU_SNW_NOC 144
|
||||
#define DOUT_CLKCMU_SSP_NOC 145
|
||||
#define DOUT_CLKCMU_TAA_NOC 146
|
||||
|
||||
/* CMU_PERIC0 */
|
||||
#define CLK_MOUT_PERIC0_IP_USER 1
|
||||
#define CLK_MOUT_PERIC0_NOC_USER 2
|
||||
#define CLK_MOUT_PERIC0_USI00_USI 3
|
||||
#define CLK_MOUT_PERIC0_USI01_USI 4
|
||||
#define CLK_MOUT_PERIC0_USI02_USI 5
|
||||
#define CLK_MOUT_PERIC0_USI03_USI 6
|
||||
#define CLK_MOUT_PERIC0_USI04_USI 7
|
||||
#define CLK_MOUT_PERIC0_USI05_USI 8
|
||||
#define CLK_MOUT_PERIC0_USI06_USI 9
|
||||
#define CLK_MOUT_PERIC0_USI07_USI 10
|
||||
#define CLK_MOUT_PERIC0_USI08_USI 11
|
||||
#define CLK_MOUT_PERIC0_USI_I2C 12
|
||||
#define CLK_MOUT_PERIC0_I3C 13
|
||||
|
||||
#define CLK_DOUT_PERIC0_USI00_USI 14
|
||||
#define CLK_DOUT_PERIC0_USI01_USI 15
|
||||
#define CLK_DOUT_PERIC0_USI02_USI 16
|
||||
#define CLK_DOUT_PERIC0_USI03_USI 17
|
||||
#define CLK_DOUT_PERIC0_USI04_USI 18
|
||||
#define CLK_DOUT_PERIC0_USI05_USI 19
|
||||
#define CLK_DOUT_PERIC0_USI06_USI 20
|
||||
#define CLK_DOUT_PERIC0_USI07_USI 21
|
||||
#define CLK_DOUT_PERIC0_USI08_USI 22
|
||||
#define CLK_DOUT_PERIC0_USI_I2C 23
|
||||
#define CLK_DOUT_PERIC0_I3C 24
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV920_H */
|
||||
Reference in New Issue
Block a user