mirrors/linux
2
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2026-05-22 09:45:08 -04:00
Code Issues Packages Projects Releases Wiki Activity

Merge tag 'renesas-dts-for-v6.18-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt

Browse Source 
Renesas DTS updates for v6.18

  - Add initial support for the RZ/T2H (R9A09G077) and RZ/N2H
    (R9A09G087) SoCs and their evaluation boards,
  - Add SPI support for the RZ/V2H SoC,
  - Add DMAC and I3C support for the RZ/G3E SoC,
  - Add I3C support for the RZ/G3S SoCs,
  - Miscellaneous fixes and improvements.

* tag 'renesas-dts-for-v6.18-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (31 commits)
  arm64: dts: renesas: Minor whitespace cleanup
  arm64: dts: renesas: sparrow-hawk: Set VDDQ18_25_AVB voltage on EVTB1
  arm64: dts: renesas: sparrow-hawk: Invert microSD voltage selector on EVTB1
  arm64: dts: renesas: r9a09g077m44-rzt2h-evk: Enable I2C0 and I2C1 support
  arm64: dts: renesas: r9a09g077: Add pinctrl node
  arm64: dts: renesas: r9a09g087: Add DT nodes for SCI channels 1-5
  arm64: dts: renesas: r9a09g077: Add DT nodes for SCI channels 1-5
  arm64: dts: renesas: r9a09g047: Add I3C node
  arm64: dts: renesas: r9a08g045: Add I3C node
  arm64: dts: renesas: sparrow-hawk: Update thermal trip points
  arm64: dts: renesas: rzg2: Increase CANFD clock rates
  arm64: dts: renesas: rcar-gen3: Increase CANFD clock rates
  ARM: dts: renesas: porter: Fix CAN pin group
  ARM: dts: renesas: r7s72100: Add boot phase tags
  arm64: dts: renesas: sparrow-hawk: Describe generic SPI NOR support
  arm64: dts: renesas: rzg2lc-smarc: Disable CAN-FD channel0
  arm64: dts: renesas: r9a09g047: Add DMAC nodes
  arm64: dts: renesas: r9a09g057h48-kakip: Fix misplaced article
  arm64: dts: renesas: r9a09g087: Add SDHI nodes
  arm64: dts: renesas: r9a09g077: Add SDHI nodes
  ...

Link: https://lore.kernel.org/r/cover.1756468048.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2025-09-01 12:00:46 +02:00
parent 58770c8759 115b557b6f
commit 4e501327bf
37 changed files with 1390 additions and 37 deletions
Download Patch File Download Diff File Expand all files Collapse all files

172
Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml Normal file
View File

@@ -0,0 +1,172 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/renesas,r9a09g077-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas RZ/T2H and RZ/N2H Pin and GPIO controller
maintainers:
- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
description:
The Renesas RZ/T2H and RZ/N2H SoCs feature a combined Pin and GPIO controller.
Pin multiplexing and GPIO configuration are performed on a per-pin basis.
Each port supports up to 8 pins, each configurable for either GPIO (port mode)
or alternate function mode. Each pin supports function mode values ranging from
0x0 to 0x2A, allowing selection from up to 43 different functions.
properties:
compatible:
enum:
- renesas,r9a09g077-pinctrl # RZ/T2H
- renesas,r9a09g087-pinctrl # RZ/N2H
reg:
minItems: 1
items:
- description: Non-safety I/O Port base
- description: Safety I/O Port safety region base
- description: Safety I/O Port Non-safety region base
reg-names:
minItems: 1
items:
- const: nsr
- const: srs
- const: srn
gpio-controller: true
'#gpio-cells':
const: 2
description:
The first cell contains the global GPIO port index, constructed using the
RZT2H_GPIO() helper macro from <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>
(e.g. "RZT2H_GPIO(3, 0)" for P03_0). The second cell represents the consumer
flag. Use the macros defined in include/dt-bindings/gpio/gpio.h.
gpio-ranges:
maxItems: 1
clocks:
maxItems: 1
power-domains:
maxItems: 1
definitions:
renesas-rzt2h-n2h-pins-node:
type: object
allOf:
- $ref: pincfg-node.yaml#
- $ref: pinmux-node.yaml#
properties:
pinmux:
description:
Values are constructed from I/O port number, pin number, and
alternate function configuration number using the RZT2H_PORT_PINMUX()
helper macro from <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>.
pins: true
phandle: true
input: true
input-enable: true
output-enable: true
oneOf:
- required: [pinmux]
- required: [pins]
additionalProperties: false
patternProperties:
# Grouping nodes: allow multiple "-pins" subnodes within a "-group"
'.*-group$':
type: object
description:
Pin controller client devices can organize pin configuration entries into
grouping nodes ending in "-group". These group nodes may contain multiple
child nodes each ending in "-pins" to configure distinct sets of pins.
additionalProperties: false
patternProperties:
'-pins$':
$ref: '#/definitions/renesas-rzt2h-n2h-pins-node'
# Standalone "-pins" nodes under client devices or groups
'-pins$':
$ref: '#/definitions/renesas-rzt2h-n2h-pins-node'
'-hog$':
type: object
description: GPIO hog node
properties:
gpio-hog: true
gpios: true
input: true
output-high: true
output-low: true
line-name: true
required:
- gpio-hog
- gpios
additionalProperties: false
allOf:
- $ref: pinctrl.yaml#
required:
- compatible
- reg
- reg-names
- gpio-controller
- '#gpio-cells'
- gpio-ranges
- clocks
- power-domains
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
#include <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>
pinctrl@802c0000 {
compatible = "renesas,r9a09g077-pinctrl";
reg = <0x802c0000 0x2000>,
<0x812c0000 0x2000>,
<0x802b0000 0x2000>;
reg-names = "nsr", "srs", "srn";
clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 0 288>;
power-domains = <&cpg>;
serial0-pins {
pinmux = <RZT2H_PORT_PINMUX(38, 0, 1)>, /* Tx */
<RZT2H_PORT_PINMUX(38, 1, 1)>; /* Rx */
};
sd1-pwr-en-hog {
gpio-hog;
gpios = <RZT2H_GPIO(39, 2) 0>;
output-high;
line-name = "sd1_pwr_en";
};
i2c0-pins {
pins = "RIIC0_SDA", "RIIC0_SCL";
input-enable;
};
sd0-sd-group {
ctrl-pins {
pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>, /* SD0_CLK */
<RZT2H_PORT_PINMUX(12, 1, 0x29)>; /* SD0_CMD */
};
data-pins {
pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>, /* SD0_CLK */
<RZT2H_PORT_PINMUX(12, 1, 0x29)>; /* SD0_CMD */
};
};
};

4
arch/arm/boot/dts/renesas/r7s72100-genmai.dts
View File

@@ -203,6 +203,7 @@ &mtu2 {
};
&ostm0 {
bootph-all;
status = "okay";
};
@@ -258,6 +259,7 @@ mmcif_pins: mmcif {
};
scif2_pins: serial2 {
bootph-all;
/* P3_0 as TxD2; P3_2 as RxD2 */
pinmux = <RZA1_PINMUX(3, 0, 6)>, <RZA1_PINMUX(3, 2, 4)>;
};
@@ -286,7 +288,7 @@ &rtc {
&scif2 {
pinctrl-names = "default";
pinctrl-0 = <&scif2_pins>;
bootph-all;
status = "okay";
};

4
arch/arm/boot/dts/renesas/r7s72100-gr-peach.dts
View File

@@ -59,6 +59,7 @@ led1 {
&pinctrl {
scif2_pins: serial2 {
bootph-all;
/* P6_2 as RxD2; P6_3 as TxD2 */
pinmux = <RZA1_PINMUX(6, 2, 7)>, <RZA1_PINMUX(6, 3, 7)>;
};
@@ -99,6 +100,7 @@ &mtu2 {
};
&ostm0 {
bootph-all;
status = "okay";
};
@@ -109,7 +111,7 @@ &ostm1 {
&scif2 {
pinctrl-names = "default";
pinctrl-0 = <&scif2_pins>;
bootph-all;
status = "okay";
};

3
arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts
View File

@@ -199,6 +199,7 @@ keyboard_pins: keyboard {
/* Serial Console */
scif2_pins: serial2 {
bootph-all;
pinmux = <RZA1_PINMUX(3, 0, 6)>, /* TxD2 */
<RZA1_PINMUX(3, 2, 4)>; /* RxD2 */
};
@@ -264,6 +265,7 @@ &sdhi1 {
};
&ostm0 {
bootph-all;
status = "okay";
};
@@ -278,6 +280,7 @@ &rtc {
&scif2 {
pinctrl-names = "default";
pinctrl-0 = <&scif2_pins>;
bootph-all;
status = "okay";
};

3
arch/arm/boot/dts/renesas/r7s72100.dtsi
View File

@@ -41,6 +41,7 @@ bsc: bus {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x18000000>;
bootph-all;
};
cpus {
@@ -107,6 +108,7 @@ soc {
#address-cells = <1>;
#size-cells = <1>;
ranges;
bootph-all;
L2: cache-controller@3ffff000 {
compatible = "arm,pl310-cache";
@@ -557,6 +559,7 @@ R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11
pinctrl: pinctrl@fcfe3000 {
compatible = "renesas,r7s72100-ports";
bootph-all;
reg = <0xfcfe3000 0x4230>;

2
arch/arm/boot/dts/renesas/r8a7791-porter.dts
View File

@@ -289,7 +289,7 @@ vin0_pins: vin0 {
};
can0_pins: can0 {
groups = "can0_data";
groups = "can0_data_b";
function = "can0";
};

4
arch/arm64/boot/dts/renesas/Makefile
View File

@@ -180,5 +180,9 @@ r9a09g057h44-rzv2h-evk-cn15-sd-dtbs := r9a09g057h44-rzv2h-evk.dtb rzv2-evk-cn15-
dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h44-rzv2h-evk-cn15-sd.dtb
dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h48-kakip.dtb
dtb-$(CONFIG_ARCH_R9A09G077) += r9a09g077m44-rzt2h-evk.dtb
dtb-$(CONFIG_ARCH_R9A09G087) += r9a09g087m44-rzn2h-evk.dtb
dtb-$(CONFIG_ARCH_RCAR_GEN3) += draak-ebisu-panel-aa104xd12.dtbo
dtb-$(CONFIG_ARCH_RCAR_GEN3) += salvator-panel-aa104xd12.dtbo

2
arch/arm64/boot/dts/renesas/r8a774a1.dtsi
View File

@@ -1186,7 +1186,7 @@ canfd: can@e66c0000 {
<&can_clk>;
clock-names = "fck", "canfd", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>;
assigned-clock-rates = <40000000>;
assigned-clock-rates = <80000000>;
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 914>;
status = "disabled";

2
arch/arm64/boot/dts/renesas/r8a774b1.dtsi
View File

@@ -1070,7 +1070,7 @@ canfd: can@e66c0000 {
<&can_clk>;
clock-names = "fck", "canfd", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>;
assigned-clock-rates = <40000000>;
assigned-clock-rates = <80000000>;
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
resets = <&cpg 914>;
status = "disabled";

2
arch/arm64/boot/dts/renesas/r8a774c0.dtsi
View File

@@ -1029,7 +1029,7 @@ canfd: can@e66c0000 {
<&can_clk>;
clock-names = "fck", "canfd", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>;
assigned-clock-rates = <40000000>;
assigned-clock-rates = <80000000>;
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
resets = <&cpg 914>;
status = "disabled";

2
arch/arm64/boot/dts/renesas/r8a774e1.dtsi
View File

@@ -1298,7 +1298,7 @@ canfd: can@e66c0000 {
<&can_clk>;
clock-names = "fck", "canfd", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>;
assigned-clock-rates = <40000000>;
assigned-clock-rates = <80000000>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 914>;
status = "disabled";

2
arch/arm64/boot/dts/renesas/r8a77951.dtsi
View File

@@ -1373,7 +1373,7 @@ canfd: can@e66c0000 {
<&can_clk>;
clock-names = "fck", "canfd", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
assigned-clock-rates = <40000000>;
assigned-clock-rates = <80000000>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 914>;
status = "disabled";

2
arch/arm64/boot/dts/renesas/r8a77960.dtsi
View File

@@ -1245,7 +1245,7 @@ canfd: can@e66c0000 {
<&can_clk>;
clock-names = "fck", "canfd", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
assigned-clock-rates = <40000000>;
assigned-clock-rates = <80000000>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 914>;
status = "disabled";

2
arch/arm64/boot/dts/renesas/r8a77961.dtsi
View File

@@ -1245,7 +1245,7 @@ canfd: can@e66c0000 {
<&can_clk>;
clock-names = "fck", "canfd", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A77961_CLK_CANFD>;
assigned-clock-rates = <40000000>;
assigned-clock-rates = <80000000>;
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
resets = <&cpg 914>;
status = "disabled";

2
arch/arm64/boot/dts/renesas/r8a77965.dtsi
View File

@@ -1108,7 +1108,7 @@ canfd: can@e66c0000 {
<&can_clk>;
clock-names = "fck", "canfd", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>;
assigned-clock-rates = <40000000>;
assigned-clock-rates = <80000000>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 914>;
status = "disabled";

2
arch/arm64/boot/dts/renesas/r8a77970.dtsi
View File

@@ -568,7 +568,7 @@ canfd: can@e66c0000 {
<&can_clk>;
clock-names = "fck", "canfd", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A77970_CLK_CANFD>;
assigned-clock-rates = <40000000>;
assigned-clock-rates = <80000000>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 914>;
status = "disabled";

2
arch/arm64/boot/dts/renesas/r8a77980.dtsi
View File

@@ -621,7 +621,7 @@ canfd: can@e66c0000 {
<&can_clk>;
clock-names = "fck", "canfd", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>;
assigned-clock-rates = <40000000>;
assigned-clock-rates = <80000000>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 914>;
status = "disabled";

2
arch/arm64/boot/dts/renesas/r8a77990.dtsi
View File

@@ -1061,7 +1061,7 @@ canfd: can@e66c0000 {
<&can_clk>;
clock-names = "fck", "canfd", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>;
assigned-clock-rates = <40000000>;
assigned-clock-rates = <80000000>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 914>;
status = "disabled";

149
arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts
View File

@@ -38,6 +38,7 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/thermal/thermal.h>
#include "r8a779g3.dtsi"
@@ -185,7 +186,42 @@ vcc_sdhi: regulator-vcc-sdhi {
regulator-max-microvolt = <3300000>;
gpios = <&gpio8 13 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 0>, <1800000 1>;
states = <1800000 0>, <3300000 1>;
};
};
/* Use thermal-idle cooling for all SoC cores */
&a76_0 {
#cooling-cells = <2>;
a76_0_thermal_idle: thermal-idle {
#cooling-cells = <2>;
duration-us = <10000>;
exit-latency-us = <500>;
};
};
&a76_1 {
a76_1_thermal_idle: thermal-idle {
#cooling-cells = <2>;
duration-us = <10000>;
exit-latency-us = <500>;
};
};
&a76_2 {
a76_2_thermal_idle: thermal-idle {
#cooling-cells = <2>;
duration-us = <10000>;
exit-latency-us = <500>;
};
};
&a76_3 {
a76_3_thermal_idle: thermal-idle {
#cooling-cells = <2>;
duration-us = <10000>;
exit-latency-us = <500>;
};
};
@@ -556,6 +592,10 @@ pins-mii {
drive-strength = <21>;
};
pins-vddq18-25-avb {
pins = "PIN_VDDQ_AVB0", "PIN_VDDQ_AVB1", "PIN_VDDQ_AVB2", "PIN_VDDQ_TSN0";
power-source = <1800>;
};
};
/* Page 28 / CANFD_IF */
@@ -756,7 +796,11 @@ &rpc {
status = "okay";
flash@0 {
compatible = "spansion,s25fs512s", "jedec,spi-nor";
/*
* EVTA1 is populated with Spansion S25FS512S
* EVTB1 is populated with Winbond W77Q51NW
*/
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
spi-rx-bus-width = <4>;
@@ -797,3 +841,104 @@ &rwdt {
&scif_clk { /* X12 */
clock-frequency = <24000000>;
};
/* THS sensors in SoC, critical temperature trip point is 100C */
&sensor1_crit {
temperature = <100000>;
};
&sensor2_crit {
temperature = <100000>;
};
&sensor3_crit {
temperature = <100000>;
};
&sensor4_crit {
temperature = <100000>;
};
/* THS sensor in SoC near CA76 cores does more progressive cooling. */
&sensor_thermal_ca76 {
critical-action = "shutdown";
cooling-maps {
/*
* The cooling-device minimum and maximum parameters inversely
* match opp-table-0 {} node entries in r8a779g0.dtsi, in other
* words, 0 refers to 1.8 GHz OPP and 4 refers to 500 MHz OPP.
* This is because they refer to cooling levels, where maximum
* cooling level happens at 500 MHz OPP, when the CPU core is
* running slowly and therefore generates least heat.
*/
map0 {
/* At 68C, inhibit 1.7 GHz and 1.8 GHz modes */
trip = <&sensor3_passive_low>;
cooling-device = <&a76_0 2 4>;
contribution = <128>;
};
map1 {
/* At 72C, inhibit 1.5 GHz mode */
trip = <&sensor3_passive_mid>;
cooling-device = <&a76_0 3 4>;
contribution = <256>;
};
map2 {
/* At 76C, start injecting idle states 0..80% of time */
trip = <&sensor3_passive_hi>;
cooling-device = <&a76_0_thermal_idle 0 80>,
<&a76_1_thermal_idle 0 80>,
<&a76_2_thermal_idle 0 80>,
<&a76_3_thermal_idle 0 80>;
contribution = <512>;
};
map3 {
/* At 80C, inhibit 1.0 GHz mode */
trip = <&sensor3_passive_crit>;
cooling-device = <&a76_0 4 4>;
contribution = <1024>;
};
};
trips {
sensor3_passive_low: sensor3-passive-low {
temperature = <68000>;
hysteresis = <2000>;
type = "passive";
};
sensor3_passive_mid: sensor3-passive-mid {
temperature = <72000>;
hysteresis = <2000>;
type = "passive";
};
sensor3_passive_hi: sensor3-passive-hi {
temperature = <76000>;
hysteresis = <2000>;
type = "passive";
};
sensor3_passive_crit: sensor3-passive-crit {
temperature = <80000>;
hysteresis = <2000>;
type = "passive";
};
};
};
&sensor_thermal_cnn {
critical-action = "shutdown";
};
&sensor_thermal_cr52 {
critical-action = "shutdown";
};
&sensor_thermal_ddr1 {
critical-action = "shutdown";
};

36
arch/arm64/boot/dts/renesas/r9a08g045.dtsi
View File

@@ -272,6 +272,42 @@ channel@8 {
};
};
i3c: i3c@1005b000 {
compatible = "renesas,r9a08g045-i3c";
reg = <0 0x1005b000 0 0x1000>;
clocks = <&cpg CPG_MOD R9A08G045_I3C_PCLK>,
<&cpg CPG_MOD R9A08G045_I3C_TCLK>;
clock-names = "pclk", "tclk";
interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 294 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 295 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ierr", "terr", "abort", "resp",
"cmd", "ibi", "rx", "tx", "rcv",
"st", "sp", "tend", "nack", "al",
"tmo", "wu", "exit";
resets = <&cpg R9A08G045_I3C_PRESETN>,
<&cpg R9A08G045_I3C_TRESETN>;
reset-names = "presetn", "tresetn";
power-domains = <&cpg>;
#address-cells = <3>;
#size-cells = <0>;
status = "disabled";
};
vbattb: clock-controller@1005c000 {
compatible = "renesas,r9a08g045-vbattb";
reg = <0 0x1005c000 0 0x1000>;

205
arch/arm64/boot/dts/renesas/r9a09g047.dtsi
View File

@@ -301,6 +301,176 @@ xspi: spi@11030000 {
status = "disabled";
};
dmac0: dma-controller@11400000 {
compatible = "renesas,r9a09g047-dmac",
"renesas,r9a09g057-dmac";
reg = <0 0x11400000 0 0x10000>;
interrupts = <GIC_SPI 499 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 89 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 90 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 91 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 92 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 93 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 94 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 95 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 96 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 97 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 98 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 99 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 101 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 102 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 103 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 104 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD 0x0>;
power-domains = <&cpg>;
resets = <&cpg 0x31>;
#dma-cells = <1>;
dma-channels = <16>;
renesas,icu = <&icu 4>;
};
dmac1: dma-controller@14830000 {
compatible = "renesas,r9a09g047-dmac",
"renesas,r9a09g057-dmac";
reg = <0 0x14830000 0 0x10000>;
interrupts = <GIC_SPI 495 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 25 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 29 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 40 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD 0x1>;
power-domains = <&cpg>;
resets = <&cpg 0x32>;
#dma-cells = <1>;
dma-channels = <16>;
renesas,icu = <&icu 0>;
};
dmac2: dma-controller@14840000 {
compatible = "renesas,r9a09g047-dmac",
"renesas,r9a09g057-dmac";
reg = <0 0x14840000 0 0x10000>;
interrupts = <GIC_SPI 496 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 42 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 43 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 48 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 49 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 50 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 53 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 54 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 56 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD 0x2>;
power-domains = <&cpg>;
resets = <&cpg 0x33>;
#dma-cells = <1>;
dma-channels = <16>;
renesas,icu = <&icu 1>;
};
dmac3: dma-controller@12000000 {
compatible = "renesas,r9a09g047-dmac",
"renesas,r9a09g057-dmac";
reg = <0 0x12000000 0 0x10000>;
interrupts = <GIC_SPI 497 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 57 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 58 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 60 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 64 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 65 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 66 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 67 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 68 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 69 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 70 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 71 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD 0x3>;
power-domains = <&cpg>;
resets = <&cpg 0x34>;
#dma-cells = <1>;
dma-channels = <16>;
renesas,icu = <&icu 2>;
};
dmac4: dma-controller@12010000 {
compatible = "renesas,r9a09g047-dmac",
"renesas,r9a09g057-dmac";
reg = <0 0x12010000 0 0x10000>;
interrupts = <GIC_SPI 498 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 73 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 76 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 81 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 82 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 83 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 84 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 85 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 86 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 87 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD 0x4>;
power-domains = <&cpg>;
resets = <&cpg 0x35>;
#dma-cells = <1>;
dma-channels = <16>;
renesas,icu = <&icu 3>;
};
scif0: serial@11c01400 {
compatible = "renesas,scif-r9a09g047", "renesas,scif-r9a09g057";
reg = <0 0x11c01400 0 0x400>;
@@ -322,6 +492,41 @@ scif0: serial@11c01400 {
status = "disabled";
};
i3c: i3c@12400000 {
compatible = "renesas,r9a09g047-i3c";
reg = <0 0x12400000 0 0x10000>;
clocks = <&cpg CPG_MOD 0x91>,
<&cpg CPG_MOD 0x92>,
<&cpg CPG_MOD 0x90>;
clock-names = "pclk", "tclk", "pclkrw";
interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 677 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 678 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 679 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 680 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 681 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 682 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ierr", "terr", "abort", "resp",
"cmd", "ibi", "rx", "tx", "rcv",
"st", "sp", "tend", "nack", "al",
"tmo", "wu";
resets = <&cpg 0x96>, <&cpg 0x97>;
reset-names = "presetn", "tresetn";
power-domains = <&cpg>;
#address-cells = <3>;
#size-cells = <0>;
status = "disabled";
};
canfd: can@12440000 {
compatible = "renesas,r9a09g047-canfd";
reg = <0 0x12440000 0 0x40000>;

16
arch/arm64/boot/dts/renesas/r9a09g056.dtsi
View File

@@ -735,10 +735,10 @@ eth0: ethernet@15c30000 {
"rx-queue-0", "rx-queue-1", "rx-queue-2",
"rx-queue-3", "tx-queue-0", "tx-queue-1",
"tx-queue-2", "tx-queue-3";
clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>,
<&cpg CPG_CORE R9A09G056_GBETH_0_CLK_PTP_REF_I>,
<&cpg CPG_MOD 0xb8>, <&cpg CPG_MOD 0xb9>,
<&cpg CPG_MOD 0xba>, <&cpg CPG_MOD 0xbb>;
clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>,
<&cpg CPG_CORE R9A09G056_GBETH_0_CLK_PTP_REF_I>,
<&cpg CPG_MOD 0xb8>, <&cpg CPG_MOD 0xb9>,
<&cpg CPG_MOD 0xba>, <&cpg CPG_MOD 0xbb>;
clock-names = "stmmaceth", "pclk", "ptp_ref",
"tx", "rx", "tx-180", "rx-180";
resets = <&cpg 0xb0>;
@@ -836,10 +836,10 @@ eth1: ethernet@15c40000 {
"rx-queue-0", "rx-queue-1", "rx-queue-2",
"rx-queue-3", "tx-queue-0", "tx-queue-1",
"tx-queue-2", "tx-queue-3";
clocks = <&cpg CPG_MOD 0xc3>, <&cpg CPG_MOD 0xc2>,
<&cpg CPG_CORE R9A09G056_GBETH_1_CLK_PTP_REF_I>,
<&cpg CPG_MOD 0xbe>, <&cpg CPG_MOD 0xbf>,
<&cpg CPG_MOD 0xc0>, <&cpg CPG_MOD 0xc1>;
clocks = <&cpg CPG_MOD 0xc3>, <&cpg CPG_MOD 0xc2>,
<&cpg CPG_CORE R9A09G056_GBETH_1_CLK_PTP_REF_I>,
<&cpg CPG_MOD 0xbe>, <&cpg CPG_MOD 0xbf>,
<&cpg CPG_MOD 0xc0>, <&cpg CPG_MOD 0xc1>;
clock-names = "stmmaceth", "pclk", "ptp_ref",
"tx", "rx", "tx-180", "rx-180";
resets = <&cpg 0xb1>;

2
arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts
View File

@@ -334,7 +334,7 @@ sd1-dat-cmd {
usb20_pins: usb20 {
ovc {
pinmux = <RZV2N_PORT_PINMUX(9, 6, 14)>; /* OVC */
pinmux = <RZV2N_PORT_PINMUX(9, 6, 14)>; /* OVC */
};
vbus {

79
arch/arm64/boot/dts/renesas/r9a09g057.dtsi
View File

@@ -607,6 +607,69 @@ scif: serial@11c01400 {
status = "disabled";
};
rspi0: spi@12800000 {
compatible = "renesas,r9a09g057-rspi";
reg = <0x0 0x12800000 0x0 0x400>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 500 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 501 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "idle", "error", "end", "rx", "tx";
clocks = <&cpg CPG_MOD 0x54>,
<&cpg CPG_MOD 0x55>,
<&cpg CPG_MOD 0x56>;
clock-names = "pclk", "pclk_sfr", "tclk";
resets = <&cpg 0x7b>, <&cpg 0x7c>;
reset-names = "presetn", "tresetn";
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
rspi1: spi@12800400 {
compatible = "renesas,r9a09g057-rspi";
reg = <0x0 0x12800400 0x0 0x400>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 110 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 502 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 503 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "idle", "error", "end", "rx", "tx";
clocks = <&cpg CPG_MOD 0x57>,
<&cpg CPG_MOD 0x58>,
<&cpg CPG_MOD 0x59>;
clock-names = "pclk", "pclk_sfr", "tclk";
resets = <&cpg 0x7d>, <&cpg 0x7e>;
reset-names = "presetn", "tresetn";
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
rspi2: spi@12800800 {
compatible = "renesas,r9a09g057-rspi";
reg = <0x0 0x12800800 0x0 0x400>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 113 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 504 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 505 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "idle", "error", "end", "rx", "tx";
clocks = <&cpg CPG_MOD 0x5a>,
<&cpg CPG_MOD 0x5b>,
<&cpg CPG_MOD 0x5c>;
clock-names = "pclk", "pclk_sfr", "tclk";
resets = <&cpg 0x7f>, <&cpg 0x80>;
reset-names = "presetn", "tresetn";
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c0: i2c@14400400 {
compatible = "renesas,riic-r9a09g057";
reg = <0 0x14400400 0 0x400>;
@@ -1020,10 +1083,10 @@ eth0: ethernet@15c30000 {
"rx-queue-0", "rx-queue-1", "rx-queue-2",
"rx-queue-3", "tx-queue-0", "tx-queue-1",
"tx-queue-2", "tx-queue-3";
clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>,
<&cpg CPG_CORE R9A09G057_GBETH_0_CLK_PTP_REF_I>,
<&cpg CPG_MOD 0xb8>, <&cpg CPG_MOD 0xb9>,
<&cpg CPG_MOD 0xba>, <&cpg CPG_MOD 0xbb>;
clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>,
<&cpg CPG_CORE R9A09G057_GBETH_0_CLK_PTP_REF_I>,
<&cpg CPG_MOD 0xb8>, <&cpg CPG_MOD 0xb9>,
<&cpg CPG_MOD 0xba>, <&cpg CPG_MOD 0xbb>;
clock-names = "stmmaceth", "pclk", "ptp_ref",
"tx", "rx", "tx-180", "rx-180";
resets = <&cpg 0xb0>;
@@ -1121,10 +1184,10 @@ eth1: ethernet@15c40000 {
"rx-queue-0", "rx-queue-1", "rx-queue-2",
"rx-queue-3", "tx-queue-0", "tx-queue-1",
"tx-queue-2", "tx-queue-3";
clocks = <&cpg CPG_MOD 0xc3>, <&cpg CPG_MOD 0xc2>,
<&cpg CPG_CORE R9A09G057_GBETH_1_CLK_PTP_REF_I>,
<&cpg CPG_MOD 0xbe>, <&cpg CPG_MOD 0xbf>,
<&cpg CPG_MOD 0xc0>, <&cpg CPG_MOD 0xc1>;
clocks = <&cpg CPG_MOD 0xc3>, <&cpg CPG_MOD 0xc2>,
<&cpg CPG_CORE R9A09G057_GBETH_1_CLK_PTP_REF_I>,
<&cpg CPG_MOD 0xbe>, <&cpg CPG_MOD 0xbf>,
<&cpg CPG_MOD 0xc0>, <&cpg CPG_MOD 0xc1>;
clock-names = "stmmaceth", "pclk", "ptp_ref",
"tx", "rx", "tx-180", "rx-180";
resets = <&cpg 0xb1>;

2
arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
View File

@@ -353,7 +353,7 @@ sd1_cd {
usb20_pins: usb20 {
ovc {
pinmux = <RZV2H_PORT_PINMUX(9, 6, 14)>; /* OVC */
pinmux = <RZV2H_PORT_PINMUX(9, 6, 14)>; /* OVC */
};
vbus {

4
arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for Yuridenki-Shokai the Kakip board
* Device Tree Source for the Yuridenki-Shokai Kakip board
*
* Copyright (C) 2024 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*/
@@ -84,7 +84,7 @@ &ostm7 {
&pinctrl {
scif_pins: scif {
pins = "SCIF_RXD", "SCIF_TXD";
pins = "SCIF_RXD", "SCIF_TXD";
};
sd0-pwr-en-hog {

292
arch/arm64/boot/dts/renesas/r9a09g077.dtsi Normal file
View File

@@ -0,0 +1,292 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/T2H SoC
*
* Copyright (C) 2025 Renesas Electronics Corp.
*/
#include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "renesas,r9a09g077";
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a55";
reg = <0>;
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
};
cpu1: cpu@100 {
compatible = "arm,cortex-a55";
reg = <0x100>;
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
};
cpu2: cpu@200 {
compatible = "arm,cortex-a55";
reg = <0x200>;
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
};
cpu3: cpu@300 {
compatible = "arm,cortex-a55";
reg = <0x300>;
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
};
L3_CA55: cache-controller-0 {
compatible = "cache";
cache-unified;
cache-size = <0x100000>;
cache-level = <3>;
};
};
extal_clk: extal {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
};
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
sci0: serial@80005000 {
compatible = "renesas,r9a09g077-rsci";
reg = <0 0x80005000 0 0x400>;
interrupts = <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 591 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 592 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi", "tei";
clocks = <&cpg CPG_MOD 8>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
clock-names = "operation", "bus";
power-domains = <&cpg>;
status = "disabled";
};
sci1: serial@80005400 {
compatible = "renesas,r9a09g077-rsci";
reg = <0 0x80005400 0 0x400>;
interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 595 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 596 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi", "tei";
clocks = <&cpg CPG_MOD 9>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
clock-names = "operation", "bus";
power-domains = <&cpg>;
status = "disabled";
};
sci2: serial@80005800 {
compatible = "renesas,r9a09g077-rsci";
reg = <0 0x80005800 0 0x400>;
interrupts = <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 599 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 600 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi", "tei";
clocks = <&cpg CPG_MOD 10>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
clock-names = "operation", "bus";
power-domains = <&cpg>;
status = "disabled";
};
sci3: serial@80005c00 {
compatible = "renesas,r9a09g077-rsci";
reg = <0 0x80005c00 0 0x400>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 603 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 604 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi", "tei";
clocks = <&cpg CPG_MOD 11>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
clock-names = "operation", "bus";
power-domains = <&cpg>;
status = "disabled";
};
sci4: serial@80006000 {
compatible = "renesas,r9a09g077-rsci";
reg = <0 0x80006000 0 0x400>;
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 607 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 608 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi", "tei";
clocks = <&cpg CPG_MOD 12>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
clock-names = "operation", "bus";
power-domains = <&cpg>;
status = "disabled";
};
sci5: serial@81005000 {
compatible = "renesas,r9a09g077-rsci";
reg = <0 0x81005000 0 0x400>;
interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 611 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 612 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi", "tei";
clocks = <&cpg CPG_MOD 600>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
clock-names = "operation", "bus";
power-domains = <&cpg>;
status = "disabled";
};
i2c0: i2c@80088000 {
compatible = "renesas,riic-r9a09g077";
reg = <0 0x80088000 0 0x400>;
interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 615 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 616 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 617 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eei", "rxi", "txi", "tei";
clocks = <&cpg CPG_MOD 100>;
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@80088400 {
compatible = "renesas,riic-r9a09g077";
reg = <0 0x80088400 0 0x400>;
interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 619 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 620 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 621 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eei", "rxi", "txi", "tei";
clocks = <&cpg CPG_MOD 101>;
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@81008000 {
compatible = "renesas,riic-r9a09g077";
reg = <0 0x81008000 0 0x400>;
interrupts = <GIC_SPI 622 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 623 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 624 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eei", "rxi", "txi", "tei";
clocks = <&cpg CPG_MOD 601>;
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
cpg: clock-controller@80280000 {
compatible = "renesas,r9a09g077-cpg-mssr";
reg = <0 0x80280000 0 0x1000>,
<0 0x81280000 0 0x9000>;
clocks = <&extal_clk>;
clock-names = "extal";
#clock-cells = <2>;
#reset-cells = <1>;
#power-domain-cells = <0>;
};
pinctrl: pinctrl@802c0000 {
compatible = "renesas,r9a09g077-pinctrl";
reg = <0 0x802c0000 0 0x10000>,
<0 0x812c0000 0 0x10000>,
<0 0x802b0000 0 0x10000>;
reg-names = "nsr", "srs", "srn";
clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 0 288>;
power-domains = <&cpg>;
};
gic: interrupt-controller@83000000 {
compatible = "arm,gic-v3";
reg = <0x0 0x83000000 0 0x40000>,
<0x0 0x83040000 0 0x160000>;
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
sdhi0: mmc@92080000 {
compatible = "renesas,sdhi-r9a09g077",
"renesas,sdhi-r9a09g057";
reg = <0x0 0x92080000 0 0x10000>;
interrupts = <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 1212>,
<&cpg CPG_CORE R9A09G077_SDHI_CLKHS>;
clock-names = "aclk", "clkh";
power-domains = <&cpg>;
status = "disabled";
sdhi0_vqmmc: vqmmc-regulator {
regulator-name = "SDHI0-VQMMC";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
status = "disabled";
};
};
sdhi1: mmc@92090000 {
compatible = "renesas,sdhi-r9a09g077",
"renesas,sdhi-r9a09g057";
reg = <0x0 0x92090000 0 0x10000>;
interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 1213>,
<&cpg CPG_CORE R9A09G077_SDHI_CLKHS>;
clock-names = "aclk", "clkh";
power-domains = <&cpg>;
status = "disabled";
sdhi1_vqmmc: vqmmc-regulator {
regulator-name = "SDHI1-VQMMC";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
status = "disabled";
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
};
};

52
arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts Normal file
View File

@@ -0,0 +1,52 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/T2H EVK board
*
* Copyright (C) 2025 Renesas Electronics Corp.
*/
/dts-v1/;
#include <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>
#include "r9a09g077m44.dtsi"
#include "rzt2h-n2h-evk-common.dtsi"
/ {
model = "Renesas RZ/T2H EVK Board based on r9a09g077m44";
compatible = "renesas,rzt2h-evk", "renesas,r9a09g077m44", "renesas,r9a09g077";
};
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
clock-frequency = <400000>;
status = "okay";
};
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
clock-frequency = <400000>;
status = "okay";
};
&pinctrl {
/*
* I2C0 Pin Configuration:
* ------------------------
* Signal | Pin | SW6
* -------|---------|--------------
* SCL | P23_3 | 7: ON, 8: OFF
* SDA | P23_4 | 9: ON, 10: OFF
*/
i2c0_pins: i2c0-pins {
pinmux = <RZT2H_PORT_PINMUX(23, 3, 0x17)>,
<RZT2H_PORT_PINMUX(23, 4, 0x17)>;
};
i2c1_pins: i2c1-pins {
pinmux = <RZT2H_PORT_PINMUX(5, 0, 0x17)>, /* SDA */
<RZT2H_PORT_PINMUX(4, 7, 0x17)>; /* SCL */
};
};

13
arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi Normal file
View File

@@ -0,0 +1,13 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/T2H 4-core SoC
*
* Copyright (C) 2025 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r9a09g077.dtsi"
/ {
compatible = "renesas,r9a09g077m44", "renesas,r9a09g077";
};

279
arch/arm64/boot/dts/renesas/r9a09g087.dtsi Normal file
View File

@@ -0,0 +1,279 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/N2H SoC
*
* Copyright (C) 2025 Renesas Electronics Corp.
*/
#include <dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "renesas,r9a09g087";
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a55";
reg = <0>;
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
};
cpu1: cpu@100 {
compatible = "arm,cortex-a55";
reg = <0x100>;
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
};
cpu2: cpu@200 {
compatible = "arm,cortex-a55";
reg = <0x200>;
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
};
cpu3: cpu@300 {
compatible = "arm,cortex-a55";
reg = <0x300>;
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
};
L3_CA55: cache-controller-0 {
compatible = "cache";
cache-unified;
cache-size = <0x100000>;
cache-level = <3>;
};
};
extal_clk: extal {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
};
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
sci0: serial@80005000 {
compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci";
reg = <0 0x80005000 0 0x400>;
interrupts = <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 591 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 592 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi", "tei";
clocks = <&cpg CPG_MOD 8>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>;
clock-names = "operation", "bus";
power-domains = <&cpg>;
status = "disabled";
};
sci1: serial@80005400 {
compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci";
reg = <0 0x80005400 0 0x400>;
interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 595 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 596 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi", "tei";
clocks = <&cpg CPG_MOD 9>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>;
clock-names = "operation", "bus";
power-domains = <&cpg>;
status = "disabled";
};
sci2: serial@80005800 {
compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci";
reg = <0 0x80005800 0 0x400>;
interrupts = <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 599 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 600 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi", "tei";
clocks = <&cpg CPG_MOD 10>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>;
clock-names = "operation", "bus";
power-domains = <&cpg>;
status = "disabled";
};
sci3: serial@80005c00 {
compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci";
reg = <0 0x80005c00 0 0x400>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 603 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 604 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi", "tei";
clocks = <&cpg CPG_MOD 11>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>;
clock-names = "operation", "bus";
power-domains = <&cpg>;
status = "disabled";
};
sci4: serial@80006000 {
compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci";
reg = <0 0x80006000 0 0x400>;
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 607 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 608 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi", "tei";
clocks = <&cpg CPG_MOD 12>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>;
clock-names = "operation", "bus";
power-domains = <&cpg>;
status = "disabled";
};
sci5: serial@81005000 {
compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci";
reg = <0 0x81005000 0 0x400>;
interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 611 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 612 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi", "tei";
clocks = <&cpg CPG_MOD 600>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>;
clock-names = "operation", "bus";
power-domains = <&cpg>;
status = "disabled";
};
i2c0: i2c@80088000 {
compatible = "renesas,riic-r9a09g087", "renesas,riic-r9a09g077";
reg = <0 0x80088000 0 0x400>;
interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 615 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 616 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 617 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eei", "rxi", "txi", "tei";
clocks = <&cpg CPG_MOD 100>;
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@80088400 {
compatible = "renesas,riic-r9a09g087", "renesas,riic-r9a09g077";
reg = <0 0x80088400 0 0x400>;
interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 619 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 620 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 621 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eei", "rxi", "txi", "tei";
clocks = <&cpg CPG_MOD 101>;
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@81008000 {
compatible = "renesas,riic-r9a09g087", "renesas,riic-r9a09g077";
reg = <0 0x81008000 0 0x400>;
interrupts = <GIC_SPI 622 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 623 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 624 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eei", "rxi", "txi", "tei";
clocks = <&cpg CPG_MOD 601>;
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
cpg: clock-controller@80280000 {
compatible = "renesas,r9a09g087-cpg-mssr";
reg = <0 0x80280000 0 0x1000>,
<0 0x81280000 0 0x9000>;
clocks = <&extal_clk>;
clock-names = "extal";
#clock-cells = <2>;
#reset-cells = <1>;
#power-domain-cells = <0>;
};
gic: interrupt-controller@83000000 {
compatible = "arm,gic-v3";
reg = <0x0 0x83000000 0 0x40000>,
<0x0 0x83040000 0 0x160000>;
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
sdhi0: mmc@92080000 {
compatible = "renesas,sdhi-r9a09g087",
"renesas,sdhi-r9a09g057";
reg = <0x0 0x92080000 0 0x10000>;
interrupts = <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 1212>,
<&cpg CPG_CORE R9A09G087_SDHI_CLKHS>;
clock-names = "aclk", "clkh";
power-domains = <&cpg>;
status = "disabled";
sdhi0_vqmmc: vqmmc-regulator {
regulator-name = "SDHI0-VQMMC";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
status = "disabled";
};
};
sdhi1: mmc@92090000 {
compatible = "renesas,sdhi-r9a09g087",
"renesas,sdhi-r9a09g057";
reg = <0x0 0x92090000 0 0x10000>;
interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 1213>,
<&cpg CPG_CORE R9A09G087_SDHI_CLKHS>;
clock-names = "aclk", "clkh";
power-domains = <&cpg>;
status = "disabled";
sdhi1_vqmmc: vqmmc-regulator {
regulator-name = "SDHI1-VQMMC";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
status = "disabled";
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
};
};

16
arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts Normal file
View File

@@ -0,0 +1,16 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/N2H EVK board
*
* Copyright (C) 2025 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r9a09g087m44.dtsi"
#include "rzt2h-n2h-evk-common.dtsi"
/ {
model = "Renesas RZ/N2H EVK Board based on r9a09g087m44";
compatible = "renesas,rzn2h-evk", "renesas,r9a09g087m44", "renesas,r9a09g087";
};

13
arch/arm64/boot/dts/renesas/r9a09g087m44.dtsi Normal file
View File

@@ -0,0 +1,13 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/N2H 4-core SoC
*
* Copyright (C) 2025 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r9a09g087.dtsi"
/ {
compatible = "renesas,r9a09g087m44", "renesas,r9a09g087";
};

5
arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
View File

@@ -48,7 +48,10 @@ sound_card {
#if (SW_SCIF_CAN || SW_RSPI_CAN)
&canfd {
pinctrl-0 = <&can1_pins>;
/delete-node/ channel@0;
channel0 {
status = "disabled";
};
};
#else
&canfd {

26
arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi Normal file
View File

@@ -0,0 +1,26 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Common Device Tree Source for the RZ/T2H and RZ/N2H EVK boards.
*
* Copyright (C) 2025 Renesas Electronics Corp.
*/
/ {
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
serial0 = &sci0;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&extal_clk {
clock-frequency = <25000000>;
};
&sci0 {
status = "okay";
};

1
include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
View File

@@ -25,5 +25,6 @@
#define R9A09G077_CLK_PCLKM 13
#define R9A09G077_CLK_PCLKL 14
#define R9A09G077_SDHI_CLKHS 15
#define R9A09G077_USB_CLK 16
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */

1
include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h
View File

@@ -25,5 +25,6 @@
#define R9A09G087_CLK_PCLKM 13
#define R9A09G087_CLK_PCLKL 14
#define R9A09G087_SDHI_CLKHS 15
#define R9A09G087_USB_CLK 16
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ */

22
include/dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h Normal file
View File

@@ -0,0 +1,22 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* This header provides constants for Renesas RZ/T2H family pinctrl bindings.
*
* Copyright (C) 2025 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_PINCTRL_RENESAS_R9A09G077_PINCTRL_H__
#define __DT_BINDINGS_PINCTRL_RENESAS_R9A09G077_PINCTRL_H__
#define RZT2H_PINS_PER_PORT 8
/*
* Create the pin index from its bank and position numbers and store in
* the upper 16 bits the alternate function identifier
*/
#define RZT2H_PORT_PINMUX(b, p, f) ((b) * RZT2H_PINS_PER_PORT + (p) | ((f) << 16))
/* Convert a port and pin label to its global pin index */
#define RZT2H_GPIO(port, pin) ((port) * RZT2H_PINS_PER_PORT + (pin))
#endif /* __DT_BINDINGS_PINCTRL_RENESAS_R9A09G077_PINCTRL_H__ */