mirrors/linux
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2026-04-05 04:46:54 -04:00
Code Issues Packages Projects Releases Wiki Activity

serial: sh-sci: Add RSCI_PORT_SCIF32 port ID

Browse Source 
The RZ/G3E RSCI IP has 32-stage FIFO compared to 16-stage FIFO on RZ/T2H.
Add RSCI_PORT_SCIF32 port ID to differentiate it from RZ/T2H RSCI and
update sci_is_rsci_type() and sci_is_fifo_type()

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://patch.msgid.link/20251129164325.209213-13-biju.das.jz@bp.renesas.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Biju Das
2025-11-29 16:43:08 +00:00
committed by Greg Kroah-Hartman
parent d53f4aa9ed
commit 4cb2bd1bf4
2 changed files with 2 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/tty/serial/sh-sci-common.h
View File

@@ -8,6 +8,7 @@
/* Private port IDs */
enum SCI_PORT_TYPE {
RSCI_PORT_SCIF16 = BIT(7) | 0,
RSCI_PORT_SCIF32 = BIT(7) | 1,
};
enum SCI_CLKS {

2
drivers/tty/serial/sh-sci.c
View File

@@ -1184,7 +1184,7 @@ static int sci_handle_errors(struct uart_port *port)
static bool sci_is_rsci_type(u8 type)
{
return (type == RSCI_PORT_SCIF16);
return (type == RSCI_PORT_SCIF16 || type == RSCI_PORT_SCIF32);
}
static int sci_handle_fifo_overrun(struct uart_port *port)