mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-08-31 15:22:21 -04:00
Merge branch 'pci/controller/cadence'
- Add missing MODULE_DEVICE_TABLE to generate module aliases for OF-based module autoloading (Pengpeng Hou) - Add debugfs 'ltssm_status' file for LGA- and HPA-based Cadence controllers (Hans Zhang) - Support up to x4 (not x2) lanes for J200 (Takuma Fujiwara) - Fix host/endpoint dependencies for cadence-plat driver to fix link error when cadence-plat is built-in but the host or endpoint driver is modular (Aksh Garg) * pci/controller/cadence: PCI: cadence: Fix host/endpoint dependencies for cadence-plat driver PCI: j721e: Fix incorrect max_lanes for J7200 PCI: cadence: Add LGA IP debugfs for LTSSM status PCI: cadence: Add HPA IP debugfs for LTSSM status PCI: cadence: Add HPA architecture flag PCI: cadence: Add missing MODULE_DEVICE_TABLE()
This commit is contained in:
Bjorn Helgaas
5
Documentation/ABI/testing/debugfs-cdns-pcie
Normal file
5
Documentation/ABI/testing/debugfs-cdns-pcie
Normal file
@@ -0,0 +1,5 @@
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What: /sys/kernel/debug/cdns_pcie_<dev>/ltssm_status
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Date: July 2026
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Contact: Hans Zhang <18255117159@163.com>
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Description: (RO) Read will return the current PCIe LTSSM state in both
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string and raw value.
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@@ -6,6 +6,15 @@ menu "Cadence-based PCIe controllers"
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config PCIE_CADENCE
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tristate
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config PCIE_CADENCE_DEBUGFS
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bool "Cadence PCIe debugfs entries"
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depends on DEBUG_FS
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depends on PCIE_CADENCE_HOST || PCIE_CADENCE_EP
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help
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Say Y here to enable debugfs entries for the PCIe controller. These
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entries provide various debug features related to the controller and
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the LTSSM status of link can be displayed.
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config PCIE_CADENCE_HOST
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tristate
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depends on OF
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@@ -20,11 +29,12 @@ config PCIE_CADENCE_EP
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config PCIE_CADENCE_PLAT
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tristate
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select PCIE_CADENCE_HOST if PCIE_CADENCE_PLAT_HOST != n
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select PCIE_CADENCE_EP if PCIE_CADENCE_PLAT_EP != n
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config PCIE_CADENCE_PLAT_HOST
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tristate "Cadence platform PCIe controller (host mode)"
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depends on OF
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select PCIE_CADENCE_HOST
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select PCIE_CADENCE_PLAT
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help
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Say Y here if you want to support the Cadence PCIe platform controller in
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@@ -35,7 +45,6 @@ config PCIE_CADENCE_PLAT_EP
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tristate "Cadence platform PCIe controller (endpoint mode)"
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depends on OF
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depends on PCI_ENDPOINT
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select PCIE_CADENCE_EP
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select PCIE_CADENCE_PLAT
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help
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Say Y here if you want to support the Cadence PCIe platform controller in
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@@ -1,5 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0
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pcie-cadence-mod-y := pcie-cadence-hpa.o pcie-cadence.o
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pcie-cadence-mod-$(CONFIG_PCIE_CADENCE_DEBUGFS) += pcie-cadence-debugfs.o
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pcie-cadence-host-mod-y := pcie-cadence-host-common.o pcie-cadence-host.o pcie-cadence-host-hpa.o
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pcie-cadence-ep-mod-y := pcie-cadence-ep.o
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@@ -383,7 +383,7 @@ static const struct j721e_pcie_data j7200_pcie_rc_data = {
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.quirk_detect_quiet_flag = true,
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.linkdown_irq_regfield = J7200_LINK_DOWN,
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.byte_access_allowed = true,
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.max_lanes = 2,
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.max_lanes = 4,
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};
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static const struct j721e_pcie_data j7200_pcie_ep_data = {
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@@ -391,7 +391,7 @@ static const struct j721e_pcie_data j7200_pcie_ep_data = {
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.quirk_detect_quiet_flag = true,
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.linkdown_irq_regfield = J7200_LINK_DOWN,
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.quirk_disable_flr = true,
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.max_lanes = 2,
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.max_lanes = 4,
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};
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static const struct j721e_pcie_data am64_pcie_rc_data = {
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@@ -174,6 +174,7 @@ static int sky1_pcie_probe(struct platform_device *pdev)
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cdns_pcie->reg_base = pcie->reg_base;
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cdns_pcie->msg_res = pcie->msg_res;
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cdns_pcie->is_rc = true;
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cdns_pcie->is_hpa = true;
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reg_off = devm_kzalloc(dev, sizeof(*reg_off), GFP_KERNEL);
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if (!reg_off) {
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@@ -220,6 +221,10 @@ MODULE_DEVICE_TABLE(of, of_sky1_pcie_match);
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static void sky1_pcie_remove(struct platform_device *pdev)
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{
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struct sky1_pcie *pcie = platform_get_drvdata(pdev);
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struct cdns_pcie_rc *rc;
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rc = container_of(pcie->cdns_pcie, struct cdns_pcie_rc, pcie);
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cdns_pcie_hpa_host_disable(rc);
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pci_ecam_free(pcie->cfg);
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}
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263
drivers/pci/controller/cadence/pcie-cadence-debugfs.c
Normal file
263
drivers/pci/controller/cadence/pcie-cadence-debugfs.c
Normal file
@@ -0,0 +1,263 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Cadence PCIe controller debugfs driver
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*
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* Copyright (C) 2026 Hans Zhang <18255117159@163.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/debugfs.h>
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#include <linux/seq_file.h>
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#include "pcie-cadence.h"
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#define CDNS_DEBUGFS_BUF_MAX 128
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static const char *cdns_pcie_lga_ltssm_status_string(enum cdns_pcie_lga_ltssm ltssm)
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{
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const char *str;
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switch (ltssm) {
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#define CDNS_PCIE_LGA_LTSSM_NAME(n) case n: str = #n; break
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CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_DETECT_QUIET);
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CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_DETECT_ACTIVE);
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CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_POLLING_ACTIVE);
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CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_POLLING_COMPLIANCE);
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CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_POLLING_CONFIGURATION);
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CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_CONFIGURATION_LINKWIDTH_START);
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CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_CONFIGURATION_LINKWIDTH_ACCEPT);
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CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_CONFIGURATION_LANENUM_ACCEPT);
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CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_CONFIGURATION_LANENUM_WAIT);
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CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_CONFIGURATION_COMPLETE);
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CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_CONFIGURATION_IDLE);
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CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_RECOVERY_RCVRLOCK);
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CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_RECOVERY_SPEED);
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CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_RECOVERY_RCVRCFG);
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CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_RECOVERY_IDLE);
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CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_L0);
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CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_RX_L0S_ENTRY);
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CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_RX_L0S_IDLE);
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CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_RX_L0S_FTS);
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CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_TX_L0S_ENTRY);
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CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_TX_L0S_IDLE);
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CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_TX_L0S_FTS);
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CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_L1_ENTRY);
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CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_L1_IDLE);
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CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_L2_IDLE);
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CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_L2_TRANSMITWAKE);
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CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_DISABLED);
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CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_LOOPBACK_ENTRY_MASTER);
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CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_LOOPBACK_ACTIVE_MASTER);
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CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_LOOPBACK_EXIT_MASTER);
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CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_LOOPBACK_ENTRY_SLAVE);
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CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_LOOPBACK_ACTIVE_SLAVE);
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CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_LOOPBACK_EXIT_SLAVE);
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CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_HOT_RESET);
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CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_RECOVERY_EQUALIZATION_PHASE_0);
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CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_RECOVERY_EQUALIZATION_PHASE_1);
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CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_RECOVERY_EQUALIZATION_PHASE_2);
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CDNS_PCIE_LGA_LTSSM_NAME(CDNS_PCIE_LGA_LTSSM_RECOVERY_EQUALIZATION_PHASE_3);
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default:
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str = "CDNS_PCIE_LGA_LTSSM_UNKNOWN";
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break;
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}
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return str + strlen("CDNS_PCIE_LGA_LTSSM_");
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}
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static const char *cdns_pcie_hpa_ltssm_status_string(enum cdns_pcie_hpa_ltssm ltssm)
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{
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const char *str;
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switch (ltssm) {
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#define CDNS_PCIE_HPA_LTSSM_NAME(n) case n: str = #n; break
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DETECT_QUIET);
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DETECT_QUIET_ENTRY);
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DETECT_ACTIVE);
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DETECT_ACTIVE_1);
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DETECT_ACTIVE_2);
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DETECT_ACTIVE_3);
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RCVR_DETECTED_ST);
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RCVR_DETECTED_1);
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_ACTIVE);
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_ACTIVE_1);
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_ACTIVE_2);
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_ACTIVE_3);
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE);
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_1);
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_CONFIG);
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_CONFIG_1);
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_CONFIG_2);
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_LW_START_RC);
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_LW_START_RC_1);
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_LW_START_RC_2);
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_LW_ACC_RC);
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_LANENUM_WAIT_RC);
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_LANENUM_WAIT_RC_1);
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_LANENUM_ACC_RC);
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_LW_START_EP);
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_LW_START_EP_1);
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_LW_START_EP_2);
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_LW_ACC_EP);
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_LANENUM_WAIT_EP);
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_LANENUM_WAIT_EP_1);
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_LANENUM_ACC_EP);
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_LANENUM_ACC_EP_1);
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DUMMY_STATE_1);
|
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_COMPLETE);
|
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_COMPLETE_1);
|
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_COMPLETE_2);
|
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_IDLE);
|
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_CONFIG_IDLE_1);
|
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DUMMY_STATE_2);
|
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DUMMY_STATE_3);
|
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DUMMY_STATE_4);
|
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L0_STATE);
|
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_RCVR_LOCK);
|
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_RCVR_LOCK_1);
|
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_RCVR_CFG);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_RCVR_CFG_1);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_IDLE);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_IDLE_1);
|
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DISABLE_LINK);
|
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DISABLE_LINK_1);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DISABLE_LINK_2);
|
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DISABLE_LINK_3);
|
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DISABLE_LINK_4);
|
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DISABLE_LINK_5);
|
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DISABLE_LINK_6);
|
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_DISABLE_LINK_7);
|
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_HOT_RESET);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_HOT_RESET_1);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_HOT_RESET_2);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_HOT_RESET_3);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L0S_ENTRY);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L0S_1);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L0S_2);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L0S_3);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L0S_4);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L0S_5);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_WAIT_FOR_LINK_TX);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_TX_FTS_ENTRY);
|
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CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_TX_FTS_1);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_TX_FTS_2);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_TX_ELEC_IDLE_ST);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_TX_ELEC_IDLE_1);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_TX_ELEC_IDLE_2);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_TX_ELEC_IDLE_3);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_SPEED);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_SPEED_1);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_SPEED_2);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_SPEED_3);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_1);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_2);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_3);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_4);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_5);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_6);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_7);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_8);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_ENTRY);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_ENTRY_FROM_RECOVERY);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_EXIT_1);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_EXIT);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_GEN2_1);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_GEN2_2);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_GEN2_3);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_GEN2_4);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_GEN2_5);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_ACTIVE);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L1_ENTRY);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L1_1);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L1_2);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L1_3);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L1_4);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L1_IDLE);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L1_EXIT);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L2_ENTRY);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L2_1);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L2_2);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L2_3);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L2_4);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L2_5);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_L2_IDLE);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ENTRY);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ENTRY_1);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ENTRY_2);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ENTRY_3);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ENTRY_4);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ENTRY_5);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ENTRY_FROM_RECOVERY);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ACTIVE);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_EXIT);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_EXIT_1);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_EXIT_2);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_EQUALIZATION_PHASE0);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_EQUALIZATION_PHASE1);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_EQUALIZATION_PHASE2_1);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_EQUALIZATION_PHASE2_2);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_EQUALIZATION_PHASE3_1);
|
||||
CDNS_PCIE_HPA_LTSSM_NAME(CDNS_PCIE_HPA_LTSSM_RECOVERY_EQUALIZATION_PHASE3_2);
|
||||
default:
|
||||
str = "CDNS_PCIE_HPA_LTSSM_UNKNOWN";
|
||||
break;
|
||||
}
|
||||
|
||||
return str + strlen("CDNS_PCIE_HPA_LTSSM_");
|
||||
}
|
||||
|
||||
static int ltssm_status_show(struct seq_file *s, void *v)
|
||||
{
|
||||
struct cdns_pcie *pci = s->private;
|
||||
enum cdns_pcie_lga_ltssm lga_ltssm;
|
||||
enum cdns_pcie_hpa_ltssm hpa_ltssm;
|
||||
const char *str_ltssm;
|
||||
u32 val;
|
||||
|
||||
if (pci->is_hpa) {
|
||||
val = cdns_pcie_hpa_readl(pci, REG_BANK_IP_REG,
|
||||
CDNS_PCIE_HPA_PHY_DBG_STS_REG0);
|
||||
hpa_ltssm = FIELD_GET(CDNS_PCIE_HPA_LTSSM_STATUS_MASK, val);
|
||||
str_ltssm = cdns_pcie_hpa_ltssm_status_string(hpa_ltssm);
|
||||
} else {
|
||||
val = cdns_pcie_readl(pci, CDNS_PCIE_LM_BASE);
|
||||
lga_ltssm = FIELD_GET(CDNS_PCIE_LGA_LTSSM_STATUS_MASK, val);
|
||||
str_ltssm = cdns_pcie_lga_ltssm_status_string(lga_ltssm);
|
||||
}
|
||||
|
||||
seq_printf(s, "%s (0x%02x)\n", str_ltssm,
|
||||
pci->is_hpa ? hpa_ltssm : lga_ltssm);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
DEFINE_SHOW_ATTRIBUTE(ltssm_status);
|
||||
|
||||
static void cdns_pcie_ltssm_debugfs_init(struct cdns_pcie *pci, struct dentry *dir)
|
||||
{
|
||||
debugfs_create_file("ltssm_status", 0444, dir, pci,
|
||||
<ssm_status_fops);
|
||||
}
|
||||
|
||||
void cdns_pcie_debugfs_deinit(struct cdns_pcie *pci)
|
||||
{
|
||||
if (!pci->debug_dir)
|
||||
return;
|
||||
|
||||
debugfs_remove_recursive(pci->debug_dir);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(cdns_pcie_debugfs_deinit);
|
||||
|
||||
void cdns_pcie_debugfs_init(struct cdns_pcie *pci)
|
||||
{
|
||||
char dirname[CDNS_DEBUGFS_BUF_MAX];
|
||||
struct device *dev = pci->dev;
|
||||
|
||||
/* Create main directory for each platform driver. */
|
||||
snprintf(dirname, CDNS_DEBUGFS_BUF_MAX, "cdns_pcie_%s", dev_name(dev));
|
||||
pci->debug_dir = debugfs_create_dir(dirname, NULL);
|
||||
|
||||
cdns_pcie_ltssm_debugfs_init(pci, pci->debug_dir);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(cdns_pcie_debugfs_init);
|
||||
@@ -655,6 +655,7 @@ void cdns_pcie_ep_disable(struct cdns_pcie_ep *ep)
|
||||
struct device *dev = ep->pcie.dev;
|
||||
struct pci_epc *epc = to_pci_epc(dev);
|
||||
|
||||
cdns_pcie_debugfs_deinit(&ep->pcie);
|
||||
pci_epc_deinit_notify(epc);
|
||||
pci_epc_mem_free_addr(epc, ep->irq_phys_addr, ep->irq_cpu_addr,
|
||||
SZ_128K);
|
||||
@@ -761,6 +762,8 @@ int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep)
|
||||
|
||||
pci_epc_init_notify(epc);
|
||||
|
||||
cdns_pcie_debugfs_init(pcie);
|
||||
|
||||
return 0;
|
||||
|
||||
free_epc_mem:
|
||||
|
||||
@@ -313,6 +313,19 @@ int cdns_pcie_hpa_host_link_setup(struct cdns_pcie_rc *rc)
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(cdns_pcie_hpa_host_link_setup);
|
||||
|
||||
void cdns_pcie_hpa_host_disable(struct cdns_pcie_rc *rc)
|
||||
{
|
||||
struct pci_host_bridge *bridge;
|
||||
|
||||
cdns_pcie_debugfs_deinit(&rc->pcie);
|
||||
bridge = pci_host_bridge_from_priv(rc);
|
||||
pci_lock_rescan_remove();
|
||||
pci_stop_root_bus(bridge->bus);
|
||||
pci_remove_root_bus(bridge->bus);
|
||||
pci_unlock_rescan_remove();
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(cdns_pcie_hpa_host_disable);
|
||||
|
||||
int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc)
|
||||
{
|
||||
struct device *dev = rc->pcie.dev;
|
||||
@@ -368,7 +381,13 @@ int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc)
|
||||
if (!bridge->ops)
|
||||
bridge->ops = &cdns_pcie_hpa_host_ops;
|
||||
|
||||
return pci_host_probe(bridge);
|
||||
ret = pci_host_probe(bridge);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
cdns_pcie_debugfs_init(pcie);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(cdns_pcie_hpa_host_setup);
|
||||
|
||||
|
||||
@@ -365,6 +365,7 @@ void cdns_pcie_host_disable(struct cdns_pcie_rc *rc)
|
||||
{
|
||||
struct pci_host_bridge *bridge;
|
||||
|
||||
cdns_pcie_debugfs_deinit(&rc->pcie);
|
||||
bridge = pci_host_bridge_from_priv(rc);
|
||||
pci_lock_rescan_remove();
|
||||
pci_stop_root_bus(bridge->bus);
|
||||
@@ -429,7 +430,13 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
|
||||
if (!bridge->ops)
|
||||
bridge->ops = &cdns_pcie_host_ops;
|
||||
|
||||
return pci_host_probe(bridge);
|
||||
ret = pci_host_probe(bridge);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
cdns_pcie_debugfs_init(pcie);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(cdns_pcie_host_setup);
|
||||
|
||||
|
||||
@@ -163,6 +163,7 @@ static const struct of_device_id cdns_plat_pcie_of_match[] = {
|
||||
},
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, cdns_plat_pcie_of_match);
|
||||
|
||||
static struct platform_driver cdns_plat_pcie_driver = {
|
||||
.driver = {
|
||||
|
||||
@@ -14,6 +14,9 @@
|
||||
#include "pcie-cadence-lga-regs.h"
|
||||
#include "pcie-cadence-hpa-regs.h"
|
||||
|
||||
#define CDNS_PCIE_LGA_LTSSM_STATUS_MASK GENMASK(29, 24)
|
||||
#define CDNS_PCIE_HPA_LTSSM_STATUS_MASK GENMASK(27, 20)
|
||||
|
||||
enum cdns_pcie_rp_bar {
|
||||
RP_BAR_UNDEFINED = -1,
|
||||
RP_BAR0,
|
||||
@@ -42,6 +45,180 @@ enum cdns_pcie_reg_bank {
|
||||
REG_BANKS_MAX,
|
||||
};
|
||||
|
||||
enum cdns_pcie_lga_ltssm {
|
||||
CDNS_PCIE_LGA_LTSSM_DETECT_QUIET = 0x00,
|
||||
CDNS_PCIE_LGA_LTSSM_DETECT_ACTIVE = 0x01,
|
||||
CDNS_PCIE_LGA_LTSSM_POLLING_ACTIVE = 0x02,
|
||||
CDNS_PCIE_LGA_LTSSM_POLLING_COMPLIANCE = 0x03,
|
||||
CDNS_PCIE_LGA_LTSSM_POLLING_CONFIGURATION = 0x04,
|
||||
CDNS_PCIE_LGA_LTSSM_CONFIGURATION_LINKWIDTH_START = 0x05,
|
||||
CDNS_PCIE_LGA_LTSSM_CONFIGURATION_LINKWIDTH_ACCEPT = 0x06,
|
||||
CDNS_PCIE_LGA_LTSSM_CONFIGURATION_LANENUM_ACCEPT = 0x07,
|
||||
CDNS_PCIE_LGA_LTSSM_CONFIGURATION_LANENUM_WAIT = 0x08,
|
||||
CDNS_PCIE_LGA_LTSSM_CONFIGURATION_COMPLETE = 0x09,
|
||||
CDNS_PCIE_LGA_LTSSM_CONFIGURATION_IDLE = 0x0A,
|
||||
CDNS_PCIE_LGA_LTSSM_RECOVERY_RCVRLOCK = 0x0B,
|
||||
CDNS_PCIE_LGA_LTSSM_RECOVERY_SPEED = 0x0C,
|
||||
CDNS_PCIE_LGA_LTSSM_RECOVERY_RCVRCFG = 0x0D,
|
||||
CDNS_PCIE_LGA_LTSSM_RECOVERY_IDLE = 0x0E,
|
||||
CDNS_PCIE_LGA_LTSSM_L0 = 0x10,
|
||||
CDNS_PCIE_LGA_LTSSM_RX_L0S_ENTRY = 0x11,
|
||||
CDNS_PCIE_LGA_LTSSM_RX_L0S_IDLE = 0x12,
|
||||
CDNS_PCIE_LGA_LTSSM_RX_L0S_FTS = 0x13,
|
||||
CDNS_PCIE_LGA_LTSSM_TX_L0S_ENTRY = 0x14,
|
||||
CDNS_PCIE_LGA_LTSSM_TX_L0S_IDLE = 0x15,
|
||||
CDNS_PCIE_LGA_LTSSM_TX_L0S_FTS = 0x16,
|
||||
CDNS_PCIE_LGA_LTSSM_L1_ENTRY = 0x17,
|
||||
CDNS_PCIE_LGA_LTSSM_L1_IDLE = 0x18,
|
||||
CDNS_PCIE_LGA_LTSSM_L2_IDLE = 0x19,
|
||||
CDNS_PCIE_LGA_LTSSM_L2_TRANSMITWAKE = 0x1A,
|
||||
CDNS_PCIE_LGA_LTSSM_DISABLED = 0x20,
|
||||
CDNS_PCIE_LGA_LTSSM_LOOPBACK_ENTRY_MASTER = 0x21,
|
||||
CDNS_PCIE_LGA_LTSSM_LOOPBACK_ACTIVE_MASTER = 0x22,
|
||||
CDNS_PCIE_LGA_LTSSM_LOOPBACK_EXIT_MASTER = 0x23,
|
||||
CDNS_PCIE_LGA_LTSSM_LOOPBACK_ENTRY_SLAVE = 0x24,
|
||||
CDNS_PCIE_LGA_LTSSM_LOOPBACK_ACTIVE_SLAVE = 0x25,
|
||||
CDNS_PCIE_LGA_LTSSM_LOOPBACK_EXIT_SLAVE = 0x26,
|
||||
CDNS_PCIE_LGA_LTSSM_HOT_RESET = 0x27,
|
||||
CDNS_PCIE_LGA_LTSSM_RECOVERY_EQUALIZATION_PHASE_0 = 0x28,
|
||||
CDNS_PCIE_LGA_LTSSM_RECOVERY_EQUALIZATION_PHASE_1 = 0x29,
|
||||
CDNS_PCIE_LGA_LTSSM_RECOVERY_EQUALIZATION_PHASE_2 = 0x2A,
|
||||
CDNS_PCIE_LGA_LTSSM_RECOVERY_EQUALIZATION_PHASE_3 = 0x2B,
|
||||
CDNS_PCIE_LGA_LTSSM_UNKNOWN = 0xFFFFFFFF,
|
||||
};
|
||||
|
||||
enum cdns_pcie_hpa_ltssm {
|
||||
CDNS_PCIE_HPA_LTSSM_DETECT_QUIET = 0,
|
||||
CDNS_PCIE_HPA_LTSSM_DETECT_QUIET_ENTRY = 1,
|
||||
CDNS_PCIE_HPA_LTSSM_DETECT_ACTIVE = 2,
|
||||
CDNS_PCIE_HPA_LTSSM_DETECT_ACTIVE_1 = 3,
|
||||
CDNS_PCIE_HPA_LTSSM_DETECT_ACTIVE_2 = 4,
|
||||
CDNS_PCIE_HPA_LTSSM_DETECT_ACTIVE_3 = 5,
|
||||
CDNS_PCIE_HPA_LTSSM_RCVR_DETECTED_ST = 6,
|
||||
CDNS_PCIE_HPA_LTSSM_RCVR_DETECTED_1 = 7,
|
||||
CDNS_PCIE_HPA_LTSSM_POLLING_ACTIVE = 8,
|
||||
CDNS_PCIE_HPA_LTSSM_POLLING_ACTIVE_1 = 9,
|
||||
CDNS_PCIE_HPA_LTSSM_POLLING_ACTIVE_2 = 10,
|
||||
CDNS_PCIE_HPA_LTSSM_POLLING_ACTIVE_3 = 11,
|
||||
CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE = 12,
|
||||
CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_1 = 13,
|
||||
CDNS_PCIE_HPA_LTSSM_POLLING_CONFIG = 14,
|
||||
CDNS_PCIE_HPA_LTSSM_POLLING_CONFIG_1 = 15,
|
||||
CDNS_PCIE_HPA_LTSSM_POLLING_CONFIG_2 = 16,
|
||||
CDNS_PCIE_HPA_LTSSM_CONFIG_LW_START_RC = 17,
|
||||
CDNS_PCIE_HPA_LTSSM_CONFIG_LW_START_RC_1 = 18,
|
||||
CDNS_PCIE_HPA_LTSSM_CONFIG_LW_START_RC_2 = 19,
|
||||
CDNS_PCIE_HPA_LTSSM_CONFIG_LW_ACC_RC = 20,
|
||||
CDNS_PCIE_HPA_LTSSM_CONFIG_LANENUM_WAIT_RC = 21,
|
||||
CDNS_PCIE_HPA_LTSSM_CONFIG_LANENUM_WAIT_RC_1 = 22,
|
||||
CDNS_PCIE_HPA_LTSSM_CONFIG_LANENUM_ACC_RC = 23,
|
||||
CDNS_PCIE_HPA_LTSSM_CONFIG_LW_START_EP = 24,
|
||||
CDNS_PCIE_HPA_LTSSM_CONFIG_LW_START_EP_1 = 25,
|
||||
CDNS_PCIE_HPA_LTSSM_CONFIG_LW_START_EP_2 = 26,
|
||||
CDNS_PCIE_HPA_LTSSM_CONFIG_LW_ACC_EP = 27,
|
||||
CDNS_PCIE_HPA_LTSSM_CONFIG_LANENUM_WAIT_EP = 28,
|
||||
CDNS_PCIE_HPA_LTSSM_CONFIG_LANENUM_WAIT_EP_1 = 29,
|
||||
CDNS_PCIE_HPA_LTSSM_CONFIG_LANENUM_ACC_EP = 30,
|
||||
CDNS_PCIE_HPA_LTSSM_CONFIG_LANENUM_ACC_EP_1 = 31,
|
||||
CDNS_PCIE_HPA_LTSSM_DUMMY_STATE_1 = 32,
|
||||
CDNS_PCIE_HPA_LTSSM_CONFIG_COMPLETE = 33,
|
||||
CDNS_PCIE_HPA_LTSSM_CONFIG_COMPLETE_1 = 34,
|
||||
CDNS_PCIE_HPA_LTSSM_CONFIG_COMPLETE_2 = 35,
|
||||
CDNS_PCIE_HPA_LTSSM_CONFIG_IDLE = 36,
|
||||
CDNS_PCIE_HPA_LTSSM_CONFIG_IDLE_1 = 37,
|
||||
CDNS_PCIE_HPA_LTSSM_DUMMY_STATE_2 = 38,
|
||||
CDNS_PCIE_HPA_LTSSM_DUMMY_STATE_3 = 39,
|
||||
CDNS_PCIE_HPA_LTSSM_DUMMY_STATE_4 = 40,
|
||||
CDNS_PCIE_HPA_LTSSM_L0_STATE = 41,
|
||||
CDNS_PCIE_HPA_LTSSM_RECOVERY_RCVR_LOCK = 42,
|
||||
CDNS_PCIE_HPA_LTSSM_RECOVERY_RCVR_LOCK_1 = 43,
|
||||
CDNS_PCIE_HPA_LTSSM_RECOVERY_RCVR_CFG = 44,
|
||||
CDNS_PCIE_HPA_LTSSM_RECOVERY_RCVR_CFG_1 = 45,
|
||||
CDNS_PCIE_HPA_LTSSM_RECOVERY_IDLE = 46,
|
||||
CDNS_PCIE_HPA_LTSSM_RECOVERY_IDLE_1 = 47,
|
||||
CDNS_PCIE_HPA_LTSSM_DISABLE_LINK = 48,
|
||||
CDNS_PCIE_HPA_LTSSM_DISABLE_LINK_1 = 49,
|
||||
CDNS_PCIE_HPA_LTSSM_DISABLE_LINK_2 = 50,
|
||||
CDNS_PCIE_HPA_LTSSM_DISABLE_LINK_3 = 51,
|
||||
CDNS_PCIE_HPA_LTSSM_DISABLE_LINK_4 = 52,
|
||||
CDNS_PCIE_HPA_LTSSM_DISABLE_LINK_5 = 53,
|
||||
CDNS_PCIE_HPA_LTSSM_DISABLE_LINK_6 = 54,
|
||||
CDNS_PCIE_HPA_LTSSM_DISABLE_LINK_7 = 55,
|
||||
CDNS_PCIE_HPA_LTSSM_HOT_RESET = 56,
|
||||
CDNS_PCIE_HPA_LTSSM_HOT_RESET_1 = 57,
|
||||
CDNS_PCIE_HPA_LTSSM_HOT_RESET_2 = 58,
|
||||
CDNS_PCIE_HPA_LTSSM_HOT_RESET_3 = 59,
|
||||
CDNS_PCIE_HPA_LTSSM_L0S_ENTRY = 60,
|
||||
CDNS_PCIE_HPA_LTSSM_L0S_1 = 61,
|
||||
CDNS_PCIE_HPA_LTSSM_L0S_2 = 62,
|
||||
CDNS_PCIE_HPA_LTSSM_L0S_3 = 63,
|
||||
CDNS_PCIE_HPA_LTSSM_L0S_4 = 64,
|
||||
CDNS_PCIE_HPA_LTSSM_L0S_5 = 65,
|
||||
CDNS_PCIE_HPA_LTSSM_WAIT_FOR_LINK_TX = 66,
|
||||
CDNS_PCIE_HPA_LTSSM_TX_FTS_ENTRY = 67,
|
||||
CDNS_PCIE_HPA_LTSSM_TX_FTS_1 = 68,
|
||||
CDNS_PCIE_HPA_LTSSM_TX_FTS_2 = 69,
|
||||
CDNS_PCIE_HPA_LTSSM_TX_ELEC_IDLE_ST = 70,
|
||||
CDNS_PCIE_HPA_LTSSM_TX_ELEC_IDLE_1 = 71,
|
||||
CDNS_PCIE_HPA_LTSSM_TX_ELEC_IDLE_2 = 72,
|
||||
CDNS_PCIE_HPA_LTSSM_TX_ELEC_IDLE_3 = 73,
|
||||
CDNS_PCIE_HPA_LTSSM_RECOVERY_SPEED = 74,
|
||||
CDNS_PCIE_HPA_LTSSM_RECOVERY_SPEED_1 = 75,
|
||||
CDNS_PCIE_HPA_LTSSM_RECOVERY_SPEED_2 = 76,
|
||||
CDNS_PCIE_HPA_LTSSM_RECOVERY_SPEED_3 = 77,
|
||||
CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23 = 78,
|
||||
CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_1 = 79,
|
||||
CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_2 = 80,
|
||||
CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_3 = 81,
|
||||
CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_4 = 82,
|
||||
CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_5 = 83,
|
||||
CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_6 = 84,
|
||||
CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_7 = 85,
|
||||
CDNS_PCIE_HPA_LTSSM_POLLING_COMPLIANCE_GEN23_8 = 86,
|
||||
CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_ENTRY = 87,
|
||||
CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_ENTRY_FROM_RECOVERY = 88,
|
||||
CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_EXIT_1 = 89,
|
||||
CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_EXIT = 90,
|
||||
CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_GEN2_1 = 91,
|
||||
CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_GEN2_2 = 92,
|
||||
CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_GEN2_3 = 93,
|
||||
CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_GEN2_4 = 94,
|
||||
CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_GEN2_5 = 95,
|
||||
CDNS_PCIE_HPA_LTSSM_LOOPBACK_SLAVE_ACTIVE = 96,
|
||||
CDNS_PCIE_HPA_LTSSM_L1_ENTRY = 97,
|
||||
CDNS_PCIE_HPA_LTSSM_L1_1 = 98,
|
||||
CDNS_PCIE_HPA_LTSSM_L1_2 = 99,
|
||||
CDNS_PCIE_HPA_LTSSM_L1_3 = 100,
|
||||
CDNS_PCIE_HPA_LTSSM_L1_4 = 101,
|
||||
CDNS_PCIE_HPA_LTSSM_L1_IDLE = 102,
|
||||
CDNS_PCIE_HPA_LTSSM_L1_EXIT = 103,
|
||||
CDNS_PCIE_HPA_LTSSM_L2_ENTRY = 104,
|
||||
CDNS_PCIE_HPA_LTSSM_L2_1 = 105,
|
||||
CDNS_PCIE_HPA_LTSSM_L2_2 = 106,
|
||||
CDNS_PCIE_HPA_LTSSM_L2_3 = 107,
|
||||
CDNS_PCIE_HPA_LTSSM_L2_4 = 108,
|
||||
CDNS_PCIE_HPA_LTSSM_L2_5 = 109,
|
||||
CDNS_PCIE_HPA_LTSSM_L2_IDLE = 110,
|
||||
CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ENTRY = 111,
|
||||
CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ENTRY_1 = 112,
|
||||
CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ENTRY_2 = 113,
|
||||
CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ENTRY_3 = 114,
|
||||
CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ENTRY_4 = 115,
|
||||
CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ENTRY_5 = 116,
|
||||
CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ENTRY_FROM_RECOVERY = 117,
|
||||
CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_ACTIVE = 118,
|
||||
CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_EXIT = 119,
|
||||
CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_EXIT_1 = 120,
|
||||
CDNS_PCIE_HPA_LTSSM_LOOPBACK_MASTER_EXIT_2 = 121,
|
||||
CDNS_PCIE_HPA_LTSSM_RECOVERY_EQUALIZATION_PHASE0 = 122,
|
||||
CDNS_PCIE_HPA_LTSSM_RECOVERY_EQUALIZATION_PHASE1 = 123,
|
||||
CDNS_PCIE_HPA_LTSSM_RECOVERY_EQUALIZATION_PHASE2_1 = 124,
|
||||
CDNS_PCIE_HPA_LTSSM_RECOVERY_EQUALIZATION_PHASE2_2 = 125,
|
||||
CDNS_PCIE_HPA_LTSSM_RECOVERY_EQUALIZATION_PHASE3_1 = 126,
|
||||
CDNS_PCIE_HPA_LTSSM_RECOVERY_EQUALIZATION_PHASE3_2 = 127,
|
||||
CDNS_PCIE_HPA_LTSSM_UNKNOWN = 0xFFFFFFFF,
|
||||
};
|
||||
|
||||
struct cdns_pcie_ops {
|
||||
int (*start_link)(struct cdns_pcie *pcie);
|
||||
void (*stop_link)(struct cdns_pcie *pcie);
|
||||
@@ -80,6 +257,7 @@ struct cdns_plat_pcie_of_data {
|
||||
* @msg_res: Region for send message to map PCI accesses
|
||||
* @dev: PCIe controller
|
||||
* @is_rc: tell whether the PCIe controller mode is Root Complex or Endpoint.
|
||||
* @is_hpa: indicates if the architecture is HPA
|
||||
* @phy_count: number of supported PHY devices
|
||||
* @phy: list of pointers to specific PHY control blocks
|
||||
* @link: list of pointers to corresponding device link representations
|
||||
@@ -87,6 +265,7 @@ struct cdns_plat_pcie_of_data {
|
||||
* wrapper
|
||||
* @cdns_pcie_reg_offsets: Register bank offsets for different SoC
|
||||
* @max_link_speed: Maximum supported link speed
|
||||
* @debug_dir: debugfs node
|
||||
*/
|
||||
struct cdns_pcie {
|
||||
void __iomem *reg_base;
|
||||
@@ -94,12 +273,14 @@ struct cdns_pcie {
|
||||
struct resource *msg_res;
|
||||
struct device *dev;
|
||||
bool is_rc;
|
||||
bool is_hpa;
|
||||
int phy_count;
|
||||
struct phy **phy;
|
||||
struct device_link **link;
|
||||
const struct cdns_pcie_ops *ops;
|
||||
const struct cdns_plat_pcie_of_data *cdns_pcie_reg_offsets;
|
||||
int max_link_speed;
|
||||
struct dentry *debug_dir;
|
||||
};
|
||||
|
||||
/**
|
||||
@@ -447,6 +628,7 @@ void cdns_pcie_host_disable(struct cdns_pcie_rc *rc);
|
||||
void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn,
|
||||
int where);
|
||||
int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc);
|
||||
void cdns_pcie_hpa_host_disable(struct cdns_pcie_rc *rc);
|
||||
#else
|
||||
static inline int cdns_pcie_host_link_setup(struct cdns_pcie_rc *rc)
|
||||
{
|
||||
@@ -472,6 +654,10 @@ static inline void cdns_pcie_host_disable(struct cdns_pcie_rc *rc)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void cdns_pcie_hpa_host_disable(struct cdns_pcie_rc *rc)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn,
|
||||
int where)
|
||||
{
|
||||
@@ -535,4 +721,16 @@ bool cdns_pcie_hpa_link_up(struct cdns_pcie *pcie);
|
||||
|
||||
extern const struct dev_pm_ops cdns_pcie_pm_ops;
|
||||
|
||||
#if IS_ENABLED(CONFIG_PCIE_CADENCE_DEBUGFS)
|
||||
void cdns_pcie_debugfs_deinit(struct cdns_pcie *pci);
|
||||
void cdns_pcie_debugfs_init(struct cdns_pcie *pci);
|
||||
#else
|
||||
static inline void cdns_pcie_debugfs_deinit(struct cdns_pcie *pci)
|
||||
{
|
||||
}
|
||||
static inline void cdns_pcie_debugfs_init(struct cdns_pcie *pci)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _PCIE_CADENCE_H */
|
||||
|
||||
Reference in New Issue
Block a user