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clk: clocking-wizard: fix integer overflow in rate calculation

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When using driver on Zynq-7000 (32-bit) determine_rate calculation
overflows. For instance requesting 32MHz with 100MHz parent clock
results in 100000000*(4*1000+0) 32-bit multiplication.

Replace the expression with mult_frac which is already used in
clk_wzrd_recalc_ratef.

Cc: stable@vger.kernel.org
Fixes: 7681f64e64 ("clk: clocking-wizard: calculate dividers fractional parts")
Signed-off-by: Pale Löbl <pavel@loebl.cz>
Reviewed-by: Brian Masney <bmasney@redhat.com>
Signed-off-by: Brian Masney <bmasney@redhat.com>
This commit is contained in:
Pavel Löbl
2026-06-05 15:03:40 +02:00
committed by Brian Masney
parent 91d00e377f
commit 4adf593c6f
1 changed files with 2 additions and 2 deletions
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4
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
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@@ -663,8 +663,8 @@ static int clk_wzrd_determine_rate_all(struct clk_hw *hw,
d = divider->d;
o = divider->o;
req->rate = div_u64(req->best_parent_rate * (m * 1000 + divider->m_frac),
d * (o * 1000 + divider->o_frac));
req->rate = mult_frac(req->best_parent_rate, m * 1000 + divider->m_frac,
d * (o * 1000 + divider->o_frac));
return 0;
}