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wifi: mt76: mt7915: trigger L1 SER on PLE MDP RIOC hang

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WM firmware can enter a partial failure state where RX is hung.

Detect this condition by monitoring SER_PLE_ERR_1 for MDP_RIOC_HANG_ERR
and trigger L1 SER to restore operation. Use transition detection on the
error bit to fire only once per new occurrence, preventing an infinite
SER loop when the bit remains set across checks.

Signed-off-by: Chad Monroe <chad@monroe.io>
Suggested-by: Ryder Lee <ryder.lee@mediatek.com>
Link: https://patch.msgid.link/20260724124813.3961474-24-nbd@nbd.name
Signed-off-by: Felix Fietkau <nbd@nbd.name>
This commit is contained in:
Chad Monroe
2026-07-24 12:48:08 +00:00
committed by Felix Fietkau
parent 98aff74779
commit 496ea8ceb2
3 changed files with 14 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
drivers/net/wireless/mediatek/mt76/mt7915/mac.c
View File

@@ -1934,7 +1934,7 @@ void mt7915_mac_update_stats(struct mt7915_phy *phy)
static void mt7915_mac_severe_check(struct mt7915_phy *phy)
{
struct mt7915_dev *dev = phy->dev;
u32 trb;
u32 trb, ple_err;
if (!phy->omac_mask)
return;
@@ -1954,6 +1954,17 @@ static void mt7915_mac_severe_check(struct mt7915_phy *phy)
phy->mt76->band_idx);
phy->trb_ts = trb;
ple_err = mt76_rr(dev, MT_SWDEF_PLE1_STATS);
if ((ple_err & MT_SWDEF_PLE1_MDP_RIOC_HANG_ERR) &&
!(dev->ple1_sts & MT_SWDEF_PLE1_MDP_RIOC_HANG_ERR)) {
dev_warn(dev->mt76.dev,
"band%d: PLE error 0x%x detected, triggering L1 SER\n",
phy->mt76->band_idx, ple_err);
mt7915_mcu_set_ser(dev, SER_RECOVER, SER_SET_RECOVER_L1,
phy->mt76->band_idx);
}
dev->ple1_sts = ple_err;
}
void mt7915_mac_sta_rc_work(struct work_struct *work)

1
drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h
View File

@@ -296,6 +296,7 @@ struct mt7915_dev {
spinlock_t reg_lock;
u32 hw_pattern;
u32 ple1_sts;
bool dbdc_support;
bool flash_mode;

1
drivers/net/wireless/mediatek/mt76/mt7915/regs.h
View File

@@ -1044,6 +1044,7 @@ enum offs_rev {
#define MT_SWDEF_SER_STATS MT_SWDEF(0x040)
#define MT_SWDEF_PLE_STATS MT_SWDEF(0x044)
#define MT_SWDEF_PLE1_STATS MT_SWDEF(0x048)
#define MT_SWDEF_PLE1_MDP_RIOC_HANG_ERR BIT(3)
#define MT_SWDEF_PLE_AMSDU_STATS MT_SWDEF(0x04C)
#define MT_SWDEF_PSE_STATS MT_SWDEF(0x050)
#define MT_SWDEF_PSE1_STATS MT_SWDEF(0x054)