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KVM: arm64: nv: Handle CPACR_EL1 traps
Handle CPACR_EL1 accesses when running a VHE guest. In order to
limit the cost of the emulation, implement it ass a shallow exit.
In the other cases:
- this is a nVHE L1 which will write to memory, and we don't trap
- this is a L2 guest:
* the L1 has CPTR_EL2.TCPAC==0, and the L2 has direct register
access
* the L1 has CPTR_EL2.TCPAC==1, and the L2 will trap, but the
handling is defered to the general handling for forwarding
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20240620164653.1130714-10-oliver.upton@linux.dev
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
This commit is contained in:
committed by
Oliver Upton
parent
1785f020b1
commit
493da2b1c4
@@ -266,10 +266,40 @@ static void kvm_hyp_save_fpsimd_host(struct kvm_vcpu *vcpu)
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__fpsimd_save_state(*host_data_ptr(fpsimd_state));
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}
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static bool kvm_hyp_handle_cpacr_el1(struct kvm_vcpu *vcpu, u64 *exit_code)
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{
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u64 esr = kvm_vcpu_get_esr(vcpu);
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int rt;
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if (!is_hyp_ctxt(vcpu) || esr_sys64_to_sysreg(esr) != SYS_CPACR_EL1)
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return false;
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rt = kvm_vcpu_sys_get_rt(vcpu);
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if ((esr & ESR_ELx_SYS64_ISS_DIR_MASK) == ESR_ELx_SYS64_ISS_DIR_READ) {
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vcpu_set_reg(vcpu, rt, __vcpu_sys_reg(vcpu, CPTR_EL2));
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} else {
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vcpu_write_sys_reg(vcpu, vcpu_get_reg(vcpu, rt), CPTR_EL2);
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__activate_cptr_traps(vcpu);
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}
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__kvm_skip_instr(vcpu);
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return true;
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}
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static bool kvm_hyp_handle_sysreg_vhe(struct kvm_vcpu *vcpu, u64 *exit_code)
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{
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if (kvm_hyp_handle_cpacr_el1(vcpu, exit_code))
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return true;
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return kvm_hyp_handle_sysreg(vcpu, exit_code);
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}
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static const exit_handler_fn hyp_exit_handlers[] = {
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[0 ... ESR_ELx_EC_MAX] = NULL,
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[ESR_ELx_EC_CP15_32] = kvm_hyp_handle_cp15_32,
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[ESR_ELx_EC_SYS64] = kvm_hyp_handle_sysreg,
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[ESR_ELx_EC_SYS64] = kvm_hyp_handle_sysreg_vhe,
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[ESR_ELx_EC_SVE] = kvm_hyp_handle_fpsimd,
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[ESR_ELx_EC_FP_ASIMD] = kvm_hyp_handle_fpsimd,
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[ESR_ELx_EC_IABT_LOW] = kvm_hyp_handle_iabt_low,
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