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pinctrl: add polarfire soc mssio pinctrl driver
On Polarfire SoC, the Bank 2 and Bank 4 IOs connected to the Multiprocessor Subsystem (MSS) are controlled by IOMUX_CRs 1 through 6, which determine what function in routed to them, and MSSIO_BANK#_IO_CFG_CRs, which determine the configuration of each pin. Add a driver for this pin controller, including several custom properties that reflect aspects of the MSS's configuration. Reuse the Kconfig option for iomux0, since controlling MSSIOs without iomux0 routing a function to the MSSIOs in question is pointless, and routing a function to the MSSIOs is equally unhelpful if none of them are configured to make use of that function. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
This commit is contained in:
Conor Dooley
committed by
Linus Walleij
Linus Walleij
parent
6b324d1994
commit
488d704ed7
@@ -9,9 +9,9 @@ config PINCTRL_PIC64GX
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This selects the pinctrl driver for gpio2 on pic64gx.
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config PINCTRL_POLARFIRE_SOC
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bool "Polarfire SoC pinctrl driver"
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bool "Polarfire SoC pinctrl drivers"
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depends on ARCH_MICROCHIP || COMPILE_TEST
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depends on OF
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select GENERIC_PINCONF
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select GENERIC_PINCTRL
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help
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This selects the pinctrl driver for Microchip Polarfire SoC.
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This selects the pinctrl drivers for Microchip Polarfire SoC.
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@@ -2,3 +2,4 @@
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obj-$(CONFIG_PINCTRL_PIC64GX) += pinctrl-pic64gx-gpio2.o
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obj-$(CONFIG_PINCTRL_POLARFIRE_SOC) += pinctrl-mpfs-iomux0.o
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obj-$(CONFIG_PINCTRL_POLARFIRE_SOC) += pinctrl-mpfs-mssio.o
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737
drivers/pinctrl/microchip/pinctrl-mpfs-mssio.c
Normal file
737
drivers/pinctrl/microchip/pinctrl-mpfs-mssio.c
Normal file
@@ -0,0 +1,737 @@
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// SPDX-License-Identifier: GPL-2.0
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#include <linux/bitfield.h>
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#include <linux/module.h>
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#include <linux/mfd/syscon.h>
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#include <linux/mod_devicetable.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/seq_file.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include <linux/pinctrl/pinconf.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinmux.h>
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#include "../core.h"
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#include "../pinctrl-utils.h"
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#include "../pinconf.h"
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#include "../pinmux.h"
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#define MPFS_PINCTRL_PAD_MUX_MASK GENMASK(3, 0)
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#define MPFS_PINCTRL_IOCFG_MASK GENMASK(14, 0)
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#define MPFS_PINCTRL_IBUFMD_MASK GENMASK(2, 0)
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#define MPFS_PINCTRL_DRV_MASK GENMASK(6, 3)
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#define MPFS_PINCTRL_CLAMP BIT(7)
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#define MPFS_PINCTRL_ENHYST BIT(8)
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#define MPFS_PINCTRL_LOCKDN BIT(9)
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#define MPFS_PINCTRL_WPD BIT(10)
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#define MPFS_PINCTRL_WPU BIT(11)
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#define MPFS_PINCTRL_PULL_MASK GENMASK(11, 10)
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#define MPFS_PINCTRL_LP_PERSIST_EN BIT(12)
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#define MPFS_PINCTRL_LP_BYPASS_EN BIT(13)
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#define MPFS_PINCTRL_MSSIO_BANK2_CFG_CR 0x1c4
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#define MPFS_PINCTRL_MSSIO_BANK4_CFG_CR 0x1c8
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#define MPFS_PINCTRL_BANK_VOLTAGE_MASK GENMASK(19, 16)
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#define MPFS_PINCTRL_IOCFG01_REG 0x234
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#define MPFS_PINCTRL_INTER_BANK_GAP 0x4
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#define MPFS_PINCTRL_BANK2_START 14
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#define MPFS_PINCTRL_LOCKDOWN (PIN_CONFIG_END + 1)
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#define MPFS_PINCTRL_CLAMP_DIODE (PIN_CONFIG_END + 2)
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#define MPFS_PINCTRL_IBUFMD (PIN_CONFIG_END + 3)
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struct mpfs_pinctrl_mux_config {
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u8 pin;
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u8 function;
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};
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struct mpfs_pinctrl {
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struct pinctrl_dev *pctrl;
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struct device *dev;
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struct regmap *regmap;
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struct regmap *sysreg_regmap;
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struct mutex mutex;
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struct pinctrl_desc desc;
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};
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struct mpfs_pinctrl_drive_strength {
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u8 ma;
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u8 val;
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};
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struct mpfs_pinctrl_bank_voltage {
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u32 uv;
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u8 val;
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};
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static struct mpfs_pinctrl_drive_strength mpfs_pinctrl_drive_strengths[8] = {
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{ .ma = 2, .val = 2 },
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{ .ma = 4, .val = 3 },
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{ .ma = 6, .val = 4 },
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{ .ma = 8, .val = 5 },
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{ .ma = 10, .val = 6 },
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{ .ma = 12, .val = 7 },
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{ .ma = 16, .val = 10 },
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{ .ma = 20, .val = 12 },
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};
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static struct mpfs_pinctrl_bank_voltage mpfs_pinctrl_bank_voltages[8] = {
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{ .uv = 1200000, .val = 0 },
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{ .uv = 1500000, .val = 2 },
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{ .uv = 1800000, .val = 4 },
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{ .uv = 2500000, .val = 6 },
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{ .uv = 3300000, .val = 8 },
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{ .uv = 0, .val = 0x3f }, // pin unused
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};
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static int mpfs_pinctrl_get_drive_strength_ma(u32 drive_strength)
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{
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size_t num = ARRAY_SIZE(mpfs_pinctrl_drive_strengths);
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for (int i = 0; i < num; i++)
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if (drive_strength == mpfs_pinctrl_drive_strengths[i].val)
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return mpfs_pinctrl_drive_strengths[i].ma;
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return -EINVAL;
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}
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static int mpfs_pinctrl_get_drive_strength_val(u32 drive_strength_ma)
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{
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size_t num = ARRAY_SIZE(mpfs_pinctrl_drive_strengths);
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if (!drive_strength_ma)
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return -EINVAL;
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for (int i = 0; i < num; i++)
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if (drive_strength_ma <= mpfs_pinctrl_drive_strengths[i].ma)
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return mpfs_pinctrl_drive_strengths[i].val;
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return mpfs_pinctrl_drive_strengths[num - 1].val;
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}
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static int mpfs_pinctrl_get_bank_voltage_uv(u32 bank_voltage)
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{
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size_t num = ARRAY_SIZE(mpfs_pinctrl_bank_voltages);
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for (int i = 0; i < num; i++)
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if (bank_voltage == mpfs_pinctrl_bank_voltages[i].val)
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return mpfs_pinctrl_bank_voltages[i].uv;
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return -EINVAL;
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}
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static int mpfs_pinctrl_get_bank_voltage_val(u32 bank_voltage_uv)
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{
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size_t num = ARRAY_SIZE(mpfs_pinctrl_bank_voltages);
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for (int i = 0; i < num; i++)
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if (bank_voltage_uv <= mpfs_pinctrl_bank_voltages[i].uv)
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return mpfs_pinctrl_bank_voltages[i].val;
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return -EINVAL;
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}
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static u32 mpfs_pinctrl_pin_to_bank_voltage(struct mpfs_pinctrl *pctrl, unsigned int pin)
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{
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u32 bank_voltage, val;
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if (pin < MPFS_PINCTRL_BANK2_START)
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regmap_read(pctrl->sysreg_regmap, MPFS_PINCTRL_MSSIO_BANK4_CFG_CR, &val);
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else
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regmap_read(pctrl->sysreg_regmap, MPFS_PINCTRL_MSSIO_BANK2_CFG_CR, &val);
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bank_voltage = FIELD_GET(MPFS_PINCTRL_BANK_VOLTAGE_MASK, val);
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return mpfs_pinctrl_get_bank_voltage_uv(bank_voltage);
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}
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static void mpfs_pinctrl_set_bank_voltage(struct mpfs_pinctrl *pctrl, unsigned int pin,
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u32 bank_voltage)
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{
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u32 val = FIELD_PREP(MPFS_PINCTRL_BANK_VOLTAGE_MASK, bank_voltage);
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if (pin < MPFS_PINCTRL_BANK2_START)
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regmap_assign_bits(pctrl->sysreg_regmap, MPFS_PINCTRL_MSSIO_BANK4_CFG_CR,
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MPFS_PINCTRL_BANK_VOLTAGE_MASK, val);
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else
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regmap_assign_bits(pctrl->sysreg_regmap, MPFS_PINCTRL_MSSIO_BANK2_CFG_CR,
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MPFS_PINCTRL_BANK_VOLTAGE_MASK, val);
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}
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static char *mpfs_pinctrl_function_names[] = {
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"sd",
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"emmc",
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"qspi",
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"spi",
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"usb",
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"uart",
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"i2c",
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"can",
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"mdio",
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"misc",
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"reserved",
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"gpio",
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"fabric test",
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"tied-low",
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"tied-high",
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"tristate"
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};
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static int mpfs_pinctrl_function_map(const char *function)
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{
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size_t num = ARRAY_SIZE(mpfs_pinctrl_function_names);
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for (int i = 0; i < num; i++)
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if (!strcmp(function, mpfs_pinctrl_function_names[i]))
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return i;
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return -EINVAL;
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}
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static const struct pinconf_generic_params mpfs_pinctrl_custom_bindings[] = {
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{ "microchip,clamp-diode", MPFS_PINCTRL_CLAMP_DIODE, 1 },
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{ "microchip,ibufmd", MPFS_PINCTRL_IBUFMD, 0x0 },
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};
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static int mpfs_pinctrl_pin_to_iomux_offset(unsigned int pin)
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{
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int offset;
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switch (pin) {
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case 0 ... 7:
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offset = pin * 4;
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break;
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case 8 ... 13:
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offset = (pin - 8) * 4;
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break;
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case 14 ... 21:
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offset = (pin - 14) * 4;
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break;
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case 22 ... 29:
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offset = (pin - 22) * 4;
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break;
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case 30 ... 37:
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offset = (pin - 30) * 4;
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break;
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default:
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offset = -EINVAL;
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}
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return offset;
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}
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static int mpfs_pinctrl_pin_to_iomux_reg(unsigned int pin)
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{
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int reg;
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switch (pin) {
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case 0 ... 7:
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reg = 0x204;
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break;
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case 8 ... 13:
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reg = 0x208;
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break;
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case 14 ... 21:
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reg = 0x20c;
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break;
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case 22 ... 29:
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reg = 0x210;
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break;
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case 30 ... 37:
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reg = 0x214;
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break;
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default:
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reg = -EINVAL;
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}
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return reg;
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}
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static int mpfs_pinctrl_pin_to_iocfg_reg(unsigned int pin)
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{
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u32 reg = MPFS_PINCTRL_IOCFG01_REG;
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if (pin >= MPFS_PINCTRL_BANK2_START)
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reg += MPFS_PINCTRL_INTER_BANK_GAP;
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// 2 pins per 32-bit register
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reg += (pin / 2) * 0x4;
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return reg;
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}
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static int mpfs_pinctrl_pin_to_iocfg_offset(unsigned int pin)
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{
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return 16 * (pin % 2);
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}
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static void mpfs_pinctrl_dbg_show(struct pinctrl_dev *pctrl_dev, struct seq_file *seq,
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unsigned int pin)
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{
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struct mpfs_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
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u32 func;
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int reg, offset;
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reg = mpfs_pinctrl_pin_to_iomux_reg(pin);
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offset = mpfs_pinctrl_pin_to_iomux_offset(pin);
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seq_printf(seq, "reg: %x, offset: %u ", reg, offset);
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seq_printf(seq, "pin: %u ", pin);
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if (reg < 0 || offset < 0)
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return;
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regmap_read(pctrl->regmap, reg, &func);
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func = (func >> offset) & MPFS_PINCTRL_PAD_MUX_MASK;
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seq_printf(seq, "func: %s (%x)\n", mpfs_pinctrl_function_names[func], func);
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}
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static const struct pinctrl_ops mpfs_pinctrl_ops = {
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.get_groups_count = pinctrl_generic_get_group_count,
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.get_group_name = pinctrl_generic_get_group_name,
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.get_group_pins = pinctrl_generic_get_group_pins,
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.pin_dbg_show = mpfs_pinctrl_dbg_show,
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.dt_node_to_map = pinctrl_generic_pins_function_dt_node_to_map,
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.dt_free_map = pinctrl_utils_free_map,
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};
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static int mpfs_pinctrl_set_pin_func(struct mpfs_pinctrl *pctrl, u8 pin, u8 function)
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{
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struct device *dev = pctrl->dev;
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int reg, offset;
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u32 func, mask;
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reg = mpfs_pinctrl_pin_to_iomux_reg(pin);
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offset = mpfs_pinctrl_pin_to_iomux_offset(pin);
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func = function << offset;
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mask = MPFS_PINCTRL_PAD_MUX_MASK << offset;
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dev_dbg(dev, "Setting pin %u. reg: %x offset %u func %x\n", pin, reg, offset, func);
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if (reg < 0 || offset < 0)
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return -EINVAL;
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regmap_update_bits(pctrl->regmap, reg, mask, func);
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return 0;
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}
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static int mpfs_pinctrl_set_mux(struct pinctrl_dev *pctrl_dev, unsigned int fsel,
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unsigned int gsel)
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{
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struct mpfs_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
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const struct group_desc *group;
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const char **functions;
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group = pinctrl_generic_get_group(pctrl_dev, gsel);
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if (!group)
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return -EINVAL;
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functions = group->data;
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for (int i = 0; i < group->grp.npins; i++) {
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int function;
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function = mpfs_pinctrl_function_map(functions[i]);
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if (function < 0) {
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dev_err(pctrl->dev, "invalid function %s\n", functions[i]);
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return function;
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}
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mpfs_pinctrl_set_pin_func(pctrl, group->grp.pins[i], function);
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}
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return 0;
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}
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static const struct pinmux_ops mpfs_pinctrl_pinmux_ops = {
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.get_functions_count = pinmux_generic_get_function_count,
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.get_function_name = pinmux_generic_get_function_name,
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.get_function_groups = pinmux_generic_get_function_groups,
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.set_mux = mpfs_pinctrl_set_mux,
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};
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static int mpfs_pinctrl_pinconf_get(struct pinctrl_dev *pctrl_dev, unsigned int pin,
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unsigned long *config)
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{
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struct mpfs_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
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int param = pinconf_to_config_param(*config);
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int reg = mpfs_pinctrl_pin_to_iocfg_reg(pin);
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int val;
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u32 arg;
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u8 str;
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regmap_read(pctrl->regmap, reg, &val);
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val = val >> mpfs_pinctrl_pin_to_iocfg_offset(pin);
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val = val & MPFS_PINCTRL_IOCFG_MASK;
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switch (param) {
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case PIN_CONFIG_BIAS_BUS_HOLD:
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if (!(val & MPFS_PINCTRL_WPD))
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return -EINVAL;
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if (!(val & MPFS_PINCTRL_WPU))
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return -EINVAL;
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arg = 1;
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break;
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case PIN_CONFIG_BIAS_PULL_DOWN:
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if (!(val & MPFS_PINCTRL_WPD))
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return -EINVAL;
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if (val & MPFS_PINCTRL_WPU)
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return -EINVAL;
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arg = 1;
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break;
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case PIN_CONFIG_BIAS_PULL_UP:
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if (!(val & MPFS_PINCTRL_WPU))
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return -EINVAL;
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if (val & MPFS_PINCTRL_WPD)
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return -EINVAL;
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arg = 1;
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break;
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case PIN_CONFIG_BIAS_DISABLE:
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if (val & MPFS_PINCTRL_PULL_MASK)
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return -EINVAL;
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arg = 1;
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break;
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case PIN_CONFIG_DRIVE_STRENGTH:
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str = FIELD_GET(MPFS_PINCTRL_DRV_MASK, val);
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if (!str)
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return -EINVAL;
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arg = mpfs_pinctrl_get_drive_strength_ma(str);
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break;
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case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
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if (!FIELD_GET(MPFS_PINCTRL_ENHYST, val))
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return -EINVAL;
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arg = 1;
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break;
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case PIN_CONFIG_PERSIST_STATE:
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if (!FIELD_GET(MPFS_PINCTRL_LP_PERSIST_EN, val))
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return -EINVAL;
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arg = 1;
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break;
|
||||
case PIN_CONFIG_MODE_LOW_POWER:
|
||||
if (!FIELD_GET(MPFS_PINCTRL_LP_BYPASS_EN, val))
|
||||
return -EINVAL;
|
||||
|
||||
arg = 1;
|
||||
break;
|
||||
case PIN_CONFIG_POWER_SOURCE:
|
||||
arg = mpfs_pinctrl_pin_to_bank_voltage(pctrl, pin);
|
||||
break;
|
||||
case MPFS_PINCTRL_CLAMP_DIODE:
|
||||
if (!FIELD_GET(MPFS_PINCTRL_CLAMP, val))
|
||||
return -EINVAL;
|
||||
|
||||
arg = 1;
|
||||
break;
|
||||
case MPFS_PINCTRL_LOCKDOWN:
|
||||
/*
|
||||
* Lockdown is a read-only configuration, it'll get set if the
|
||||
* tamper unit triggers global lockdown and lockdown has been
|
||||
* set in the MSS Configurator for the bank a pin belongs to.
|
||||
*/
|
||||
if (!FIELD_GET(MPFS_PINCTRL_LOCKDN, val))
|
||||
return -EINVAL;
|
||||
|
||||
arg = 1;
|
||||
break;
|
||||
case MPFS_PINCTRL_IBUFMD:
|
||||
arg = FIELD_GET(MPFS_PINCTRL_IBUFMD_MASK, val);
|
||||
break;
|
||||
default:
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
*config = pinconf_to_config_packed(param, arg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mpfs_pinctrl_pinconf_generate_config(struct mpfs_pinctrl *pctrl, unsigned int pin,
|
||||
unsigned long *configs, unsigned int num_configs,
|
||||
u32 *value, u32 *bank_voltage)
|
||||
{
|
||||
u32 val = 0;
|
||||
|
||||
for (int i = 0; i < num_configs; i++) {
|
||||
int param, tmp;
|
||||
u32 arg;
|
||||
|
||||
param = pinconf_to_config_param(configs[i]);
|
||||
arg = pinconf_to_config_argument(configs[i]);
|
||||
|
||||
switch (param) {
|
||||
case PIN_CONFIG_BIAS_BUS_HOLD:
|
||||
val |= MPFS_PINCTRL_PULL_MASK;
|
||||
break;
|
||||
case PIN_CONFIG_BIAS_PULL_DOWN:
|
||||
val &= ~MPFS_PINCTRL_PULL_MASK;
|
||||
val |= MPFS_PINCTRL_WPD;
|
||||
break;
|
||||
case PIN_CONFIG_BIAS_PULL_UP:
|
||||
val &= ~MPFS_PINCTRL_PULL_MASK;
|
||||
val |= MPFS_PINCTRL_WPU;
|
||||
break;
|
||||
case PIN_CONFIG_BIAS_DISABLE:
|
||||
val &= ~MPFS_PINCTRL_PULL_MASK;
|
||||
break;
|
||||
case PIN_CONFIG_DRIVE_STRENGTH:
|
||||
tmp = mpfs_pinctrl_get_drive_strength_val(arg);
|
||||
if (tmp < 0)
|
||||
return tmp;
|
||||
|
||||
val |= FIELD_PREP(MPFS_PINCTRL_DRV_MASK, tmp);
|
||||
break;
|
||||
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
|
||||
if (!arg)
|
||||
break;
|
||||
val |= MPFS_PINCTRL_ENHYST;
|
||||
break;
|
||||
case PIN_CONFIG_PERSIST_STATE:
|
||||
val |= MPFS_PINCTRL_LP_PERSIST_EN;
|
||||
break;
|
||||
case PIN_CONFIG_MODE_LOW_POWER:
|
||||
if (arg)
|
||||
val |= MPFS_PINCTRL_LP_BYPASS_EN;
|
||||
break;
|
||||
case PIN_CONFIG_POWER_SOURCE:
|
||||
tmp = mpfs_pinctrl_get_bank_voltage_val(arg);
|
||||
if (tmp < 0)
|
||||
return tmp;
|
||||
|
||||
*bank_voltage = tmp;
|
||||
break;
|
||||
case MPFS_PINCTRL_CLAMP_DIODE:
|
||||
val |= MPFS_PINCTRL_CLAMP;
|
||||
break;
|
||||
case MPFS_PINCTRL_IBUFMD:
|
||||
val |= FIELD_PREP(MPFS_PINCTRL_IBUFMD_MASK, arg);
|
||||
break;
|
||||
default:
|
||||
dev_err(pctrl->dev, "config %u not supported\n", param);
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
}
|
||||
|
||||
*value = val;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mpfs_pinctrl_pin_set_config(struct mpfs_pinctrl *pctrl, unsigned int pin, u32 config)
|
||||
{
|
||||
int reg = mpfs_pinctrl_pin_to_iocfg_reg(pin);
|
||||
int offset = mpfs_pinctrl_pin_to_iocfg_offset(pin);
|
||||
u32 val, mask;
|
||||
|
||||
mask = MPFS_PINCTRL_IOCFG_MASK << offset;
|
||||
val = config << offset;
|
||||
|
||||
regmap_update_bits(pctrl->regmap, reg, mask, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mpfs_pinctrl_pinconf_set(struct pinctrl_dev *pctrl_dev, unsigned int pin,
|
||||
unsigned long *configs, unsigned int num_configs)
|
||||
{
|
||||
struct mpfs_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
|
||||
u32 val, bank_voltage = 0;
|
||||
int ret;
|
||||
|
||||
ret = mpfs_pinctrl_pinconf_generate_config(pctrl, pin, configs, num_configs, &val,
|
||||
&bank_voltage);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = mpfs_pinctrl_pin_set_config(pctrl, pin, val);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (bank_voltage)
|
||||
mpfs_pinctrl_set_bank_voltage(pctrl, pin, bank_voltage);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mpfs_pinctrl_pinconf_group_set(struct pinctrl_dev *pctrl_dev, unsigned int gsel,
|
||||
unsigned long *configs, unsigned int num_configs)
|
||||
{
|
||||
struct mpfs_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
|
||||
const struct group_desc *group;
|
||||
unsigned int pin;
|
||||
u32 val, bank_voltage = 0;
|
||||
int ret;
|
||||
|
||||
group = pinctrl_generic_get_group(pctrl_dev, gsel);
|
||||
if (!group)
|
||||
return -EINVAL;
|
||||
|
||||
/*
|
||||
* Assume that the first pin in a group is representative, as the mss
|
||||
* configurator doesn't allow splitting a function between two banks.
|
||||
*/
|
||||
pin = group->grp.pins[0];
|
||||
|
||||
ret = mpfs_pinctrl_pinconf_generate_config(pctrl, pin, configs, num_configs, &val,
|
||||
&bank_voltage);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
for (int i = 0; i < group->grp.npins; i++)
|
||||
mpfs_pinctrl_pin_set_config(pctrl, group->grp.pins[i], val);
|
||||
|
||||
if (bank_voltage)
|
||||
mpfs_pinctrl_set_bank_voltage(pctrl, group->grp.pins[0], bank_voltage);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void mpfs_pinctrl_pinconf_dbg_show(struct pinctrl_dev *pctrl_dev, struct seq_file *seq,
|
||||
unsigned int pin)
|
||||
{
|
||||
struct mpfs_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
|
||||
u32 val;
|
||||
int reg, offset;
|
||||
|
||||
reg = mpfs_pinctrl_pin_to_iocfg_reg(pin);
|
||||
offset = mpfs_pinctrl_pin_to_iocfg_offset(pin);
|
||||
|
||||
seq_printf(seq, "pin: %u ", pin);
|
||||
seq_printf(seq, "reg: %x offset: %u ", reg, offset);
|
||||
|
||||
if (reg < 0 || offset < 0)
|
||||
return;
|
||||
|
||||
regmap_read(pctrl->regmap, reg, &val);
|
||||
val = (val & (MPFS_PINCTRL_IOCFG_MASK << offset)) >> offset;
|
||||
seq_printf(seq, "val: %x\n", val);
|
||||
}
|
||||
|
||||
static const struct pinconf_ops mpfs_pinctrl_pinconf_ops = {
|
||||
.pin_config_get = mpfs_pinctrl_pinconf_get,
|
||||
.pin_config_set = mpfs_pinctrl_pinconf_set,
|
||||
.pin_config_group_set = mpfs_pinctrl_pinconf_group_set,
|
||||
.pin_config_dbg_show = mpfs_pinctrl_pinconf_dbg_show,
|
||||
.is_generic = true,
|
||||
};
|
||||
|
||||
static const struct pinctrl_pin_desc mpfs_pinctrl_pins[] = {
|
||||
PINCTRL_PIN(0, "bank 4 0"),
|
||||
PINCTRL_PIN(1, "bank 4 1"),
|
||||
PINCTRL_PIN(2, "bank 4 2"),
|
||||
PINCTRL_PIN(3, "bank 4 3"),
|
||||
PINCTRL_PIN(4, "bank 4 4"),
|
||||
PINCTRL_PIN(5, "bank 4 5"),
|
||||
PINCTRL_PIN(6, "bank 4 6"),
|
||||
PINCTRL_PIN(7, "bank 4 7"),
|
||||
PINCTRL_PIN(8, "bank 4 8"),
|
||||
PINCTRL_PIN(9, "bank 4 9"),
|
||||
PINCTRL_PIN(10, "bank 4 10"),
|
||||
PINCTRL_PIN(11, "bank 4 11"),
|
||||
PINCTRL_PIN(12, "bank 4 12"),
|
||||
PINCTRL_PIN(13, "bank 4 13"),
|
||||
|
||||
PINCTRL_PIN(14, "bank 2 0"),
|
||||
PINCTRL_PIN(15, "bank 2 1"),
|
||||
PINCTRL_PIN(16, "bank 2 2"),
|
||||
PINCTRL_PIN(17, "bank 2 3"),
|
||||
PINCTRL_PIN(18, "bank 2 4"),
|
||||
PINCTRL_PIN(19, "bank 2 5"),
|
||||
PINCTRL_PIN(20, "bank 2 6"),
|
||||
PINCTRL_PIN(21, "bank 2 7"),
|
||||
PINCTRL_PIN(22, "bank 2 8"),
|
||||
PINCTRL_PIN(23, "bank 2 9"),
|
||||
PINCTRL_PIN(24, "bank 2 10"),
|
||||
PINCTRL_PIN(25, "bank 2 11"),
|
||||
PINCTRL_PIN(26, "bank 2 12"),
|
||||
PINCTRL_PIN(27, "bank 2 13"),
|
||||
PINCTRL_PIN(28, "bank 2 14"),
|
||||
PINCTRL_PIN(29, "bank 2 15"),
|
||||
PINCTRL_PIN(30, "bank 2 16"),
|
||||
PINCTRL_PIN(31, "bank 2 17"),
|
||||
PINCTRL_PIN(32, "bank 2 18"),
|
||||
PINCTRL_PIN(33, "bank 2 19"),
|
||||
PINCTRL_PIN(34, "bank 2 20"),
|
||||
PINCTRL_PIN(35, "bank 2 21"),
|
||||
PINCTRL_PIN(36, "bank 2 22"),
|
||||
PINCTRL_PIN(37, "bank 2 23"),
|
||||
};
|
||||
|
||||
static int mpfs_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct mpfs_pinctrl *pctrl;
|
||||
int ret;
|
||||
|
||||
pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
|
||||
if (!pctrl)
|
||||
return -ENOMEM;
|
||||
|
||||
pctrl->regmap = device_node_to_regmap(pdev->dev.parent->of_node);
|
||||
if (IS_ERR(pctrl->regmap))
|
||||
dev_err_probe(dev, PTR_ERR(pctrl->regmap), "Failed to find syscon regmap\n");
|
||||
|
||||
pctrl->sysreg_regmap = syscon_regmap_lookup_by_compatible("microchip,mpfs-sysreg-scb");
|
||||
if (IS_ERR(pctrl->sysreg_regmap))
|
||||
return PTR_ERR(pctrl->sysreg_regmap);
|
||||
|
||||
pctrl->desc.name = dev_name(dev);
|
||||
pctrl->desc.pins = mpfs_pinctrl_pins;
|
||||
pctrl->desc.npins = ARRAY_SIZE(mpfs_pinctrl_pins);
|
||||
pctrl->desc.pctlops = &mpfs_pinctrl_ops;
|
||||
pctrl->desc.pmxops = &mpfs_pinctrl_pinmux_ops;
|
||||
pctrl->desc.confops = &mpfs_pinctrl_pinconf_ops;
|
||||
pctrl->desc.owner = THIS_MODULE;
|
||||
pctrl->desc.num_custom_params = ARRAY_SIZE(mpfs_pinctrl_custom_bindings);
|
||||
pctrl->desc.custom_params = mpfs_pinctrl_custom_bindings;
|
||||
|
||||
pctrl->dev = dev;
|
||||
|
||||
ret = devm_mutex_init(dev, &pctrl->mutex);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
platform_set_drvdata(pdev, pctrl);
|
||||
|
||||
pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl);
|
||||
if (IS_ERR(pctrl->pctrl))
|
||||
return PTR_ERR(pctrl->pctrl);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id mpfs_pinctrl_of_match[] = {
|
||||
{ .compatible = "microchip,mpfs-pinctrl-mssio" },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, mpfs_pinctrl_of_match);
|
||||
|
||||
static struct platform_driver mpfs_pinctrl_driver = {
|
||||
.driver = {
|
||||
.name = "mpfs-pinctrl",
|
||||
.of_match_table = mpfs_pinctrl_of_match,
|
||||
},
|
||||
.probe = mpfs_pinctrl_probe,
|
||||
};
|
||||
module_platform_driver(mpfs_pinctrl_driver);
|
||||
|
||||
MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
|
||||
MODULE_DESCRIPTION("Polarfire SoC mssio pinctrl driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
Reference in New Issue
Block a user