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dt-bindings: perf: Convert apm,xgene-pmu to DT schema
Convert the Applied Micro X-Gene PMU binding to DT schema format. It is a straightforward conversion. Link: https://lore.kernel.org/r/20250812181422.68286-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
This commit is contained in:
Rob Herring (Arm)
142
Documentation/devicetree/bindings/perf/apm,xgene-pmu.yaml
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142
Documentation/devicetree/bindings/perf/apm,xgene-pmu.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/perf/apm,xgene-pmu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: APM X-Gene SoC PMU
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maintainers:
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- Khuong Dinh <khuong@os.amperecomputing.com>
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description: |
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This is APM X-Gene SoC PMU (Performance Monitoring Unit) module.
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The following PMU devices are supported:
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L3C - L3 cache controller
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IOB - IO bridge
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MCB - Memory controller bridge
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MC - Memory controller
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properties:
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compatible:
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enum:
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- apm,xgene-pmu
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- apm,xgene-pmu-v2
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"#address-cells":
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const: 2
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"#size-cells":
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const: 2
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ranges: true
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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regmap-csw:
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$ref: /schemas/types.yaml#/definitions/phandle
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regmap-mcba:
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$ref: /schemas/types.yaml#/definitions/phandle
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regmap-mcbb:
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$ref: /schemas/types.yaml#/definitions/phandle
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required:
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- compatible
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- regmap-csw
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- regmap-mcba
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- regmap-mcbb
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- reg
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- interrupts
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additionalProperties:
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type: object
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additionalProperties: false
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properties:
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compatible:
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enum:
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- apm,xgene-pmu-l3c
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- apm,xgene-pmu-iob
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- apm,xgene-pmu-mcb
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- apm,xgene-pmu-mc
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reg:
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maxItems: 1
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enable-bit-index:
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description:
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Specifies which bit enables the associated resource in MCB or MC subnodes.
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 31
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examples:
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- |
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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pmu@78810000 {
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compatible = "apm,xgene-pmu-v2";
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reg = <0x0 0x78810000 0x0 0x1000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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regmap-csw = <&csw>;
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regmap-mcba = <&mcba>;
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regmap-mcbb = <&mcbb>;
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interrupts = <0x0 0x22 0x4>;
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pmul3c@7e610000 {
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compatible = "apm,xgene-pmu-l3c";
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reg = <0x0 0x7e610000 0x0 0x1000>;
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};
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pmuiob@7e940000 {
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compatible = "apm,xgene-pmu-iob";
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reg = <0x0 0x7e940000 0x0 0x1000>;
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};
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pmucmcb@7e710000 {
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compatible = "apm,xgene-pmu-mcb";
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reg = <0x0 0x7e710000 0x0 0x1000>;
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enable-bit-index = <0>;
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};
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pmucmcb@7e730000 {
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compatible = "apm,xgene-pmu-mcb";
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reg = <0x0 0x7e730000 0x0 0x1000>;
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enable-bit-index = <1>;
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};
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pmucmc@7e810000 {
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compatible = "apm,xgene-pmu-mc";
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reg = <0x0 0x7e810000 0x0 0x1000>;
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enable-bit-index = <0>;
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};
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pmucmc@7e850000 {
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compatible = "apm,xgene-pmu-mc";
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reg = <0x0 0x7e850000 0x0 0x1000>;
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enable-bit-index = <1>;
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};
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pmucmc@7e890000 {
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compatible = "apm,xgene-pmu-mc";
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reg = <0x0 0x7e890000 0x0 0x1000>;
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enable-bit-index = <2>;
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};
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pmucmc@7e8d0000 {
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compatible = "apm,xgene-pmu-mc";
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reg = <0x0 0x7e8d0000 0x0 0x1000>;
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enable-bit-index = <3>;
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};
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};
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};
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@@ -1,112 +0,0 @@
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* APM X-Gene SoC PMU bindings
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This is APM X-Gene SoC PMU (Performance Monitoring Unit) module.
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The following PMU devices are supported:
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L3C - L3 cache controller
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IOB - IO bridge
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MCB - Memory controller bridge
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MC - Memory controller
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The following section describes the SoC PMU DT node binding.
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Required properties:
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- compatible : Shall be "apm,xgene-pmu" for revision 1 or
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"apm,xgene-pmu-v2" for revision 2.
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- regmap-csw : Regmap of the CPU switch fabric (CSW) resource.
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- regmap-mcba : Regmap of the MCB-A (memory bridge) resource.
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- regmap-mcbb : Regmap of the MCB-B (memory bridge) resource.
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- reg : First resource shall be the CPU bus PMU resource.
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- interrupts : Interrupt-specifier for PMU IRQ.
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Required properties for L3C subnode:
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- compatible : Shall be "apm,xgene-pmu-l3c".
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- reg : First resource shall be the L3C PMU resource.
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Required properties for IOB subnode:
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- compatible : Shall be "apm,xgene-pmu-iob".
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- reg : First resource shall be the IOB PMU resource.
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Required properties for MCB subnode:
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- compatible : Shall be "apm,xgene-pmu-mcb".
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- reg : First resource shall be the MCB PMU resource.
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- enable-bit-index : The bit indicates if the according MCB is enabled.
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Required properties for MC subnode:
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- compatible : Shall be "apm,xgene-pmu-mc".
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- reg : First resource shall be the MC PMU resource.
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- enable-bit-index : The bit indicates if the according MC is enabled.
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Example:
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csw: csw@7e200000 {
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compatible = "apm,xgene-csw", "syscon";
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reg = <0x0 0x7e200000 0x0 0x1000>;
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};
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mcba: mcba@7e700000 {
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compatible = "apm,xgene-mcb", "syscon";
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reg = <0x0 0x7e700000 0x0 0x1000>;
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};
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mcbb: mcbb@7e720000 {
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compatible = "apm,xgene-mcb", "syscon";
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reg = <0x0 0x7e720000 0x0 0x1000>;
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};
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pmu: pmu@78810000 {
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compatible = "apm,xgene-pmu-v2";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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regmap-csw = <&csw>;
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regmap-mcba = <&mcba>;
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regmap-mcbb = <&mcbb>;
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reg = <0x0 0x78810000 0x0 0x1000>;
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interrupts = <0x0 0x22 0x4>;
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pmul3c@7e610000 {
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compatible = "apm,xgene-pmu-l3c";
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reg = <0x0 0x7e610000 0x0 0x1000>;
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};
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pmuiob@7e940000 {
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compatible = "apm,xgene-pmu-iob";
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reg = <0x0 0x7e940000 0x0 0x1000>;
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};
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pmucmcb@7e710000 {
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compatible = "apm,xgene-pmu-mcb";
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reg = <0x0 0x7e710000 0x0 0x1000>;
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enable-bit-index = <0>;
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};
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pmucmcb@7e730000 {
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compatible = "apm,xgene-pmu-mcb";
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reg = <0x0 0x7e730000 0x0 0x1000>;
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enable-bit-index = <1>;
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};
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pmucmc@7e810000 {
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compatible = "apm,xgene-pmu-mc";
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reg = <0x0 0x7e810000 0x0 0x1000>;
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enable-bit-index = <0>;
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};
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pmucmc@7e850000 {
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compatible = "apm,xgene-pmu-mc";
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reg = <0x0 0x7e850000 0x0 0x1000>;
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enable-bit-index = <1>;
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};
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pmucmc@7e890000 {
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compatible = "apm,xgene-pmu-mc";
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reg = <0x0 0x7e890000 0x0 0x1000>;
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enable-bit-index = <2>;
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};
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pmucmc@7e8d0000 {
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compatible = "apm,xgene-pmu-mc";
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reg = <0x0 0x7e8d0000 0x0 0x1000>;
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enable-bit-index = <3>;
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};
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};
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@@ -1895,7 +1895,7 @@ APPLIED MICRO (APM) X-GENE SOC PMU
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M: Khuong Dinh <khuong@os.amperecomputing.com>
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S: Supported
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F: Documentation/admin-guide/perf/xgene-pmu.rst
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F: Documentation/devicetree/bindings/perf/apm-xgene-pmu.txt
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F: Documentation/devicetree/bindings/perf/apm,xgene-pmu.yaml
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F: drivers/perf/xgene_pmu.c
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APPLIED MICRO QT2025 PHY DRIVER
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