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Merge branch 'extend-bit-width-in-the-flow-director-of-hns3-driver'

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Jijie Shao says:

====================
extend bit width in the flow director of HNS3 driver

The bit widths of HCLGE_FD_AD_QID and HCLGE_FD_AD_COUNTER_NUM are
increased to support higher specifications.

Note: The hardware already supports the specifications.
====================

Link: https://patch.msgid.link/20260123094756.3718516-1-shaojijie@huawei.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
This commit is contained in:
Paolo Abeni
2026-01-27 13:32:35 +01:00
parent 4c17c01c31 6a0fc0ea61
commit 4778a04c15
2 changed files with 15 additions and 7 deletions
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11
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
View File

@@ -26,6 +26,7 @@ struct hclge_misc_vector {
#define HCLGE_TQP_REG_OFFSET 0x80000
#define HCLGE_TQP_REG_SIZE 0x200
#define HCLGE_FD_COUNTER_MAX_SIZE_DEV_V2 128
#define HCLGE_TQP_MAX_SIZE_DEV_V2 1024
#define HCLGE_TQP_EXT_REG_OFFSET 0x100
@@ -727,11 +728,11 @@ struct hclge_fd_tcam_config_3_cmd {
#define HCLGE_FD_AD_DROP_B 0
#define HCLGE_FD_AD_DIRECT_QID_B 1
#define HCLGE_FD_AD_QID_S 2
#define HCLGE_FD_AD_QID_M GENMASK(11, 2)
#define HCLGE_FD_AD_QID_L_S 2
#define HCLGE_FD_AD_QID_L_M GENMASK(11, 2)
#define HCLGE_FD_AD_USE_COUNTER_B 12
#define HCLGE_FD_AD_COUNTER_NUM_S 13
#define HCLGE_FD_AD_COUNTER_NUM_M GENMASK(19, 13)
#define HCLGE_FD_AD_COUNTER_NUM_L_S 13
#define HCLGE_FD_AD_COUNTER_NUM_L_M GENMASK(19, 13)
#define HCLGE_FD_AD_NXT_STEP_B 20
#define HCLGE_FD_AD_NXT_KEY_S 21
#define HCLGE_FD_AD_NXT_KEY_M GENMASK(25, 21)
@@ -741,6 +742,8 @@ struct hclge_fd_tcam_config_3_cmd {
#define HCLGE_FD_AD_TC_OVRD_B 16
#define HCLGE_FD_AD_TC_SIZE_S 17
#define HCLGE_FD_AD_TC_SIZE_M GENMASK(20, 17)
#define HCLGE_FD_AD_QID_H_B 21
#define HCLGE_FD_AD_COUNTER_NUM_H_B 26
struct hclge_fd_ad_config_cmd {
u8 stage;

11
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
View File

@@ -5679,15 +5679,20 @@ static int hclge_fd_ad_config(struct hclge_dev *hdev, u8 stage, int loc,
hnae3_set_field(ad_data, HCLGE_FD_AD_TC_SIZE_M,
HCLGE_FD_AD_TC_SIZE_S, (u32)action->tc_size);
}
hnae3_set_bit(ad_data, HCLGE_FD_AD_QID_H_B,
action->queue_id >= HCLGE_TQP_MAX_SIZE_DEV_V2 ? 1 : 0);
hnae3_set_bit(ad_data, HCLGE_FD_AD_COUNTER_NUM_H_B,
action->counter_id >= HCLGE_FD_COUNTER_MAX_SIZE_DEV_V2 ?
1 : 0);
ad_data <<= 32;
hnae3_set_bit(ad_data, HCLGE_FD_AD_DROP_B, action->drop_packet);
hnae3_set_bit(ad_data, HCLGE_FD_AD_DIRECT_QID_B,
action->forward_to_direct_queue);
hnae3_set_field(ad_data, HCLGE_FD_AD_QID_M, HCLGE_FD_AD_QID_S,
hnae3_set_field(ad_data, HCLGE_FD_AD_QID_L_M, HCLGE_FD_AD_QID_L_S,
action->queue_id);
hnae3_set_bit(ad_data, HCLGE_FD_AD_USE_COUNTER_B, action->use_counter);
hnae3_set_field(ad_data, HCLGE_FD_AD_COUNTER_NUM_M,
HCLGE_FD_AD_COUNTER_NUM_S, action->counter_id);
hnae3_set_field(ad_data, HCLGE_FD_AD_COUNTER_NUM_L_M,
HCLGE_FD_AD_COUNTER_NUM_L_S, action->counter_id);
hnae3_set_bit(ad_data, HCLGE_FD_AD_NXT_STEP_B, action->use_next_stage);
hnae3_set_field(ad_data, HCLGE_FD_AD_NXT_KEY_M, HCLGE_FD_AD_NXT_KEY_S,
action->next_input_key);