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drm/i915: Make ilk+ pfit regiser unlocked

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The ilk+ panel fitter register are sitting nicely on their own
cacheline, so no need for global serialization via uncore.lock.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220224165103.15682-3-ville.syrjala@linux.intel.com
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
This commit is contained in:
Ville Syrjälä
2022-02-24 18:51:01 +02:00
parent e0c603ef70
commit 46fc66be60
1 changed files with 9 additions and 9 deletions
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18
drivers/gpu/drm/i915/display/intel_display.c
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@@ -1117,13 +1117,13 @@ static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
* e.g. x201.
*/
if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE |
PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe));
intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe));
else
intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE |
PF_FILTER_MED_3x3);
intel_de_write(dev_priv, PF_WIN_POS(pipe), x << 16 | y);
intel_de_write(dev_priv, PF_WIN_SZ(pipe), width << 16 | height);
intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
PF_FILTER_MED_3x3);
intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), x << 16 | y);
intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), width << 16 | height);
}
static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc)
@@ -2023,9 +2023,9 @@ void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state)
if (!old_crtc_state->pch_pfit.enabled)
return;
intel_de_write(dev_priv, PF_CTL(pipe), 0);
intel_de_write(dev_priv, PF_WIN_POS(pipe), 0);
intel_de_write(dev_priv, PF_WIN_SZ(pipe), 0);
intel_de_write_fw(dev_priv, PF_CTL(pipe), 0);
intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 0);
intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 0);
}
static void ilk_crtc_disable(struct intel_atomic_state *state,