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riscv: dts: starfive: fix jh7110 qspi sort order

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Emil pointed out that "13010000 sorts after 12070000". Reshuffle the
entries to be in-order.

Reported-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
Conor Dooley
2023-08-15 11:34:34 +01:00
parent f331eb1f54
commit 466a885182
1 changed files with 19 additions and 19 deletions
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38
arch/riscv/boot/dts/starfive/jh7110.dtsi
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@@ -676,25 +676,6 @@ i2c6: i2c@12060000 {
status = "disabled";
};
qspi: spi@13010000 {
compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";
reg = <0x0 0x13010000 0x0 0x10000>,
<0x0 0x21000000 0x0 0x400000>;
interrupts = <25>;
clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>,
<&syscrg JH7110_SYSCLK_QSPI_AHB>,
<&syscrg JH7110_SYSCLK_QSPI_APB>;
clock-names = "ref", "ahb", "apb";
resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
<&syscrg JH7110_SYSRST_QSPI_AHB>,
<&syscrg JH7110_SYSRST_QSPI_REF>;
reset-names = "qspi", "qspi-ocp", "rstc_ref";
cdns,fifo-depth = <256>;
cdns,fifo-width = <4>;
cdns,trigger-address = <0x0>;
status = "disabled";
};
spi3: spi@12070000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x0 0x12070000 0x0 0x10000>;
@@ -767,6 +748,25 @@ sfctemp: temperature-sensor@120e0000 {
#thermal-sensor-cells = <0>;
};
qspi: spi@13010000 {
compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";
reg = <0x0 0x13010000 0x0 0x10000>,
<0x0 0x21000000 0x0 0x400000>;
interrupts = <25>;
clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>,
<&syscrg JH7110_SYSCLK_QSPI_AHB>,
<&syscrg JH7110_SYSCLK_QSPI_APB>;
clock-names = "ref", "ahb", "apb";
resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
<&syscrg JH7110_SYSRST_QSPI_AHB>,
<&syscrg JH7110_SYSRST_QSPI_REF>;
reset-names = "qspi", "qspi-ocp", "rstc_ref";
cdns,fifo-depth = <256>;
cdns,fifo-width = <4>;
cdns,trigger-address = <0x0>;
status = "disabled";
};
syscrg: clock-controller@13020000 {
compatible = "starfive,jh7110-syscrg";
reg = <0x0 0x13020000 0x0 0x10000>;