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media: atomisp: fix several typos
Running checkpatch.pl codespell logic found several typos at atomisp driver. Fix them using --fix-inline. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
This commit is contained in:
@@ -717,7 +717,7 @@ static int gc0310_init(struct v4l2_subdev *sd)
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pr_info("%s S\n", __func__);
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mutex_lock(&dev->input_lock);
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/* set inital registers */
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/* set initial registers */
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ret = gc0310_write_reg_array(client, gc0310_reset_register);
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/* restore settings */
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@@ -343,7 +343,7 @@ static const struct gc0310_reg gc0310_reset_register[] = {
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/////////////////////////////////////////////////
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{GC0310_8BIT, 0xfe, 0x01},
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{GC0310_8BIT, 0x45, 0xa4}, // 0xf7
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{GC0310_8BIT, 0x46, 0xf0}, // 0xff //f0//sun vaule th
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{GC0310_8BIT, 0x46, 0xf0}, // 0xff //f0//sun value th
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{GC0310_8BIT, 0x48, 0x03}, //sun mode
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{GC0310_8BIT, 0x4f, 0x60}, //sun_clamp
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{GC0310_8BIT, 0xfe, 0x00},
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@@ -275,10 +275,10 @@ struct mt9m114_device {
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unsigned int agc;
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unsigned int awb;
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unsigned int aec;
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/* extention SENSOR version 2 */
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/* extension SENSOR version 2 */
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unsigned int cie_profile;
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/* extention SENSOR version 3 */
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/* extension SENSOR version 3 */
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unsigned int flicker_freq;
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/* extension SENSOR version 4 */
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@@ -4261,7 +4261,7 @@ int atomisp_set_parameters(struct video_device *vdev,
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#endif
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if (arg->per_frame_setting && !atomisp_is_vf_pipe(pipe)) {
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/*
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* Per-frame setting enabled, we allocate a new paramter
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* Per-frame setting enabled, we allocate a new parameter
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* buffer to cache the parameters and only when frame buffers
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* are ready, the parameters will be set to CSS.
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* per-frame setting only works for the main output frame.
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@@ -2574,7 +2574,7 @@ static void __configure_preview_pp_input(struct atomisp_sub_device *asd,
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*
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* Rule for Bayer Downscaling: support factor 2, 1.5 and 1.25
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* Rule for YUV Decimation: support factor 2, 4
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* Rule for YUV Downscaling: arbitary value below 2
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* Rule for YUV Downscaling: arbitrary value below 2
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*
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* General rule of factor distribution among these stages:
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* 1: try to do Bayer downscaling first if not in online mode.
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@@ -67,7 +67,7 @@ static int csi2_enum_mbus_code(struct v4l2_subdev *sd,
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* @fh : V4L2 subdev file handle
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* @pad: pad num
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* @fmt: pointer to v4l2 format structure
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* return -EINVAL or zero on sucess
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* return -EINVAL or zero on success
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*/
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static int csi2_get_format(struct v4l2_subdev *sd,
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struct v4l2_subdev_pad_config *cfg,
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@@ -270,7 +270,7 @@ int atomisp_q_video_buffers_to_css(struct atomisp_sub_device *asd,
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* Because the camera halv3 can't ensure to set zoom
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* region to per_frame setting and global setting at
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* same time and only set zoom region to pre_frame
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* setting now.so when the pre_frame setting inculde
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* setting now.so when the pre_frame setting include
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* zoom region,I will set it to global setting.
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*/
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if (param->params.update_flag.dz_config &&
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@@ -239,7 +239,7 @@ struct atomisp_device {
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*/
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struct atomisp_sub_device *asd;
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/*
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* this will be assiged dyanamically.
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* this will be assigned dyanamically.
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* For Merr/BTY(ISP2400), 2 streams are supported.
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*/
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unsigned int num_of_streams;
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@@ -2492,7 +2492,7 @@ static int atomisp_g_ext_ctrls(struct file *file, void *fh,
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struct v4l2_control ctrl;
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int i, ret = 0;
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/* input_lock is not need for the Camera releated IOCTLs
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/* input_lock is not need for the Camera related IOCTLs
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* The input_lock downgrade the FPS of 3A*/
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ret = atomisp_camera_g_ext_ctrls(file, fh, c);
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if (ret != -EINVAL)
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@@ -2618,7 +2618,7 @@ static int atomisp_s_ext_ctrls(struct file *file, void *fh,
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struct v4l2_control ctrl;
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int i, ret = 0;
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/* input_lock is not need for the Camera releated IOCTLs
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/* input_lock is not need for the Camera related IOCTLs
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* The input_lock downgrade the FPS of 3A*/
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ret = atomisp_camera_s_ext_ctrls(file, fh, c);
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if (ret != -EINVAL)
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@@ -1002,7 +1002,7 @@ static const struct v4l2_ctrl_config ctrl_enable_raw_buffer_lock = {
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/*
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* Control to disable digital zoom of the whole stream
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*
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* When it is true, pipe configuation enable_dz will be set to false.
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* When it is true, pipe configuration enable_dz will be set to false.
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* This can help get a better performance by disabling pp binary.
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*
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* Note: Make sure set this configuration before creating stream.
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@@ -365,7 +365,7 @@ extern uint32_t ia_css_circbuf_peek_from_start(
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* but new elements should be added at the end to existing
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* cb element array which if of max_size >= new size
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*
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* @return true on succesfully increasing the size
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* @return true on successfully increasing the size
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* false on failure
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*/
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extern bool ia_css_circbuf_increase_size(
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@@ -63,7 +63,7 @@
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#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH8 15 /* 00 1111 Generic Short Packet Code 8 */
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#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8_CSPS 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */
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#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_10_CSPS 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */
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/* used reseved mipi positions for these */
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/* used reserved mipi positions for these */
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#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW16 46
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#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18 47
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#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18_2 37
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@@ -68,7 +68,7 @@
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/* */
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#define _PXG_SYNG_PAUSE_CYCLES 0
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/* Subblock ID's */
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#define _PXG_DISBALE_IDX 0
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#define _PXG_DISABLE_IDX 0
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#define _PXG_PRBS_IDX 0
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#define _PXG_TPG_IDX 1
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#define _PXG_SYNG_IDX 2
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@@ -63,7 +63,7 @@
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#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH8 15 /* 00 1111 Generic Short Packet Code 8 */
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#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8_CSPS 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */
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#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_10_CSPS 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */
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/* used reseved mipi positions for these */
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/* used reserved mipi positions for these */
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#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW16 46
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#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18 47
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#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18_2 37
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@@ -63,7 +63,7 @@
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#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH8 15 /* 00 1111 Generic Short Packet Code 8 */
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#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8_CSPS 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */
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#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_10_CSPS 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */
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/* used reseved mipi positions for these */
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/* used reserved mipi positions for these */
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#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW16 46
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#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18 47
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#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18_2 37
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@@ -32,8 +32,8 @@
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* The DMA port definition for the input system
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* 2401 DMA is the duplication of the DMA port
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* definition for the CSS system DMA. It is duplicated
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* here just as the temporal step before the device libary
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* is available. The device libary is suppose to provide
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* here just as the temporal step before the device library
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* is available. The device library is suppose to provide
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* the capability of reusing the control interface of the
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* same device prototypes. The refactor team will work on
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* this, right?
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@@ -55,8 +55,8 @@ struct isys2401_dma_port_cfg_s {
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* The DMA device definition for the input system
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* 2401 DMA is the duplicattion of the DMA device
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* definition for the CSS system DMA. It is duplicated
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* here just as the temporal step before the device libary
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* is available. The device libary is suppose to provide
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* here just as the temporal step before the device library
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* is available. The device library is suppose to provide
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* the capability of reusing the control interface of the
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* same device prototypes. The refactor team will work on
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* this, right?
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@@ -451,7 +451,7 @@ enum ia_css_isp_memories {
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N_IA_CSS_MEMORIES
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};
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#define IA_CSS_NUM_MEMORIES 9
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/* For driver compatability */
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/* For driver compatibility */
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#define N_IA_CSS_ISP_MEMORIES IA_CSS_NUM_MEMORIES
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#define IA_CSS_NUM_ISP_MEMORIES IA_CSS_NUM_MEMORIES
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@@ -63,7 +63,7 @@
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#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH8 15 /* 00 1111 Generic Short Packet Code 8 */
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#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8_CSPS 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */
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#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_10_CSPS 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */
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/* used reseved mipi positions for these */
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/* used reserved mipi positions for these */
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#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW16 46
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#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18 47
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#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18_2 37
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@@ -317,7 +317,7 @@ enum ia_css_isp_memories {
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N_IA_CSS_MEMORIES
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};
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#define IA_CSS_NUM_MEMORIES 9
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/* For driver compatability */
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/* For driver compatibility */
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#define N_IA_CSS_ISP_MEMORIES IA_CSS_NUM_MEMORIES
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#define IA_CSS_NUM_ISP_MEMORIES IA_CSS_NUM_MEMORIES
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@@ -88,7 +88,7 @@
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#ifndef PIPE_GENERATION
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/* Deprecated OP___assert, this is still used in ~1000 places
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* in the code. This will be removed over time.
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* The implemenation for the pipe generation tool is in see support.isp.h */
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* The implementation for the pipe generation tool is in see support.isp.h */
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#define OP___assert(cnd) assert(cnd)
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static inline void compile_time_assert (unsigned cond)
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@@ -85,7 +85,7 @@ extern void csi_rx_be_ctrl_dump_state(
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* Load the value of the register of the csi rx fe.
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*
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* @param[in] ID The global unique ID for the ibuf-controller instance.
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* @param[in] reg The offet address of the register.
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* @param[in] reg The offset address of the register.
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*
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* @return the value of the register.
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*/
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@@ -97,7 +97,7 @@ extern hrt_data csi_rx_fe_ctrl_reg_load(
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* Store a value to the registe of the csi rx fe.
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*
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* @param[in] ID The global unique ID for the ibuf-controller instance.
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* @param[in] reg The offet address of the register.
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* @param[in] reg The offset address of the register.
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* @param[in] value The value to be stored.
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*
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*/
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@@ -110,7 +110,7 @@ extern void csi_rx_fe_ctrl_reg_store(
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* Load the value of the register of the csirx be.
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*
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* @param[in] ID The global unique ID for the ibuf-controller instance.
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* @param[in] reg The offet address of the register.
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* @param[in] reg The offset address of the register.
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*
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* @return the value of the register.
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*/
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@@ -122,7 +122,7 @@ extern hrt_data csi_rx_be_ctrl_reg_load(
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* Store a value to the registe of the csi rx be.
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*
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* @param[in] ID The global unique ID for the ibuf-controller instance.
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* @param[in] reg The offet address of the register.
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* @param[in] reg The offset address of the register.
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* @param[in] value The value to be stored.
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*
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*/
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@@ -66,7 +66,7 @@ STORAGE_CLASS_IBUF_CTRL_H void ibuf_ctrl_dump_state(
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* Load the value of the register of the ibuf-controller.
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*
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* @param[in] ID The global unique ID for the ibuf-controller instance.
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* @param[in] reg The offet address of the register.
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* @param[in] reg The offset address of the register.
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*
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* @return the value of the register.
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*/
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@@ -79,7 +79,7 @@ STORAGE_CLASS_IBUF_CTRL_H hrt_data ibuf_ctrl_reg_load(
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* Store a value to the registe of the ibuf-controller.
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*
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* @param[in] ID The global unique ID for the ibuf-controller instance.
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* @param[in] reg The offet address of the register.
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* @param[in] reg The offset address of the register.
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* @param[in] value The value to be stored.
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*
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*/
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@@ -56,7 +56,7 @@ STORAGE_CLASS_STREAM2MMIO_H void stream2mmio_get_sid_state(
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*
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* @param[in] ID The global unique ID for the stream2mmio-controller instance.
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* @param[in] sid_id The SID in question.
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* @param[in] reg_idx The offet address of the register.
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* @param[in] reg_idx The offset address of the register.
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*
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* @return the value of the register.
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*/
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@@ -88,7 +88,7 @@ STORAGE_CLASS_STREAM2MMIO_H void stream2mmio_dump_state(
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* Store a value to the registe of the stream2mmio-controller.
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*
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* @param[in] ID The global unique ID for the stream2mmio-controller instance.
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* @param[in] reg The offet address of the register.
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* @param[in] reg The offset address of the register.
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* @param[in] value The value to be stored.
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*
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*/
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@@ -53,7 +53,7 @@ STORAGE_CLASS_PIXELGEN_H void pixelgen_ctrl_dump_state(
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* Load the value of the register of the pixelgen
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*
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* @param[in] ID The global unique ID for the pixelgen instance.
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* @param[in] reg The offet address of the register.
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* @param[in] reg The offset address of the register.
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*
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* @return the value of the register.
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*/
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@@ -65,7 +65,7 @@ STORAGE_CLASS_PIXELGEN_H hrt_data pixelgen_ctrl_reg_load(
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* Store a value to the registe of the pixelgen
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*
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* @param[in] ID The global unique ID for the pixelgen.
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* @param[in] reg The offet address of the register.
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* @param[in] reg The offset address of the register.
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* @param[in] value The value to be stored.
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*
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*/
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@@ -128,7 +128,7 @@ extern hrt_vaddress mmgr_alloc_attr(const size_t size, const uint16_t attribute)
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\param attribute[in] Bit vector specifying the properties
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of the allocation
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\param context Pointer of a context provided by
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client/driver for additonal parameters
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client/driver for additional parameters
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needed by the implementation
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\Note
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This interface is tentative, limited to the desired function
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@@ -47,9 +47,9 @@ enum ia_css_err {
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enum ia_css_fw_warning {
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IA_CSS_FW_WARNING_NONE,
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IA_CSS_FW_WARNING_ISYS_QUEUE_FULL, /* < CSS system delayed because of insufficient space in the ISys queue.
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This warning can be avoided by de-queing ISYS buffers more timely. */
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This warning can be avoided by de-queuing ISYS buffers more timely. */
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IA_CSS_FW_WARNING_PSYS_QUEUE_FULL, /* < CSS system delayed because of insufficient space in the PSys queue.
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This warning can be avoided by de-queing PSYS buffers more timely. */
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This warning can be avoided by de-queuing PSYS buffers more timely. */
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IA_CSS_FW_WARNING_CIRCBUF_ALL_LOCKED, /* < CSS system delayed because of insufficient available buffers.
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This warning can be avoided by unlocking locked frame-buffers more timely. */
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IA_CSS_FW_WARNING_EXP_ID_LOCKED, /* < Exposure ID skipped because the frame associated to it was still locked.
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@@ -308,7 +308,7 @@ ia_css_pipe_set_isp_config(struct ia_css_pipe *pipe,
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* @param[in] and_mask Binary or of enum ia_css_event_irq_mask_type. An event
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IRQ for the Host is only raised after all pipe related
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events have occurred at least once for all the active
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pipes. Events are remembered and don't need to occure
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pipes. Events are remembered and don't need to occurred
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at the same moment in time. There is no control over
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the order of these events. Once an IRQ has been raised
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all remembered events are reset.
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@@ -125,7 +125,7 @@ struct ia_css_stream_config {
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bool pack_raw_pixels; /** Pack pixels in the raw buffers */
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bool continuous; /** Use SP copy feature to continuously capture frames
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to system memory and run pipes in offline mode */
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bool disable_cont_viewfinder; /** disable continous viewfinder for ZSL use case */
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bool disable_cont_viewfinder; /** disable continuous viewfinder for ZSL use case */
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int32_t flash_gpio_pin; /** pin on which the flash is connected, -1 for no flash */
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int left_padding; /** The number of input-formatter left-paddings, -1 for default from binary.*/
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struct ia_css_mipi_buffer_config mipi_buffer_config; /** mipi buffer configuration */
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@@ -45,7 +45,7 @@ static int ctc2_slope(int y1, int y0, int x1, int x0)
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int dy_shift = dy << shift_val;
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int slope, dydx;
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||||
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/*Protection for paramater values, & avoiding zero divisions*/
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/*Protection for parameter values, & avoiding zero divisions*/
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assert(y0 >= 0 && y0 <= max_slope);
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assert(y1 >= 0 && y1 <= max_slope);
|
||||
assert(x0 >= 0 && x0 <= max_slope);
|
||||
@@ -80,7 +80,7 @@ void ia_css_ctc2_vmem_encode(struct ia_css_isp_ctc2_vmem_params *to,
|
||||
{
|
||||
unsigned i, j;
|
||||
const unsigned shffl_blck = 4;
|
||||
const unsigned lenght_zeros = 11;
|
||||
const unsigned length_zeros = 11;
|
||||
short dydx0, dydx1, dydx2, dydx3, dydx4;
|
||||
|
||||
(void)size;
|
||||
@@ -127,7 +127,7 @@ void ia_css_ctc2_vmem_encode(struct ia_css_isp_ctc2_vmem_params *to,
|
||||
to->e_y_slope[0][(i << shffl_blck) + 3] = dydx3;
|
||||
to->e_y_slope[0][(i << shffl_blck) + 4] = dydx4;
|
||||
|
||||
for (j = 0; j < lenght_zeros; j++) {
|
||||
for (j = 0; j < length_zeros; j++) {
|
||||
to->y_x[0][(i << shffl_blck) + 5 + j] = 0;
|
||||
to->y_y[0][(i << shffl_blck) + 5 + j] = 0;
|
||||
to->e_y_slope[0][(i << shffl_blck)+ 5 + j] = 0;
|
||||
|
||||
@@ -21,7 +21,7 @@
|
||||
|
||||
/**
|
||||
* \brief HDR Irradiance Parameters
|
||||
* \detail Currently HDR paramters are used only for testing purposes
|
||||
* \detail Currently HDR parameters are used only for testing purposes
|
||||
*/
|
||||
struct ia_css_hdr_irradiance_params {
|
||||
int test_irr; /** Test parameter */
|
||||
@@ -36,7 +36,7 @@ struct ia_css_hdr_irradiance_params {
|
||||
|
||||
/**
|
||||
* \brief HDR Deghosting Parameters
|
||||
* \detail Currently HDR paramters are used only for testing purposes
|
||||
* \detail Currently HDR parameters are used only for testing purposes
|
||||
*/
|
||||
struct ia_css_hdr_deghost_params {
|
||||
int test_deg; /** Test parameter */
|
||||
@@ -44,7 +44,7 @@ struct ia_css_hdr_deghost_params {
|
||||
|
||||
/**
|
||||
* \brief HDR Exclusion Parameters
|
||||
* \detail Currently HDR paramters are used only for testing purposes
|
||||
* \detail Currently HDR parameters are used only for testing purposes
|
||||
*/
|
||||
struct ia_css_hdr_exclusion_params {
|
||||
int test_excl; /** Test parameter */
|
||||
@@ -52,11 +52,11 @@ struct ia_css_hdr_exclusion_params {
|
||||
|
||||
/**
|
||||
* \brief HDR public paramterers.
|
||||
* \details Struct with all paramters for HDR that can be seet from
|
||||
* the CSS API. Currenly, only test paramters are defined.
|
||||
* \details Struct with all parameters for HDR that can be seet from
|
||||
* the CSS API. Currenly, only test parameters are defined.
|
||||
*/
|
||||
struct ia_css_hdr_config {
|
||||
struct ia_css_hdr_irradiance_params irradiance; /** HDR irradiance paramaters */
|
||||
struct ia_css_hdr_irradiance_params irradiance; /** HDR irradiance parameters */
|
||||
struct ia_css_hdr_deghost_params deghost; /** HDR deghosting parameters */
|
||||
struct ia_css_hdr_exclusion_params exclusion; /** HDR exclusion parameters */
|
||||
};
|
||||
|
||||
@@ -1805,7 +1805,7 @@ unsigned
|
||||
ia_css_binary_max_vf_width(void)
|
||||
{
|
||||
/* This is (should be) true for IPU1 and IPU2 */
|
||||
/* For IPU3 (SkyCam) this pointer is guarenteed to be NULL simply because such a binary does not exist */
|
||||
/* For IPU3 (SkyCam) this pointer is guaranteed to be NULL simply because such a binary does not exist */
|
||||
if (binary_infos[IA_CSS_BINARY_MODE_VF_PP])
|
||||
return binary_infos[IA_CSS_BINARY_MODE_VF_PP]->sp.output.max_width;
|
||||
return 0;
|
||||
|
||||
@@ -71,7 +71,7 @@ void ia_css_queue_map(
|
||||
|
||||
|
||||
/**
|
||||
* @brief Initilize buffer type to a queue id mapping
|
||||
* @brief Initialize buffer type to a queue id mapping
|
||||
* @return none
|
||||
*/
|
||||
void ia_css_queue_map_init(void);
|
||||
|
||||
@@ -2872,7 +2872,7 @@ ia_css_debug_pipe_graph_dump_stage(
|
||||
if (l <= ENABLE_LINE_MAX_LENGTH) {
|
||||
/* The 2nd line fits */
|
||||
/* we cannot use ei as argument because
|
||||
* it is not guarenteed dword aligned
|
||||
* it is not guaranteed dword aligned
|
||||
*/
|
||||
strncpy_s(enable_info2,
|
||||
sizeof(enable_info2),
|
||||
@@ -2896,7 +2896,7 @@ ia_css_debug_pipe_graph_dump_stage(
|
||||
if (l <= ENABLE_LINE_MAX_LENGTH) {
|
||||
/* The 3rd line fits */
|
||||
/* we cannot use ei as argument because
|
||||
* it is not guarenteed dword aligned
|
||||
* it is not guaranteed dword aligned
|
||||
*/
|
||||
strcpy_s(enable_info3,
|
||||
sizeof(enable_info3), ei);
|
||||
|
||||
@@ -917,7 +917,7 @@ ia_css_elems_bytes_from_info(const struct ia_css_frame_info *info)
|
||||
return 2; /* bytes per pixel */
|
||||
/* Note: Essentially NV12_16 is a 2 bytes per pixel format, this return value is used
|
||||
* to configure DMA for the output buffer,
|
||||
* At least in SKC this data is overwriten by isp_output_init.sp.c except for elements(elems),
|
||||
* At least in SKC this data is overwritten by isp_output_init.sp.c except for elements(elems),
|
||||
* which is configured from this return value,
|
||||
* NV12_16 is implemented by a double buffer of 8 bit elements hence elems should be configured as 8 */
|
||||
if (info->format == IA_CSS_FRAME_FORMAT_NV12_16)
|
||||
|
||||
@@ -215,7 +215,7 @@ enum ia_css_err ia_css_pipeline_get_stage_from_fw(struct ia_css_pipeline *pipeli
|
||||
uint32_t fw_handle,
|
||||
struct ia_css_pipeline_stage **stage);
|
||||
|
||||
/* @brief Gets the Firmware handle correponding the stage num from the pipeline
|
||||
/* @brief Gets the Firmware handle corresponding the stage num from the pipeline
|
||||
*
|
||||
* @param[in] pipeline
|
||||
* @param[in] stage_num
|
||||
|
||||
@@ -1259,7 +1259,7 @@ static void print_pc_histo(char *core_name, struct sh_css_pc_histogram *hist)
|
||||
return;
|
||||
|
||||
sh_css_print("%s histogram length = %d\n", core_name, hist->length);
|
||||
sh_css_print("%s PC\trun\tstall\n", core_name);
|
||||
sh_css_print("%s PC\turn\tstall\n", core_name);
|
||||
|
||||
for (i = 0; i < hist->length; i++) {
|
||||
if ((hist->run[i] == 0) && (hist->run[i] == hist->stall[i]))
|
||||
|
||||
@@ -335,7 +335,7 @@ struct sh_css_sp_debug_state {
|
||||
#define SH_CSS_SP_DBG_NR_OF_TRACES (1)
|
||||
#define SH_CSS_SP_DBG_TRACE_DEPTH (40)
|
||||
#else
|
||||
/* E.g. if you like seperate traces for 4 threads */
|
||||
/* E.g. if you like separate traces for 4 threads */
|
||||
#define SH_CSS_SP_DBG_NR_OF_TRACES (4)
|
||||
#define SH_CSS_SP_DBG_TRACE_DEPTH (10)
|
||||
#endif
|
||||
@@ -373,7 +373,7 @@ struct sh_css_sp_debug_command {
|
||||
* Bit 31...24: unused.
|
||||
* Bit 23...16: unused.
|
||||
* Bit 15...08: reading-request enabling bits for DMA channel 7..0
|
||||
* Bit 07...00: writing-reqeust enabling bits for DMA channel 7..0
|
||||
* Bit 07...00: writing-request enabling bits for DMA channel 7..0
|
||||
*
|
||||
* For example, "0...0 0...0 11111011 11111101" indicates that the
|
||||
* writing request through DMA Channel 1 and the reading request
|
||||
@@ -584,11 +584,11 @@ struct sh_css_sp_pipeline {
|
||||
/*
|
||||
* The first frames (with comment Dynamic) can be dynamic or static
|
||||
* The other frames (ref_in and below) can only be static
|
||||
* Static means that the data addres will not change during the life time
|
||||
* Static means that the data address will not change during the life time
|
||||
* of the associated pipe. Dynamic means that the data address can
|
||||
* change with every (frame) iteration of the associated pipe
|
||||
*
|
||||
* s3a and dis are now also dynamic but (stil) handled seperately
|
||||
* s3a and dis are now also dynamic but (stil) handled separately
|
||||
*/
|
||||
#define SH_CSS_NUM_DYNAMIC_FRAME_IDS (3)
|
||||
|
||||
@@ -608,7 +608,7 @@ struct ia_css_frames_sp {
|
||||
/* Information for a single pipeline stage for an ISP */
|
||||
struct sh_css_isp_stage {
|
||||
/*
|
||||
* For compatability and portabilty, only types
|
||||
* For compatibility and portabilty, only types
|
||||
* from "stdint.h" are allowed
|
||||
*
|
||||
* Use of "enum" and "bool" is prohibited
|
||||
@@ -624,7 +624,7 @@ struct sh_css_isp_stage {
|
||||
/* Information for a single pipeline stage */
|
||||
struct sh_css_sp_stage {
|
||||
/*
|
||||
* For compatability and portabilty, only types
|
||||
* For compatibility and portabilty, only types
|
||||
* from "stdint.h" are allowed
|
||||
*
|
||||
* Use of "enum" and "bool" is prohibited
|
||||
@@ -686,7 +686,7 @@ struct sh_css_sp_stage {
|
||||
* Note:
|
||||
* Group all host initialized SP variables into this struct.
|
||||
* This is initialized every stage through dma.
|
||||
* The stage part itself is transfered through sh_css_sp_stage.
|
||||
* The stage part itself is transferred through sh_css_sp_stage.
|
||||
*/
|
||||
struct sh_css_sp_group {
|
||||
struct sh_css_sp_config config;
|
||||
@@ -840,7 +840,7 @@ struct sh_css_event_irq_mask {
|
||||
struct host_sp_communication {
|
||||
/*
|
||||
* Don't use enum host2sp_commands, because the sizeof an enum is
|
||||
* compiler dependant and thus non-portable
|
||||
* compiler dependent and thus non-portable
|
||||
*/
|
||||
uint32_t host2sp_command;
|
||||
|
||||
|
||||
@@ -3828,7 +3828,7 @@ sh_css_param_update_isp_params(struct ia_css_pipe *curr_pipe,
|
||||
cur_map_size = ¶ms->pipe_ddr_ptrs_size[pipeline->pipe_id];
|
||||
|
||||
/* TODO: Normally, zoom and motion parameters shouldn't
|
||||
* be part of "isp_params" as it is resolution/pipe dependant
|
||||
* be part of "isp_params" as it is resolution/pipe dependent
|
||||
* Therefore, move the zoom config elsewhere (e.g. shading
|
||||
* table can be taken as an example! @GC
|
||||
* */
|
||||
|
||||
@@ -1403,7 +1403,7 @@ sh_css_read_host2sp_command(void)
|
||||
|
||||
/*
|
||||
* Frame data is no longer part of the sp_stage structure but part of a
|
||||
* seperate structure. The aim is to make the sp_data struct static
|
||||
* separate structure. The aim is to make the sp_data struct static
|
||||
* (it defines a pipeline) and that the dynamic (per frame) data is stored
|
||||
* separetly.
|
||||
*
|
||||
@@ -1422,7 +1422,7 @@ sh_css_init_host2sp_frame_data(void)
|
||||
/*
|
||||
* rvanimme: don't clean it to save static frame info line ref_in
|
||||
* ref_out, and tnr_frames. Once this static data is in a
|
||||
* seperate data struct, this may be enable (but still, there is
|
||||
* separate data struct, this may be enable (but still, there is
|
||||
* no need for it)
|
||||
*/
|
||||
}
|
||||
|
||||
@@ -1516,7 +1516,7 @@ int hmm_bo_mmap(struct vm_area_struct *vma, struct hmm_buffer_object *bo)
|
||||
vma->vm_flags |= VM_IO|VM_DONTEXPAND|VM_DONTDUMP;
|
||||
|
||||
/*
|
||||
* call hmm_bo_vm_open explictly.
|
||||
* call hmm_bo_vm_open explicitly.
|
||||
*/
|
||||
hmm_bo_vm_open(vma);
|
||||
|
||||
|
||||
@@ -136,7 +136,7 @@ int isp_mmu_init(struct isp_mmu *mmu, struct isp_mmu_client *driver);
|
||||
void isp_mmu_exit(struct isp_mmu *mmu);
|
||||
|
||||
/*
|
||||
* setup/remove address mapping for pgnr continous physical pages
|
||||
* setup/remove address mapping for pgnr continuous physical pages
|
||||
* and isp_virt.
|
||||
*
|
||||
* map/unmap is mutex lock protected, and caller does not have
|
||||
|
||||
@@ -168,7 +168,7 @@ static void mmu_unmap_l2_pte_error(struct isp_mmu *mmu,
|
||||
phys_addr_t l2_pt, unsigned int l2_idx,
|
||||
unsigned int isp_virt, unsigned int pte)
|
||||
{
|
||||
dev_err(atomisp_dev, "unmap unvalid L2 pte:\n\n"
|
||||
dev_err(atomisp_dev, "unmap invalid L2 pte:\n\n"
|
||||
"\tL1 PT: virt = %p, phys = 0x%llx, "
|
||||
"idx = %d\n"
|
||||
"\tL2 PT: virt = %p, phys = 0x%llx, "
|
||||
@@ -185,7 +185,7 @@ static void mmu_unmap_l1_pte_error(struct isp_mmu *mmu,
|
||||
phys_addr_t l1_pt, unsigned int l1_idx,
|
||||
unsigned int isp_virt, unsigned int pte)
|
||||
{
|
||||
dev_err(atomisp_dev, "unmap unvalid L1 pte (L2 PT):\n\n"
|
||||
dev_err(atomisp_dev, "unmap invalid L1 pte (L2 PT):\n\n"
|
||||
"\tL1 PT: virt = %p, phys = 0x%llx, "
|
||||
"idx = %d\n"
|
||||
"\tisp_virt = 0x%x, l1_pte(L2 PT) = 0x%x\n",
|
||||
@@ -196,7 +196,7 @@ static void mmu_unmap_l1_pte_error(struct isp_mmu *mmu,
|
||||
|
||||
static void mmu_unmap_l1_pt_error(struct isp_mmu *mmu, unsigned int pte)
|
||||
{
|
||||
dev_err(atomisp_dev, "unmap unvalid L1PT:\n\n"
|
||||
dev_err(atomisp_dev, "unmap invalid L1PT:\n\n"
|
||||
"L1PT = 0x%x\n", (unsigned int)pte);
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user