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arm64: dts: mediatek: mt8188: Add Global Command Engine mailboxes

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In preparation for adding multimedia nodes and power domains, add
support for the two Global Command Engine (GCE) mailboxes found in
this SoC.

Link: https://lore.kernel.org/r/20240527093908.97574-3-angelogioacchino.delregno@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
This commit is contained in:
AngeloGioacchino Del Regno
2024-05-27 11:39:05 +02:00
parent b220332f98
commit 45682a4fff
1 changed files with 17 additions and 0 deletions
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17
arch/arm64/boot/dts/mediatek/mt8188.dtsi
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@@ -8,6 +8,7 @@
#include <dt-bindings/clock/mediatek,mt8188-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/mailbox/mediatek,mt8188-gce.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h>
#include <dt-bindings/power/mediatek,mt8188-power.h>
@@ -413,6 +414,22 @@ pwrap: pwrap@10024000 {
clock-names = "spi", "wrap";
};
gce0: mailbox@10320000 {
compatible = "mediatek,mt8188-gce";
reg = <0 0x10320000 0 0x4000>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
#mbox-cells = <2>;
clocks = <&infracfg_ao CLK_INFRA_AO_GCE>;
};
gce1: mailbox@10330000 {
compatible = "mediatek,mt8188-gce";
reg = <0 0x10330000 0 0x4000>;
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>;
#mbox-cells = <2>;
clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>;
};
scp: scp@10500000 {
compatible = "mediatek,mt8188-scp";
reg = <0 0x10500000 0 0x100000>,