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arm64: dts: sc7180: Factor out ti-sn65dsi86 support

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Factor out ti-sn65dsi86 edp bridge as a separate dts fragment.
This helps us introduce the second source edp bridge later.

Signed-off-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211008113839.v3.1.Ibada67e75d2982157e64164f1d11715d46cdc42c@changeid
This commit is contained in:
Philip Chen
2021-10-08 11:39:34 -07:00
committed by Bjorn Andersson
parent eaa744b1c1
commit 4537977a50
7 changed files with 95 additions and 86 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi
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@@ -11,6 +11,7 @@
ap_h1_spi: &spi0 {};
#include "sc7180-trogdor.dtsi"
#include "sc7180-trogdor-ti-sn65dsi86.dtsi"
/* Deleted nodes from trogdor.dtsi */

1
arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi
View File

@@ -11,6 +11,7 @@
ap_h1_spi: &spi0 {};
#include "sc7180-trogdor.dtsi"
#include "sc7180-trogdor-ti-sn65dsi86.dtsi"
/ {
/* BOARD-SPECIFIC TOP LEVEL NODES */

1
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi
View File

@@ -11,6 +11,7 @@
ap_h1_spi: &spi0 {};
#include "sc7180-trogdor.dtsi"
#include "sc7180-trogdor-ti-sn65dsi86.dtsi"
&ap_sar_sensor {
semtech,cs0-ground;

1
arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi
View File

@@ -11,6 +11,7 @@
ap_h1_spi: &spi0 {};
#include "sc7180-trogdor.dtsi"
#include "sc7180-trogdor-ti-sn65dsi86.dtsi"
/ {
thermal-zones {

1
arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts
View File

@@ -13,6 +13,7 @@
ap_h1_spi: &spi0 {};
#include "sc7180-trogdor.dtsi"
#include "sc7180-trogdor-ti-sn65dsi86.dtsi"
/ {
model = "Google Trogdor (rev1+)";

90
arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi Normal file
View File

@@ -0,0 +1,90 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Trogdor dts fragment for the boards with TI sn65dsi86 edp bridge
*
* Copyright 2021 Google LLC.
*/
&dsi0_out {
remote-endpoint = <&sn65dsi86_in>;
data-lanes = <0 1 2 3>;
};
edp_brij_i2c: &i2c2 {
status = "okay";
clock-frequency = <400000>;
sn65dsi86_bridge: bridge@2d {
compatible = "ti,sn65dsi86";
reg = <0x2d>;
pinctrl-names = "default";
pinctrl-0 = <&edp_brij_en>, <&edp_brij_irq>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&tlmm>;
interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
enable-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>;
vpll-supply = <&pp1800_edp_vpll>;
vccio-supply = <&pp1800_brij_vccio>;
vcca-supply = <&pp1200_brij>;
vcc-supply = <&pp1200_brij>;
clocks = <&rpmhcc RPMH_LN_BB_CLK3>;
clock-names = "refclk";
no-hpd;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
sn65dsi86_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
port@1 {
reg = <1>;
sn65dsi86_out: endpoint {
data-lanes = <0 1>;
remote-endpoint = <&panel_in_edp>;
};
};
};
aux-bus {
panel: panel {
/* Compatible will be filled in per-board */
power-supply = <&pp3300_dx_edp>;
backlight = <&backlight>;
hpd-gpios = <&sn65dsi86_bridge 2 GPIO_ACTIVE_HIGH>;
port {
panel_in_edp: endpoint {
remote-endpoint = <&sn65dsi86_out>;
};
};
};
};
};
};
&tlmm {
edp_brij_irq: edp-brij-irq {
pinmux {
pins = "gpio11";
function = "gpio";
};
pinconf {
pins = "gpio11";
drive-strength = <2>;
bias-pull-down;
};
};
};

86
arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
View File

@@ -602,15 +602,6 @@ &camcc {
&dsi0 {
status = "okay";
vdda-supply = <&vdda_mipi_dsi0_1p2>;
ports {
port@1 {
endpoint {
remote-endpoint = <&sn65dsi86_in>;
data-lanes = <0 1 2 3>;
};
};
};
};
&dsi_phy {
@@ -618,70 +609,6 @@ &dsi_phy {
vdds-supply = <&vdda_mipi_dsi0_pll>;
};
edp_brij_i2c: &i2c2 {
status = "okay";
clock-frequency = <400000>;
sn65dsi86_bridge: bridge@2d {
compatible = "ti,sn65dsi86";
reg = <0x2d>;
pinctrl-names = "default";
pinctrl-0 = <&edp_brij_en>, <&edp_brij_irq>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&tlmm>;
interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
enable-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>;
vpll-supply = <&pp1800_edp_vpll>;
vccio-supply = <&pp1800_brij_vccio>;
vcca-supply = <&pp1200_brij>;
vcc-supply = <&pp1200_brij>;
clocks = <&rpmhcc RPMH_LN_BB_CLK3>;
clock-names = "refclk";
no-hpd;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
sn65dsi86_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
port@1 {
reg = <1>;
sn65dsi86_out: endpoint {
data-lanes = <0 1>;
remote-endpoint = <&panel_in_edp>;
};
};
};
aux-bus {
panel: panel {
/* Compatible will be filled in per-board */
power-supply = <&pp3300_dx_edp>;
backlight = <&backlight>;
hpd-gpios = <&sn65dsi86_bridge 2 GPIO_ACTIVE_HIGH>;
port {
panel_in_edp: endpoint {
remote-endpoint = <&sn65dsi86_out>;
};
};
};
};
};
};
ap_sar_sensor_i2c: &i2c5 {
clock-frequency = <400000>;
@@ -1234,19 +1161,6 @@ pinconf {
};
};
edp_brij_irq: edp-brij-irq {
pinmux {
pins = "gpio11";
function = "gpio";
};
pinconf {
pins = "gpio11";
drive-strength = <2>;
bias-pull-down;
};
};
en_pp3300_codec: en-pp3300-codec {
pinmux {
pins = "gpio83";