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drm/xe: Separate pure MMIO init from VRAM checkout

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We can setup root tile registers mapping at the same time as we
do early mapping of the entire MMIO BAR and keep mandatory VRAM
checkout as a separate step. This will allow us to perform SR-IOV
VF mode detection between those two steps using regular MMIO regs
access functions.

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240327182740.407-2-michal.wajdeczko@intel.com
This commit is contained in:
Michal Wajdeczko
2024-03-27 19:27:38 +01:00
parent 7ee7dd6f30
commit 451d261a6e
3 changed files with 28 additions and 39 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/xe/xe_device.c
View File

@@ -424,7 +424,7 @@ int xe_device_probe_early(struct xe_device *xe)
if (err)
return err;
err = xe_mmio_root_tile_init(xe);
err = xe_mmio_verify_vram(xe);
if (err)
return err;

63
drivers/gpu/drm/xe/xe_mmio.c
View File

@@ -360,7 +360,32 @@ static void mmio_fini(struct drm_device *drm, void *arg)
iounmap(xe->mem.vram.mapping);
}
static int xe_verify_lmem_ready(struct xe_device *xe)
int xe_mmio_init(struct xe_device *xe)
{
struct xe_tile *root_tile = xe_device_get_root_tile(xe);
struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
const int mmio_bar = 0;
/*
* Map the entire BAR.
* The first 16MB of the BAR, belong to the root tile, and include:
* registers (0-4MB), reserved space (4MB-8MB) and GGTT (8MB-16MB).
*/
xe->mmio.size = pci_resource_len(pdev, mmio_bar);
xe->mmio.regs = pci_iomap(pdev, mmio_bar, 0);
if (xe->mmio.regs == NULL) {
drm_err(&xe->drm, "failed to map registers\n");
return -EIO;
}
/* Setup first tile; other tiles (if present) will be setup later. */
root_tile->mmio.size = SZ_16M;
root_tile->mmio.regs = xe->mmio.regs;
return drmm_add_action_or_reset(&xe->drm, mmio_fini, xe);
}
int xe_mmio_verify_vram(struct xe_device *xe)
{
struct xe_gt *gt = xe_root_mmio_gt(xe);
@@ -384,42 +409,6 @@ static int xe_verify_lmem_ready(struct xe_device *xe)
return 0;
}
int xe_mmio_init(struct xe_device *xe)
{
struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
const int mmio_bar = 0;
/*
* Map the entire BAR.
* The first 16MB of the BAR, belong to the root tile, and include:
* registers (0-4MB), reserved space (4MB-8MB) and GGTT (8MB-16MB).
*/
xe->mmio.size = pci_resource_len(pdev, mmio_bar);
xe->mmio.regs = pci_iomap(pdev, mmio_bar, 0);
if (xe->mmio.regs == NULL) {
drm_err(&xe->drm, "failed to map registers\n");
return -EIO;
}
return drmm_add_action_or_reset(&xe->drm, mmio_fini, xe);
}
int xe_mmio_root_tile_init(struct xe_device *xe)
{
struct xe_tile *root_tile = xe_device_get_root_tile(xe);
int err;
/* Setup first tile; other tiles (if present) will be setup later. */
root_tile->mmio.size = SZ_16M;
root_tile->mmio.regs = xe->mmio.regs;
err = xe_verify_lmem_ready(xe);
if (err)
return err;
return 0;
}
u8 xe_mmio_read8(struct xe_gt *gt, struct xe_reg reg)
{
struct xe_tile *tile = gt_to_tile(gt);

2
drivers/gpu/drm/xe/xe_mmio.h
View File

@@ -21,7 +21,7 @@ struct xe_device;
#define LMEM_BAR 2
int xe_mmio_init(struct xe_device *xe);
int xe_mmio_root_tile_init(struct xe_device *xe);
int xe_mmio_verify_vram(struct xe_device *xe);
void xe_mmio_probe_tiles(struct xe_device *xe);
u8 xe_mmio_read8(struct xe_gt *gt, struct xe_reg reg);