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Merge tag 'imx-dt64-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt

Browse Source 
i.MX arm64 device tree change for 6.3:

- New board support: i.MX8MP Beacon Kit, Debix Model A Board,
  Verdin Yavia boards.
- Add Flexcan and ADC support for i.MX93.
- A series from Krzysztof Kozlowski to align LED node names with
  dtschema and use generic node name for rave-sp.
- Move PCIe controller clock setup from board dts to SoC dtsi.
- Add clock-cells to i.MX8MP hsio-blk-ctrl device.
- Add TMU phandle to calibration data in OCOTP for i.MX8M.
- Improve bluetooth UART on DH electronics i.MX8M Plus DHCOM.
- Drop sd-vsel-gpios from i.MX8M Verdin SoM and DHCOM SoM.
- A series from Peng Fan to improve iomuxc-gpr device for i.MX8M.
- Declare IOMMU cache-coherent page table walk feature for LS1028A and
  LS1088A.
- A few small corrections and random updates.

* tag 'imx-dt64-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (50 commits)
  arm64: ls1046ardb: Use in-band-status for SFP module
  arm64: dts: imx8mp-verdin: Add yavia carrier board
  arm64: dts: imx8mm-verdin: Add yavia carrier board
  arm64: dts: imx8q: use generic node name for rave-sp
  arm64: dts: imx8mp-verdin-dev: Do not include dahlia dtsi
  arm64: dts: imx8mm-verdin-dev: Do not include dahlia dtsi
  arm64: dts: imx8mp: Drop sd-vsel-gpios from i.MX8M Plus DHCOM SoM
  arm64: dts: imx8mp: Drop sd-vsel-gpios from i.MX8M Plus Verdin SoM
  arm64: dts: imx8mm: Drop sd-vsel-gpios from i.MX8M Mini Verdin SoM
  arm64: dts: imx8mp: Improve bluetooth UART on DH electronics i.MX8M Plus DHCOM
  arm64: dts: freescale: Introduce imx8mp-beacon-kit
  arm64: dts: imx8mm-evk: use correct gpio-expander compatible
  arm64: dts: imx93: add ADC support
  arm64: dts: imx8mp: Reorder clock to match fsl,imx6q-pcie.yaml
  arm64: dts: imx8mq: Deduplicate PCIe clock-names property
  arm64: dts: imx8mm: Deduplicate PCIe clock-names property
  arm64: dts: verdin-imx8mp: unify gpio-key node name
  arm64: dts: ls1028a: sl28: get MAC addresses from VPD
  arm64: dts: freescale: Add LVDS overlay for TQMa8MPxL
  arm64: dts: imx8mp: Add LCDIF2 & LDB nodes
  ...

Link: https://lore.kernel.org/r/20230130023947.11780-5-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2023-01-30 23:05:14 +01:00
parent 739a7c29a7 46e828026c
commit 4503fc6ea3
67 changed files with 2717 additions and 280 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
arch/arm64/boot/dts/freescale/Makefile
View File

@@ -75,8 +75,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7903.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7904.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dahlia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-yavia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dahlia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-yavia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-beacon-kit.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-bsh-smm-s2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-bsh-smm-s2pro.dtb
@@ -86,6 +88,8 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-venice-gw7902.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-beacon-kit.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-model-a.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-icore-mx8mp-edimm2.2.dtb
@@ -95,8 +99,14 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dahlia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-yavia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-dahlia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-yavia.dtb
imx8mp-tqma8mpql-mba8mpxl-lvds-dtbs += imx8mp-tqma8mpql-mba8mpxl.dtb imx8mp-tqma8mpql-mba8mpxl-lvds.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl-lvds.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-hummingboard-pulse.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-kontron-pitx-imx8m.dtb

12
arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dts
View File

@@ -56,10 +56,14 @@ qsgmii_phy3: ethernet-phy@10 {
};
&enetc_port2 {
nvmem-cells = <&base_mac_address 2>;
nvmem-cell-names = "mac-address";
status = "okay";
};
&enetc_port3 {
nvmem-cells = <&base_mac_address 3>;
nvmem-cell-names = "mac-address";
status = "okay";
};
@@ -80,6 +84,8 @@ &mscc_felix_port0 {
managed = "in-band-status";
phy-handle = <&qsgmii_phy0>;
phy-mode = "qsgmii";
nvmem-cells = <&base_mac_address 4>;
nvmem-cell-names = "mac-address";
status = "okay";
};
@@ -88,6 +94,8 @@ &mscc_felix_port1 {
managed = "in-band-status";
phy-handle = <&qsgmii_phy1>;
phy-mode = "qsgmii";
nvmem-cells = <&base_mac_address 5>;
nvmem-cell-names = "mac-address";
status = "okay";
};
@@ -96,6 +104,8 @@ &mscc_felix_port2 {
managed = "in-band-status";
phy-handle = <&qsgmii_phy2>;
phy-mode = "qsgmii";
nvmem-cells = <&base_mac_address 6>;
nvmem-cell-names = "mac-address";
status = "okay";
};
@@ -104,6 +114,8 @@ &mscc_felix_port3 {
managed = "in-band-status";
phy-handle = <&qsgmii_phy3>;
phy-mode = "qsgmii";
nvmem-cells = <&base_mac_address 7>;
nvmem-cell-names = "mac-address";
status = "okay";
};

2
arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts
View File

@@ -55,5 +55,7 @@ &enetc_port0 {
&enetc_port1 {
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
nvmem-cells = <&base_mac_address 0>;
nvmem-cell-names = "mac-address";
status = "okay";
};

8
arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var2.dts
View File

@@ -36,10 +36,14 @@ &enetc_port0 {
};
&enetc_port2 {
nvmem-cells = <&base_mac_address 2>;
nvmem-cell-names = "mac-address";
status = "okay";
};
&enetc_port3 {
nvmem-cells = <&base_mac_address 3>;
nvmem-cell-names = "mac-address";
status = "okay";
};
@@ -52,6 +56,8 @@ &mscc_felix_port0 {
managed = "in-band-status";
phy-handle = <&phy0>;
phy-mode = "sgmii";
nvmem-cells = <&base_mac_address 0>;
nvmem-cell-names = "mac-address";
status = "okay";
};
@@ -60,6 +66,8 @@ &mscc_felix_port1 {
managed = "in-band-status";
phy-handle = <&phy1>;
phy-mode = "sgmii";
nvmem-cells = <&base_mac_address 1>;
nvmem-cell-names = "mac-address";
status = "okay";
};

2
arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts
View File

@@ -43,5 +43,7 @@ vddh: vddh-regulator {
&enetc_port1 {
phy-handle = <&phy1>;
phy-mode = "rgmii-id";
nvmem-cells = <&base_mac_address 1>;
nvmem-cell-names = "mac-address";
status = "okay";
};

17
arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts
View File

@@ -92,6 +92,8 @@ &enetc_port0 {
phy-handle = <&phy0>;
phy-mode = "sgmii";
managed = "in-band-status";
nvmem-cells = <&base_mac_address 0>;
nvmem-cell-names = "mac-address";
status = "okay";
};
@@ -154,6 +156,21 @@ partition@3e0000 {
label = "bootloader environment";
};
};
otp-1 {
compatible = "user-otp";
nvmem-layout {
compatible = "kontron,sl28-vpd";
serial_number: serial-number {
};
base_mac_address: base-mac-address {
#nvmem-cell-cells = <1>;
};
};
};
};
};

1
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
View File

@@ -713,6 +713,7 @@ smmu: iommu@5000000 {
reg = <0 0x5000000 0 0x800000>;
#global-interrupts = <8>;
#iommu-cells = <1>;
dma-coherent;
stream-match-mask = <0x7c00>;
/* global secure fault */
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,

4
arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
View File

@@ -153,8 +153,8 @@ ethernet@f0000 { /* 10GEC1 */
};
ethernet@f2000 { /* 10GEC2 */
fixed-link = <0 1 1000 0 0>;
phy-connection-type = "xgmii";
phy-connection-type = "10gbase-r";
managed = "in-band-status";
};
mdio@fc000 {

1
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
View File

@@ -674,6 +674,7 @@ smmu: iommu@5000000 {
reg = <0 0x5000000 0 0x800000>;
#iommu-cells = <1>;
stream-match-mask = <0x7C00>;
dma-coherent;
#global-interrupts = <12>;
// global secure fault
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,

1
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
View File

@@ -135,6 +135,7 @@ ethphy0: ethernet-phy@0 {
reg = <0>;
eee-broken-1000t;
qca,disable-smarteee;
qca,disable-hibernation-mode;
vddio-supply = <&vddio0>;
vddio0: vddio-regulator {

2
arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
View File

@@ -67,7 +67,7 @@ usbmisc2: usbmisc@5b0e0200 {
reg = <0x5b0e0200 0x200>;
};
usbphy2: usbphy@0x5b110000 {
usbphy2: usbphy@5b110000 {
compatible = "fsl,imx8dxl-usbphy", "fsl,imx7ulp-usbphy";
reg = <0x5b110000 0x1000>;
clocks = <&usb2_2_lpcg IMX_LPCG_CLK_7>;

5
arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
View File

@@ -241,9 +241,8 @@ &pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
<&pcie0_refclk_gated>;
clock-names = "pcie", "pcie_aux", "pcie_bus";
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk_gated>,
<&clk IMX8MM_CLK_PCIE1_AUX>;
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_CTRL>;
assigned-clock-rates = <10000000>, <250000000>;

5
arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts
View File

@@ -904,9 +904,8 @@ &pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
<&pcieclk 0>;
clock-names = "pcie", "pcie_aux", "pcie_bus";
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcieclk 0>,
<&clk IMX8MM_CLK_PCIE1_AUX>;
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_CTRL>;
assigned-clock-rates = <10000000>, <250000000>;

4
arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi
View File

@@ -18,14 +18,14 @@ som_leds: leds {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_led>;
green {
led-green {
label = "som:green";
gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
default-state = "on";
linux,default-trigger = "heartbeat";
};
red {
led-red {
label = "som:red";
gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>;
default-state = "off";

7
arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
View File

@@ -340,7 +340,7 @@ &i2c3 {
status = "okay";
pca6416: gpio@20 {
compatible = "ti,tca6416";
compatible = "nxp,pca6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
@@ -360,9 +360,8 @@ &pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_bus";
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
<&clk IMX8MM_CLK_PCIE1_AUX>;
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_CTRL>;
assigned-clock-rates = <10000000>, <250000000>;

3
arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi
View File

@@ -210,9 +210,6 @@ &pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_PHY>,
<&clk IMX8MM_CLK_PCIE1_AUX>;
clock-names = "pcie", "pcie_bus", "pcie_aux";
fsl,max-link-speed = <1>;
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk IMX8MM_CLK_PCIE1_CTRL>;
assigned-clock-rates = <10000000>, <250000000>;

4
arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts
View File

@@ -13,6 +13,8 @@ / {
aliases {
ethernet1 = &usbnet;
rtc0 = &rx8900;
rtc1 = &snvs_rtc;
};
/* fixed crystal dedicated to mcp2515 */
@@ -136,7 +138,7 @@ &i2c4 {
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
rtc@32 {
rx8900: rtc@32 {
compatible = "epson,rx8900";
reg = <0x32>;
};

7
arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi
View File

@@ -10,6 +10,11 @@ / {
model = "Kontron OSM-S i.MX8MM (N802X SOM)";
compatible = "kontron,imx8mm-osm-s", "fsl,imx8mm";
aliases {
rtc0 = &rv3028;
rtc1 = &snvs_rtc;
};
memory@40000000 {
device_type = "memory";
/*
@@ -200,7 +205,7 @@ reg_nvcc_sd: LDO5 {
};
};
rtc@52 {
rv3028: rtc@52 {
compatible = "microcrystal,rv3028";
reg = <0x52>;
pinctrl-names = "default";

1
arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts
View File

@@ -10,6 +10,7 @@
/ {
model = "MENLO MX8MM EMBEDDED DEVICE";
compatible = "menlo,mx8menlo",
"toradex,verdin-imx8mm-nonwifi",
"toradex,verdin-imx8mm",
"fsl,imx8mm";

3
arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts
View File

@@ -175,9 +175,6 @@ &pcie0 {
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
<&clk IMX8MM_SYS_PLL2_250M>;
assigned-clock-rates = <10000000>, <250000000>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_PHY>;
clock-names = "pcie", "pcie_aux", "pcie_bus";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>;

5
arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts
View File

@@ -79,9 +79,8 @@ &pcie_phy {
&pcie0 {
reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_bus";
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
<&clk IMX8MM_CLK_PCIE1_AUX>;
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_CTRL>;
assigned-clock-rates = <10000000>, <250000000>;

4
arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi
View File

@@ -87,8 +87,8 @@ &i2c1 {
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
sensor0: temperature-sensor-eeprom@1b {
compatible = "nxp,se97", "jedec,jc-42.4-temp";
sensor0: temperature-sensor@1b {
compatible = "nxp,se97b", "jedec,jc-42.4-temp";
reg = <0x1b>;
};

1
arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi
View File

@@ -231,7 +231,6 @@ ldo4_reg: LDO4 {
};
ldo5_reg: LDO5 {
regulator-compatible = "ldo5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;

5
arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
View File

@@ -120,9 +120,8 @@ &pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_bus";
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
<&clk IMX8MM_CLK_PCIE1_AUX>;
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_CTRL>;
assigned-clock-rates = <10000000>, <250000000>;

5
arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
View File

@@ -142,9 +142,8 @@ &pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_bus";
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
<&clk IMX8MM_CLK_PCIE1_AUX>;
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_CTRL>;
assigned-clock-rates = <10000000>, <250000000>;

5
arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi
View File

@@ -162,9 +162,8 @@ &pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_bus";
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
<&clk IMX8MM_CLK_PCIE1_AUX>;
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_CTRL>;
assigned-clock-rates = <10000000>, <250000000>;

5
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
View File

@@ -702,9 +702,8 @@ &pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio5 2 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_bus";
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
<&clk IMX8MM_CLK_PCIE1_AUX>;
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_CTRL>;
assigned-clock-rates = <10000000>, <250000000>;

5
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
View File

@@ -623,9 +623,8 @@ &pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio4 5 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_bus";
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
<&clk IMX8MM_CLK_PCIE1_AUX>;
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_CTRL>;
assigned-clock-rates = <10000000>, <250000000>;

5
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts
View File

@@ -557,9 +557,8 @@ &pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_bus";
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
<&clk IMX8MM_CLK_PCIE1_AUX>;
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_CTRL>;
assigned-clock-rates = <10000000>, <250000000>;

5
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts
View File

@@ -618,9 +618,8 @@ &pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_bus";
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
<&clk IMX8MM_CLK_PCIE1_AUX>;
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_CTRL>;
assigned-clock-rates = <10000000>, <250000000>;

2
arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi
View File

@@ -136,11 +136,13 @@ &uart3 {
/* Verdin USB_1 */
&usbotg1 {
disable-over-current;
status = "okay";
};
/* Verdin USB_2 */
&usbotg2 {
disable-over-current;
status = "okay";
};

96
arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi
View File

@@ -3,8 +3,6 @@
* Copyright 2022 Toradex
*/
#include "imx8mm-verdin-dahlia.dtsi"
/ {
sound_card: sound-card {
compatible = "simple-audio-card";
@@ -41,27 +39,121 @@ simple-audio-card,cpu {
};
};
/* Verdin SPI_1 */
&ecspi2 {
status = "okay";
};
/* EEPROM on display adapter boards */
&eeprom_display_adapter {
status = "okay";
};
/* EEPROM on Verdin Development board */
&eeprom_carrier_board {
status = "okay";
};
&fec1 {
status = "okay";
};
/* Verdin QSPI_1 */
&flexspi {
status = "okay";
};
/* Current measurement into module VCC */
&hwmon {
status = "okay";
};
&hwmon_temp {
vs-supply = <&reg_1p8v>;
status = "okay";
};
&i2c3 {
status = "okay";
};
&gpio_expander_21 {
status = "okay";
};
/* Verdin I2C_1 */
&i2c4 {
status = "okay";
/* Audio Codec */
nau8822_1a: audio-codec@1a {
compatible = "nuvoton,nau8822";
reg = <0x1a>;
#sound-dai-cells = <0>;
};
};
/* Verdin PCIE_1 */
&pcie0 {
status = "okay";
};
&pcie_phy {
status = "okay";
};
/* Verdin PWM_3_DSI */
&pwm1 {
status = "okay";
};
/* Verdin PWM_1 */
&pwm2 {
status = "okay";
};
/* Verdin PWM_2 */
&pwm3 {
status = "okay";
};
/* Verdin I2S_1 */
&sai2 {
status = "okay";
};
/* Verdin UART_3 */
&uart1 {
status = "okay";
};
/* Verdin UART_1, connector X50 through RS485 transceiver */
&uart2 {
linux,rs485-enabled-at-boot-time;
rs485-rts-active-low;
rs485-rx-during-tx;
status = "okay";
};
/* Verdin UART_2 */
&uart3 {
status = "okay";
};
/* Verdin USB_1 */
&usbotg1 {
disable-over-current;
status = "okay";
};
/* Verdin USB_2 */
&usbotg2 {
disable-over-current;
status = "okay";
};
/* Limit frequency on dev board due to long traces and bad signal integrity */
&usdhc2 {
max-frequency = <100000000>;
status = "okay";
};

18
arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-yavia.dts Normal file
View File

@@ -0,0 +1,18 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2023 Toradex
*/
/dts-v1/;
#include "imx8mm-verdin.dtsi"
#include "imx8mm-verdin-nonwifi.dtsi"
#include "imx8mm-verdin-yavia.dtsi"
/ {
model = "Toradex Verdin iMX8M Mini on Yavia Board";
compatible = "toradex,verdin-imx8mm-nonwifi-yavia",
"toradex,verdin-imx8mm-nonwifi",
"toradex,verdin-imx8mm",
"fsl,imx8mm";
};

18
arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-yavia.dts Normal file
View File

@@ -0,0 +1,18 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2023 Toradex
*/
/dts-v1/;
#include "imx8mm-verdin.dtsi"
#include "imx8mm-verdin-wifi.dtsi"
#include "imx8mm-verdin-yavia.dtsi"
/ {
model = "Toradex Verdin iMX8M Mini WB on Yavia Board";
compatible = "toradex,verdin-imx8mm-wifi-yavia",
"toradex,verdin-imx8mm-wifi",
"toradex,verdin-imx8mm",
"fsl,imx8mm";
};

169
arch/arm64/boot/dts/freescale/imx8mm-verdin-yavia.dtsi Normal file
View File

@@ -0,0 +1,169 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2023 Toradex
*/
#include <dt-bindings/leds/common.h>
/ {
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_leds_yavia>;
/* SODIMM 52 - LD1_RED */
led-0 {
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_DEBUG;
function-enumerator = <1>;
gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
};
/* SODIMM 54 - LD1_GREEN */
led-1 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_DEBUG;
function-enumerator = <1>;
gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>;
};
/* SODIMM 56 - LD1_BLUE */
led-2 {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_DEBUG;
function-enumerator = <1>;
gpios = <&gpio3 6 GPIO_ACTIVE_HIGH>;
};
/* SODIMM 58 - LD2_RED */
led-3 {
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_DEBUG;
function-enumerator = <2>;
gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>;
};
/* SODIMM 60 - LD2_GREEN */
led-4 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_DEBUG;
function-enumerator = <2>;
gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>;
};
/* SODIMM 62 - LD2_BLUE */
led-5 {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_DEBUG;
function-enumerator = <2>;
gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>;
};
};
};
/* Verdin SPI_1 */
&ecspi2 {
status = "okay";
};
/* EEPROM on display adapter boards */
&eeprom_display_adapter {
status = "okay";
};
/* EEPROM on Verdin yavia board */
&eeprom_carrier_board {
status = "okay";
};
&fec1 {
status = "okay";
};
&gpio3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpios_ext_yavia>;
};
&hwmon_temp {
status = "okay";
};
&i2c3 {
status = "okay";
};
/* Verdin I2C_1 */
&i2c4 {
status = "okay";
};
/* Verdin PCIE_1 */
&pcie0 {
status = "okay";
};
&pcie_phy {
status = "okay";
};
/* Verdin PWM_3_DSI */
&pwm1 {
status = "okay";
};
/* Verdin PWM_1 */
&pwm2 {
status = "okay";
};
/* Verdin PWM_2 */
&pwm3 {
status = "okay";
};
/* Verdin UART_3 */
&uart1 {
status = "okay";
};
/* Verdin UART_1 */
&uart2 {
status = "okay";
};
/* Verdin UART_2 */
&uart3 {
status = "okay";
};
/* Verdin USB_1 */
&usbotg1 {
status = "okay";
};
/* Verdin USB_2 */
&usbotg2 {
status = "okay";
};
/* Verdin SD_1 */
&usdhc2 {
status = "okay";
};
&iomuxc {
pinctrl_leds_yavia: ledsyaviagrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x106 /* SODIMM 52 */
MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x106 /* SODIMM 54 */
MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6 0x106 /* SODIMM 56 */
MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x106 /* SODIMM 58 */
MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x106 /* SODIMM 60 */
MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9 0x106 /* SODIMM 62 */
>;
};
pinctrl_gpios_ext_yavia: gpiosextyaviagrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x106 /* SODIMM 64 */
MX8MM_IOMUXC_NAND_DQS_GPIO3_IO14 0x106 /* SODIMM 66 */
>;
};
};

13
arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
View File

@@ -56,7 +56,11 @@ key-wakeup {
hdmi_connector: hdmi-connector {
compatible = "hdmi-connector";
ddc-i2c-bus = <&i2c2>;
/* Verdin PWM_3_DSI (SODIMM 19) */
hpd-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
label = "hdmi";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm_3_dsi_hpd_gpio>;
type = "a";
status = "disabled";
};
@@ -358,7 +362,6 @@ pca9450: pmic@25 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
reg = <0x25>;
sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
/*
* The bootloader is expected to switch on the I2C level shifter for the TLA2024 ADC
@@ -598,7 +601,7 @@ hwmon: hwmon@40 {
hdmi_lontium_lt8912: hdmi@48 {
compatible = "lontium,lt8912b";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_10_dsi>, <&pinctrl_pwm_3_dsi_hpd_gpio>;
pinctrl-0 = <&pinctrl_gpio_10_dsi>;
reg = <0x48>;
/* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */
/* Verdin GPIO_10_DSI (SODIMM 21) */
@@ -653,10 +656,6 @@ &pcie0 {
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
<&clk IMX8MM_SYS_PLL2_250M>;
assigned-clock-rates = <10000000>, <250000000>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
<&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_PHY>;
clock-names = "pcie", "pcie_aux", "pcie_bus";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
/* PCIE_1_RESET# (SODIMM 244) */
@@ -741,7 +740,6 @@ &usbotg1 {
adp-disable;
dr_mode = "otg";
hnp-disable;
over-current-active-low;
samsung,picophy-dc-vol-level-adjust = <7>;
samsung,picophy-pre-emp-curr-control = <3>;
srp-disable;
@@ -751,7 +749,6 @@ &usbotg1 {
/* Verdin USB_2 */
&usbotg2 {
dr_mode = "host";
over-current-active-low;
samsung,picophy-dc-vol-level-adjust = <7>;
samsung,picophy-pre-emp-curr-control = <3>;
vbus-supply = <&reg_usb_otg2_vbus>;

34
arch/arm64/boot/dts/freescale/imx8mm.dtsi
View File

@@ -496,6 +496,8 @@ tmu: tmu@30260000 {
compatible = "fsl,imx8mm-tmu";
reg = <0x30260000 0x10000>;
clocks = <&clk IMX8MM_CLK_TMU_ROOT>;
nvmem-cells = <&tmu_calib>;
nvmem-cell-names = "calib";
#thermal-sensor-cells = <0>;
};
@@ -550,8 +552,8 @@ iomuxc: pinctrl@30330000 {
reg = <0x30330000 0x10000>;
};
gpr: iomuxc-gpr@30340000 {
compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon";
gpr: syscon@30340000 {
compatible = "fsl,imx8mm-iomuxc-gpr", "syscon";
reg = <0x30340000 0x10000>;
};
@@ -563,15 +565,32 @@ ocotp: efuse@30350000 {
#address-cells = <1>;
#size-cells = <1>;
imx8mm_uid: unique-id@410 {
/*
* The register address below maps to the MX8M
* Fusemap Description Table entries this way.
* Assuming
* reg = <ADDR SIZE>;
* then
* Fuse Address = (ADDR * 4) + 0x400
* Note that if SIZE is greater than 4, then
* each subsequent fuse is located at offset
* +0x10 in Fusemap Description Table (e.g.
* reg = <0x4 0x8> describes fuses 0x410 and
* 0x420).
*/
imx8mm_uid: unique-id@4 { /* 0x410-0x420 */
reg = <0x4 0x8>;
};
cpu_speed_grade: speed-grade@10 {
cpu_speed_grade: speed-grade@10 { /* 0x440 */
reg = <0x10 4>;
};
fec_mac_address: mac-address@90 {
tmu_calib: calib@3c { /* 0x4f0 */
reg = <0x3c 4>;
};
fec_mac_address: mac-address@90 { /* 0x640 */
reg = <0x90 6>;
};
};
@@ -1240,7 +1259,6 @@ dma_apbh: dma-controller@33000000 {
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
#dma-cells = <1>;
dma-channels = <4>;
clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
@@ -1284,6 +1302,10 @@ pcie0: pcie@33800000 {
<0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
fsl,max-link-speed = <2>;
linux,pci-domain = <0>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
<&clk IMX8MM_CLK_PCIE1_PHY>,
<&clk IMX8MM_CLK_PCIE1_AUX>;
clock-names = "pcie", "pcie_bus", "pcie_aux";
power-domains = <&pgc_pcie>;
resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
<&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;

4
arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi
View File

@@ -77,8 +77,8 @@ &i2c1 {
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
sensor0: temperature-sensor-eeprom@1b {
compatible = "nxp,se97", "jedec,jc-42.4-temp";
sensor0: temperature-sensor@1b {
compatible = "nxp,se97b", "jedec,jc-42.4-temp";
reg = <0x1b>;
};

2
arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi
View File

@@ -207,7 +207,7 @@ ldo4_reg: LDO4 {
};
ldo5_reg: LDO5 {
regulator-compatible = "ldo5";
regulator-name = "ldo5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;

28
arch/arm64/boot/dts/freescale/imx8mn.dtsi
View File

@@ -498,6 +498,8 @@ tmu: tmu@30260000 {
compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu";
reg = <0x30260000 0x10000>;
clocks = <&clk IMX8MN_CLK_TMU_ROOT>;
nvmem-cells = <&tmu_calib>;
nvmem-cell-names = "calib";
#thermal-sensor-cells = <0>;
};
@@ -552,7 +554,7 @@ iomuxc: pinctrl@30330000 {
reg = <0x30330000 0x10000>;
};
gpr: iomuxc-gpr@30340000 {
gpr: syscon@30340000 {
compatible = "fsl,imx8mn-iomuxc-gpr", "syscon";
reg = <0x30340000 0x10000>;
};
@@ -564,15 +566,32 @@ ocotp: efuse@30350000 {
#address-cells = <1>;
#size-cells = <1>;
imx8mn_uid: unique-id@410 {
/*
* The register address below maps to the MX8M
* Fusemap Description Table entries this way.
* Assuming
* reg = <ADDR SIZE>;
* then
* Fuse Address = (ADDR * 4) + 0x400
* Note that if SIZE is greater than 4, then
* each subsequent fuse is located at offset
* +0x10 in Fusemap Description Table (e.g.
* reg = <0x4 0x8> describes fuses 0x410 and
* 0x420).
*/
imx8mn_uid: unique-id@4 { /* 0x410-0x420 */
reg = <0x4 0x8>;
};
cpu_speed_grade: speed-grade@10 {
cpu_speed_grade: speed-grade@10 { /* 0x440 */
reg = <0x10 4>;
};
fec_mac_address: mac-address@90 {
tmu_calib: calib@3c { /* 0x4f0 */
reg = <0x3c 4>;
};
fec_mac_address: mac-address@90 { /* 0x640 */
reg = <0x90 6>;
};
};
@@ -1094,7 +1113,6 @@ dma_apbh: dma-controller@33000000 {
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
#dma-cells = <1>;
dma-channels = <4>;
clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;

550
arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts Normal file
View File

@@ -0,0 +1,550 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2023 Logic PD, Inc dba Beacon EmbeddedWorks
*/
/dts-v1/;
#include <dt-bindings/usb/pd.h>
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include "imx8mp.dtsi"
#include "imx8mp-beacon-som.dtsi"
/ {
model = "Beacon EmbeddedWorks i.MX8MPlus Development kit";
compatible = "beacon,imx8mp-beacon-kit", "fsl,imx8mp";
aliases {
ethernet0 = &eqos;
ethernet1 = &fec;
};
chosen {
stdout-path = &uart2;
};
connector {
compatible = "usb-c-connector";
label = "USB-C";
data-role = "dual";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hs_ep: endpoint {
remote-endpoint = <&usb3_hs_ep>;
};
};
port@1 {
reg = <1>;
ss_ep: endpoint {
remote-endpoint = <&hd3ss3220_in_ep>;
};
};
};
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
button-0 {
label = "btn0";
linux,code = <BTN_0>;
gpios = <&pca6416_1 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
wakeup-source;
};
button-1 {
label = "btn1";
linux,code = <BTN_1>;
gpios = <&pca6416_1 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
wakeup-source;
};
button-2 {
label = "btn2";
linux,code = <BTN_2>;
gpios = <&pca6416_1 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
wakeup-source;
};
button-3 {
label = "btn3";
linux,code = <BTN_3>;
gpios = <&pca6416_1 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led3>;
led-0 {
label = "gen_led0";
gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-1 {
label = "gen_led1";
gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-2 {
label = "gen_led2";
gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-3 {
label = "heartbeat";
gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
pcie0_refclk: clock-pcie {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
startup-delay-us = <100>;
off-on-delay-us = <20000>;
};
reg_usb1_host_vbus: regulator-usb1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb1_host_vbus";
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
gpio = <&pca6416_1 0 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
status = "okay";
tpm: tpm@0 {
compatible = "infineon,slb9670";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tpm>;
reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
spi-max-frequency = <18500000>;
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy1>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@3 {
compatible = "ethernet-phy-id0022.1640",
"ethernet-phy-ieee802.3-c22";
reg = <3>;
reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <150000>;
interrupt-parent = <&gpio4>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
};
};
};
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
status = "okay";
};
&gpio2 {
usb-mux-hog {
gpio-hog;
gpios = <20 0>;
output-low;
line-name = "USB-C Mux En";
};
};
&i2c2 {
clock-frequency = <384000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
pca6416_3: gpio@20 {
compatible = "nxp,pcal6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gpio4>;
interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
&i2c3 {
/* Connected to USB Hub */
usb-typec@52 {
compatible = "nxp,ptn5110";
reg = <0x52>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_typec>;
interrupt-parent = <&gpio4>;
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
connector {
compatible = "usb-c-connector";
label = "USB-C";
power-role = "source";
data-role = "host";
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
};
};
};
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
clock-frequency = <384000>;
status = "okay";
pca6416: gpio@20 {
compatible = "nxp,pcal6416";
reg = <0x20>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcal6414>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gpio4>;
interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
};
pca6416_1: gpio@21 {
compatible = "nxp,pcal6416";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gpio4>;
interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
usb-hub-hog {
gpio-hog;
gpios = <7 0>;
output-low;
line-name = "USB Hub Enable";
};
};
usb-typec@47 {
compatible = "ti,hd3ss3220";
reg = <0x47>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hd3ss3220>;
interrupt-parent = <&gpio4>;
interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hd3ss3220_in_ep: endpoint {
remote-endpoint = <&ss_ep>;
};
};
port@1 {
reg = <1>;
hd3ss3220_out_ep: endpoint {
remote-endpoint = <&usb3_role_switch>;
};
};
};
};
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pcie_phy {
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
clocks = <&pcie0_refclk>;
clock-names = "ref";
status = "okay";
};
&snvs_pwrkey {
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
assigned-clocks = <&clk IMX8MP_CLK_UART3>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
uart-has-rtscts;
status = "okay";
};
&usb3_0 {
status = "okay";
};
&usb_dwc3_0 {
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
usb-role-switch;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb3_hs_ep: endpoint {
remote-endpoint = <&hs_ep>;
};
};
port@1 {
reg = <1>;
usb3_role_switch: endpoint {
remote-endpoint = <&hd3ss3220_out_ep>;
};
};
};
};
&usb3_phy0 {
vbus-supply = <&reg_usb1_host_vbus>;
status = "okay";
};
&usb3_1 {
status = "okay";
};
&usb_dwc3_1 {
dr_mode = "host";
status = "okay";
};
&usb3_phy1 {
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
bus-width = <4>;
status = "okay";
};
&iomuxc {
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82
MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82
MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82
MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40000
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2
MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16
MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x140
MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x10
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
>;
};
pinctrl_hd3ss3220: hd3ss3220grp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x140
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2
MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2
>;
};
pinctrl_led3: led3grp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x41
>;
};
pinctrl_pcal6414: pcal6414-gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x10
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x10 /* PCIe_nDIS */
MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x10 /* PCIe_nRST */
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
>;
};
pinctrl_tpm: tpmgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x19 /* Reset */
MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x1d6 /* IRQ */
>;
};
pinctrl_typec: typec1grp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0xc4
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140
MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140
MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140
MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
>;
};
};

416
arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi Normal file
View File

@@ -0,0 +1,416 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2023 LogicPD, Inc. dba Beacon EmbeddedWorks
*/
/ {
aliases {
rtc0 = &rtc;
rtc1 = &snvs_rtc;
};
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0xc0000000>,
<0x1 0x00000000 0 0xc0000000>;
};
reg_wl_bt: regulator-wifi-bt {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_wl_bt>;
regulator-name = "wl-bt-pow-dwn";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 6 GPIO_ACTIVE_LOW>;
startup-delay-us = <70000>;
regulator-always-on;
};
};
&A53_0 {
cpu-supply = <&buck2>;
};
&A53_1 {
cpu-supply = <&buck2>;
};
&A53_2 {
cpu-supply = <&buck2>;
};
&A53_3 {
cpu-supply = <&buck2>;
};
&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
snps,force_thresh_dma_mode;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@3 {
compatible = "ethernet-phy-id0022.1640",
"ethernet-phy-ieee802.3-c22";
reg = <3>;
reset-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio1>;
interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
};
};
};
&flexspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi0>;
status = "okay";
flash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <80000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clock-frequency = <384000>;
status = "okay";
pmic@25 {
compatible = "nxp,pca9450c";
reg = <0x25>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
regulators {
buck1: BUCK1 {
regulator-name = "BUCK1";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck2: BUCK2 {
regulator-name = "BUCK2";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
nxp,dvs-run-voltage = <950000>;
nxp,dvs-standby-voltage = <850000>;
};
buck4: BUCK4 {
regulator-name = "BUCK4";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
buck5: BUCK5 {
regulator-name = "BUCK5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
buck6: BUCK6 {
regulator-name = "BUCK6";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
ldo1: LDO1 {
regulator-name = "LDO1";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo3: LDO3 {
regulator-name = "LDO3";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo4: LDO4 {
regulator-name = "LDO4";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo5: LDO5 {
regulator-name = "LDO5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clock-frequency = <384000>;
status = "okay";
eeprom@50 {
compatible = "atmel,24c64";
reg = <0x50>;
pagesize = <32>;
read-only; /* Manufacturing EEPROM programmed at factory */
};
rtc: rtc@51 {
compatible = "nxp,pcf85263";
reg = <0x51>;
};
};
&snvs_pwrkey {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
assigned-clocks = <&clk IMX8MP_CLK_UART1>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
uart-has-rtscts;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <4>;
vmmc-supply = <&reg_wl_bt>;
cap-sd-highspeed;
sd-uhs-sdr50;
sd-uhs-sdr104;
keep-power-in-suspend;
wakeup-source;
non-removable;
cap-power-off-card;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
mwifiex: wifi@1 {
compatible = "marvell,sd8997";
reg = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wlan>;
interrupt-parent = <&gpio2>;
interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
};
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10
MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x10
>;
};
pinctrl_flexspi0: flexspi0grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2
MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82
MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82
MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82
MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82
MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0
>;
};
pinctrl_reg_wl_bt: reg-wl-btgrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140
MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166
>;
};
pinctrl_wlan: wlangrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x140
>;
};
};

506
arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts Normal file
View File

@@ -0,0 +1,506 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2019 NXP
* Copyright 2022 Ideas on Board Oy
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/usb/pd.h>
#include "imx8mp.dtsi"
/ {
model = "Polyhex Debix Model A i.MX8MPlus board";
compatible = "polyhex,imx8mp-debix-model-a", "polyhex,imx8mp-debix", "fsl,imx8mp";
chosen {
stdout-path = &uart2;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_led>;
led-0 {
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_RED>;
gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&A53_0 {
cpu-supply = <&buck2>;
};
&A53_1 {
cpu-supply = <&buck2>;
};
&A53_2 {
cpu-supply = <&buck2>;
};
&A53_3 {
cpu-supply = <&buck2>;
};
&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
phy-connection-type = "rgmii-id";
phy-handle = <&ethphy0>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 { /* RTL8211E */
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
reset-assert-us = <20>;
reset-deassert-us = <200000>;
};
};
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic@25 {
compatible = "nxp,pca9450c";
reg = <0x25>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_EDGE_RISING>;
regulators {
buck1: BUCK1 {
regulator-name = "BUCK1";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck2: BUCK2 {
regulator-name = "BUCK2";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
nxp,dvs-run-voltage = <950000>;
nxp,dvs-standby-voltage = <850000>;
};
buck4: BUCK4{
regulator-name = "BUCK4";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
buck5: BUCK5{
regulator-name = "BUCK5";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
buck6: BUCK6 {
regulator-name = "BUCK6";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
ldo1: LDO1 {
regulator-name = "LDO1";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo2: LDO2 {
regulator-name = "LDO2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1150000>;
regulator-boot-on;
regulator-always-on;
};
ldo3: LDO3 {
regulator-name = "LDO3";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo4: LDO4 {
regulator-name = "LDO4";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo5: LDO5 {
regulator-name = "LDO5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
rtc@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "xin32k";
interrupt-parent = <&gpio2>;
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rtc_int>;
};
};
&i2c6 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c6>;
status = "okay";
};
&snvs_pwrkey {
status = "okay";
};
&uart2 {
/* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
/* SD Card */
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
bus-width = <4>;
status = "okay";
};
/* eMMC */
&usdhc3 {
assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x1f
MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x1f
MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x19
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
MX8MP_IOMUXC_SAI1_RXD1__ENET1_1588_EVENT1_OUT 0x1f
MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN 0x1f
MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x19
>;
};
pinctrl_gpio_led: gpioledgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3
MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3
>;
};
pinctrl_i2c6: i2c6grp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x400001c3
MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c3
>;
};
pinctrl_pmic: pmicirqgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
>;
};
pinctrl_rtc_int: rtcintgrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x140
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x14f
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x14f
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x49
MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x49
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49
MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
>;
};
};

21
arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi
View File

@@ -239,7 +239,6 @@ pmic: pmic@25 {
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
/*
* i.MX 8M Plus Data Sheet for Consumer Products
@@ -248,7 +247,6 @@ pmic: pmic@25 {
*/
regulators {
buck1: BUCK1 { /* VDD_SOC (dual-phase with BUCK3) */
regulator-compatible = "BUCK1";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1000000>;
regulator-ramp-delay = <3125>;
@@ -257,7 +255,6 @@ buck1: BUCK1 { /* VDD_SOC (dual-phase with BUCK3) */
};
buck2: BUCK2 { /* VDD_ARM */
regulator-compatible = "BUCK2";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1000000>;
regulator-ramp-delay = <3125>;
@@ -266,7 +263,6 @@ buck2: BUCK2 { /* VDD_ARM */
};
buck4: BUCK4 { /* VDD_3V3 */
regulator-compatible = "BUCK4";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
@@ -274,7 +270,6 @@ buck4: BUCK4 { /* VDD_3V3 */
};
buck5: BUCK5 { /* VDD_1V8 */
regulator-compatible = "BUCK5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
@@ -282,7 +277,6 @@ buck5: BUCK5 { /* VDD_1V8 */
};
buck6: BUCK6 { /* NVCC_DRAM_1V1 */
regulator-compatible = "BUCK6";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
@@ -290,7 +284,6 @@ buck6: BUCK6 { /* NVCC_DRAM_1V1 */
};
ldo1: LDO1 { /* NVCC_SNVS_1V8 */
regulator-compatible = "LDO1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
@@ -298,7 +291,6 @@ ldo1: LDO1 { /* NVCC_SNVS_1V8 */
};
ldo3: LDO3 { /* VDDA_1V8 */
regulator-compatible = "LDO3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
@@ -306,13 +298,11 @@ ldo3: LDO3 { /* VDDA_1V8 */
};
ldo4: LDO4 { /* PMIC_LDO4 */
regulator-compatible = "LDO4";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
ldo5: LDO5 { /* NVCC_SD2 */
regulator-compatible = "LDO5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
@@ -429,14 +419,15 @@ &uart2 {
status = "okay";
/*
* PLL3 at 320 MHz supplies UART2 root with 64 MHz clock,
* which with 16x oversampling yields 4 Mbdps baud base,
* PLL1 at 80 MHz supplies UART2 root with 80 MHz clock,
* which with 16x oversampling yields 5 Mbdps baud base,
* which can be well divided by 5/4 to achieve 4 Mbdps,
* which is exactly the maximum rate supported by muRata
* 2AE bluetooth UART.
*/
assigned-clocks = <&clk IMX8MP_SYS_PLL3>, <&clk IMX8MP_CLK_UART2>;
assigned-clock-parents = <0>, <&clk IMX8MP_SYS_PLL3_OUT>;
assigned-clock-rates = <320000000>, <64000000>;
assigned-clocks = <&clk IMX8MP_CLK_UART2>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
assigned-clock-rates = <80000000>;
bluetooth {
pinctrl-names = "default";

7
arch/arm64/boot/dts/freescale/imx8mp-evk.dts
View File

@@ -400,13 +400,6 @@ &pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
<&clk IMX8MP_CLK_PCIE_ROOT>,
<&clk IMX8MP_CLK_HSIO_AXI>;
clock-names = "pcie", "pcie_aux", "pcie_bus";
assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
assigned-clock-rates = <10000000>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
vpcie-supply = <&reg_pcie0>;
status = "okay";
};

61
arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl-lvds.dtso Normal file
View File

@@ -0,0 +1,61 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2022 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Alexander Stein
*/
/dts-v1/;
/plugin/;
&{/} {
compatible = "tq,imx8mp-tqma8mpql-mba8mpxl", "tq,imx8mp-tqma8mpql", "fsl,imx8mp";
};
&backlight_lvds {
status = "okay";
};
&display {
compatible = "tianma,tm070jvhg33";
status = "okay";
panel-timing {
clock-frequency = <74250000>;
hactive = <1280>;
vactive = <800>;
hfront-porch = <64>;
hback-porch = <5>;
hsync-len = <1>;
vfront-porch = <40>;
vback-porch = <2>;
vsync-len = <1>;
de-active = <1>;
};
port {
panel_in_lvds0: endpoint {
remote-endpoint = <&ldb_lvds_ch0>;
};
};
};
&lcdif2 {
status = "okay";
};
&lvds_bridge {
status = "okay";
ports {
port@1 {
ldb_lvds_ch0: endpoint {
remote-endpoint = <&panel_in_lvds0>;
};
};
};
};
&pwm2 {
status = "okay";
};

5
arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts
View File

@@ -447,9 +447,8 @@ &i2c2 {
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
/* NXP SE97BTP with temperature sensor + eeprom */
se97_1c: temperature-sensor-eeprom@1c {
compatible = "nxp,se97", "jedec,jc-42.4-temp";
se97_1c: temperature-sensor@1c {
compatible = "nxp,se97b", "jedec,jc-42.4-temp";
reg = <0x1c>;
};

5
arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi
View File

@@ -63,9 +63,8 @@ &i2c1 {
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
/* NXP SE97BTP with temperature sensor + eeprom */
se97: temperature-sensor-eeprom@1b {
compatible = "nxp,se97", "jedec,jc-42.4-temp";
se97: temperature-sensor@1b {
compatible = "nxp,se97b", "jedec,jc-42.4-temp";
reg = <0x1b>;
};

7
arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
View File

@@ -593,13 +593,6 @@ &pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio2 17 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
<&clk IMX8MP_CLK_PCIE_ROOT>,
<&clk IMX8MP_CLK_HSIO_AXI>;
clock-names = "pcie", "pcie_aux", "pcie_bus";
assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
assigned-clock-rates = <10000000>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
status = "okay";
};

116
arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi
View File

@@ -3,8 +3,6 @@
* Copyright 2022 Toradex
*/
#include "imx8mp-verdin-dahlia.dtsi"
/ {
/* TODO: Audio Codec */
@@ -21,16 +19,99 @@ reg_eth2phy: regulator-eth2phy {
};
};
&backlight {
power-supply = <&reg_3p3v>;
};
/* Verdin SPI_1 */
&ecspi1 {
status = "okay";
};
/* EEPROM on display adapter boards */
&eeprom_display_adapter {
status = "okay";
};
/* EEPROM on Verdin Development board */
&eeprom_carrier_board {
status = "okay";
};
&eqos {
status = "okay";
};
&fec {
phy-supply = <&reg_eth2phy>;
status = "okay";
};
&flexcan1 {
status = "okay";
};
&flexcan2 {
status = "okay";
};
/* Verdin QSPI_1 */
&flexspi {
status = "okay";
};
&gpio_expander_21 {
status = "okay";
vcc-supply = <&reg_1p8v>;
};
/* Current measurement into module VCC */
&hwmon {
status = "okay";
};
&hwmon_temp {
vs-supply = <&reg_1p8v>;
status = "okay";
};
/* Verdin I2C_2_DSI */
&i2c2 {
status = "okay";
};
&i2c3 {
status = "okay";
};
/* Verdin I2C_1 */
&i2c4 {
status = "okay";
/* TODO: Audio Codec */
};
/* TODO: Verdin PCIE_1 */
/* Verdin PWM_1 */
&pwm1 {
status = "okay";
};
/* Verdin PWM_2 */
&pwm2 {
status = "okay";
};
/* Verdin PWM_3_DSI */
&pwm3 {
status = "okay";
};
&reg_usdhc2_vmmc {
vin-supply = <&reg_3p3v>;
};
/* TODO: Verdin I2C_1 with Audio Codec */
/* Verdin UART_1, connector X50 through RS485 transceiver */
@@ -38,9 +119,40 @@ &uart1 {
linux,rs485-enabled-at-boot-time;
rs485-rts-active-low;
rs485-rx-during-tx;
status = "okay";
};
/* Verdin UART_2 */
&uart2 {
status = "okay";
};
/* Verdin UART_3, used as the Linux Console */
&uart3 {
status = "okay";
};
/* Verdin USB_1 */
&usb3_0 {
status = "okay";
};
&usb3_phy0 {
status = "okay";
};
/* Verdin USB_2 */
&usb3_1 {
fsl,permanently-attached;
status = "okay";
};
&usb3_phy1 {
status = "okay";
};
/* Limit frequency on dev board due to long traces and bad signal integrity */
&usdhc2 {
max-frequency = <100000000>;
status = "okay";
};

18
arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-yavia.dts Normal file
View File

@@ -0,0 +1,18 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2023 Toradex
*/
/dts-v1/;
#include "imx8mp-verdin.dtsi"
#include "imx8mp-verdin-nonwifi.dtsi"
#include "imx8mp-verdin-yavia.dtsi"
/ {
model = "Toradex Verdin iMX8M Plus on Yavia Board";
compatible = "toradex,verdin-imx8mp-nonwifi-yavia",
"toradex,verdin-imx8mp-nonwifi",
"toradex,verdin-imx8mp",
"fsl,imx8mp";
};

18
arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-yavia.dts Normal file
View File

@@ -0,0 +1,18 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2023 Toradex
*/
/dts-v1/;
#include "imx8mp-verdin.dtsi"
#include "imx8mp-verdin-wifi.dtsi"
#include "imx8mp-verdin-yavia.dtsi"
/ {
model = "Toradex Verdin iMX8M Plus WB on Yavia Board";
compatible = "toradex,verdin-imx8mp-wifi-yavia",
"toradex,verdin-imx8mp-wifi",
"toradex,verdin-imx8mp",
"fsl,imx8mp";
};

213
arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi Normal file
View File

@@ -0,0 +1,213 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2023 Toradex
*/
#include <dt-bindings/leds/common.h>
/ {
/* Carrier Board Supply +V1.8 */
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
regulator-name = "+V1.8_SW";
};
/* Carrier Board Supply +V3.3 */
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "+V3.3_SW";
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_leds_yavia>;
/* SODIMM 52 - LD1_RED */
led-0 {
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_DEBUG;
function-enumerator = <1>;
gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
};
/* SODIMM 54 - LD1_GREEN */
led-1 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_DEBUG;
function-enumerator = <1>;
gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>;
};
/* SODIMM 56 - LD1_BLUE */
led-2 {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_DEBUG;
function-enumerator = <1>;
gpios = <&gpio3 6 GPIO_ACTIVE_HIGH>;
};
/* SODIMM 58 - LD2_RED */
led-3 {
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_DEBUG;
function-enumerator = <2>;
gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>;
};
/* SODIMM 60 - LD2_GREEN */
led-4 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_DEBUG;
function-enumerator = <2>;
gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>;
};
/* SODIMM 62 - LD2_BLUE */
led-5 {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_DEBUG;
function-enumerator = <2>;
gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>;
};
};
};
&backlight {
power-supply = <&reg_3p3v>;
};
/* Verdin SPI_1 */
&ecspi1 {
status = "okay";
};
/* EEPROM on display adapter boards */
&eeprom_display_adapter {
status = "okay";
};
/* EEPROM on Verdin yavia board */
&eeprom_carrier_board {
status = "okay";
};
&eqos {
status = "okay";
};
&flexcan1 {
status = "okay";
};
&hwmon_temp {
status = "okay";
};
/* Verdin I2C_2_DSI */
&i2c2 {
status = "okay";
};
&i2c3 {
status = "okay";
};
&i2c4 {
status = "okay";
};
/* Verdin PCIE_1 */
&pcie {
status = "okay";
};
&pcie_phy{
status = "okay";
};
/* Verdin PWM_1 */
&pwm1 {
status = "okay";
};
/* Verdin PWM_2 */
&pwm2 {
status = "okay";
};
/* Verdin PWM_3_DSI */
&pwm3 {
status = "okay";
};
&reg_usdhc2_vmmc {
vin-supply = <&reg_3p3v>;
};
/* Verdin UART_1 */
&uart1 {
status = "okay";
};
/* Verdin UART_2 */
&uart2 {
status = "okay";
};
/* Verdin UART_3, used as the Linux Console */
&uart3 {
status = "okay";
};
/* Verdin USB_1 */
&usb3_phy0 {
status = "okay";
};
&usb3_0 {
status = "okay";
};
&usb_dwc3_0 {
status = "okay";
};
/* Verdin USB_2 */
&usb3_phy1 {
status = "okay";
};
&usb3_1 {
status = "okay";
};
&usb_dwc3_1 {
disable-over-current;
status = "okay";
};
/* Verdin SD_1 */
&usdhc2 {
status = "okay";
};
&iomuxc {
pinctrl_leds_yavia: ledsyaviagrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x106 /* SODIMM 52 */
MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x106 /* SODIMM 54 */
MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x106 /* SODIMM 56 */
MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x106 /* SODIMM 58 */
MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x106 /* SODIMM 60 */
MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x106 /* SODIMM 62 */
>;
};
pinctrl_gpios_ext_yavia: gpiosextyaviagrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_CE1_B__GPIO3_IO02 0x106 /* SODIMM 64 */
MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x106 /* SODIMM 66 */
>;
};
};

3
arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
View File

@@ -50,7 +50,7 @@ gpio-keys {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
button-wakeup {
key-wakeup {
debounce-interval = <10>;
/* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */
gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
@@ -453,7 +453,6 @@ pca9450: pmic@25 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
reg = <0x25>;
sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
/*
* The bootloader is expected to switch on LDO4 for the on-module +V3.3_ADC and the

349
arch/arm64/boot/dts/freescale/imx8mp.dtsi
View File

@@ -380,6 +380,8 @@ tmu: tmu@30260000 {
compatible = "fsl,imx8mp-tmu";
reg = <0x30260000 0x10000>;
clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>;
nvmem-cells = <&tmu_calib>;
nvmem-cell-names = "calib";
#thermal-sensor-cells = <1>;
};
@@ -412,7 +414,7 @@ iomuxc: pinctrl@30330000 {
reg = <0x30330000 0x10000>;
};
gpr: iomuxc-gpr@30340000 {
gpr: syscon@30340000 {
compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
reg = <0x30340000 0x10000>;
};
@@ -425,21 +427,38 @@ ocotp: efuse@30350000 {
#address-cells = <1>;
#size-cells = <1>;
imx8mp_uid: unique-id@420 {
/*
* The register address below maps to the MX8M
* Fusemap Description Table entries this way.
* Assuming
* reg = <ADDR SIZE>;
* then
* Fuse Address = (ADDR * 4) + 0x400
* Note that if SIZE is greater than 4, then
* each subsequent fuse is located at offset
* +0x10 in Fusemap Description Table (e.g.
* reg = <0x8 0x8> describes fuses 0x420 and
* 0x430).
*/
imx8mp_uid: unique-id@8 { /* 0x420-0x430 */
reg = <0x8 0x8>;
};
cpu_speed_grade: speed-grade@10 {
cpu_speed_grade: speed-grade@10 { /* 0x440 */
reg = <0x10 4>;
};
eth_mac1: mac-address@90 {
eth_mac1: mac-address@90 { /* 0x640 */
reg = <0x90 6>;
};
eth_mac2: mac-address@96 {
eth_mac2: mac-address@96 { /* 0x658 */
reg = <0x96 6>;
};
tmu_calib: calib@264 { /* 0xd90-0xdc0 */
reg = <0x264 0x10>;
};
};
anatop: clock-controller@30360000 {
@@ -711,121 +730,129 @@ aips3: bus@30800000 {
#size-cells = <1>;
ranges;
ecspi1: spi@30820000 {
spba-bus@30800000 {
compatible = "fsl,spba-bus", "simple-bus";
reg = <0x30800000 0x100000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
reg = <0x30820000 0x10000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,
<&clk IMX8MP_CLK_ECSPI1_ROOT>;
clock-names = "ipg", "per";
assigned-clock-rates = <80000000>;
assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
#size-cells = <1>;
ranges;
ecspi2: spi@30830000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
reg = <0x30830000 0x10000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
<&clk IMX8MP_CLK_ECSPI2_ROOT>;
clock-names = "ipg", "per";
assigned-clock-rates = <80000000>;
assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
ecspi1: spi@30820000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
reg = <0x30820000 0x10000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,
<&clk IMX8MP_CLK_ECSPI1_ROOT>;
clock-names = "ipg", "per";
assigned-clock-rates = <80000000>;
assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
ecspi3: spi@30840000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
reg = <0x30840000 0x10000>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,
<&clk IMX8MP_CLK_ECSPI3_ROOT>;
clock-names = "ipg", "per";
assigned-clock-rates = <80000000>;
assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
ecspi2: spi@30830000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
reg = <0x30830000 0x10000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
<&clk IMX8MP_CLK_ECSPI2_ROOT>;
clock-names = "ipg", "per";
assigned-clock-rates = <80000000>;
assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
uart1: serial@30860000 {
compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
reg = <0x30860000 0x10000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_UART1_ROOT>,
<&clk IMX8MP_CLK_UART1_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
dma-names = "rx", "tx";
status = "disabled";
};
ecspi3: spi@30840000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
reg = <0x30840000 0x10000>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,
<&clk IMX8MP_CLK_ECSPI3_ROOT>;
clock-names = "ipg", "per";
assigned-clock-rates = <80000000>;
assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
uart3: serial@30880000 {
compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
reg = <0x30880000 0x10000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_UART3_ROOT>,
<&clk IMX8MP_CLK_UART3_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
dma-names = "rx", "tx";
status = "disabled";
};
uart1: serial@30860000 {
compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
reg = <0x30860000 0x10000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_UART1_ROOT>,
<&clk IMX8MP_CLK_UART1_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
dma-names = "rx", "tx";
status = "disabled";
};
uart2: serial@30890000 {
compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
reg = <0x30890000 0x10000>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_UART2_ROOT>,
<&clk IMX8MP_CLK_UART2_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
dma-names = "rx", "tx";
status = "disabled";
};
uart3: serial@30880000 {
compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
reg = <0x30880000 0x10000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_UART3_ROOT>,
<&clk IMX8MP_CLK_UART3_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
dma-names = "rx", "tx";
status = "disabled";
};
flexcan1: can@308c0000 {
compatible = "fsl,imx8mp-flexcan";
reg = <0x308c0000 0x10000>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
<&clk IMX8MP_CLK_CAN1_ROOT>;
clock-names = "ipg", "per";
assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
assigned-clock-rates = <40000000>;
fsl,clk-source = /bits/ 8 <0>;
fsl,stop-mode = <&gpr 0x10 4>;
status = "disabled";
};
uart2: serial@30890000 {
compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
reg = <0x30890000 0x10000>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_UART2_ROOT>,
<&clk IMX8MP_CLK_UART2_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
dma-names = "rx", "tx";
status = "disabled";
};
flexcan2: can@308d0000 {
compatible = "fsl,imx8mp-flexcan";
reg = <0x308d0000 0x10000>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
<&clk IMX8MP_CLK_CAN2_ROOT>;
clock-names = "ipg", "per";
assigned-clocks = <&clk IMX8MP_CLK_CAN2>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
assigned-clock-rates = <40000000>;
fsl,clk-source = /bits/ 8 <0>;
fsl,stop-mode = <&gpr 0x10 5>;
status = "disabled";
flexcan1: can@308c0000 {
compatible = "fsl,imx8mp-flexcan";
reg = <0x308c0000 0x10000>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
<&clk IMX8MP_CLK_CAN1_ROOT>;
clock-names = "ipg", "per";
assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
assigned-clock-rates = <40000000>;
fsl,clk-source = /bits/ 8 <0>;
fsl,stop-mode = <&gpr 0x10 4>;
status = "disabled";
};
flexcan2: can@308d0000 {
compatible = "fsl,imx8mp-flexcan";
reg = <0x308d0000 0x10000>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
<&clk IMX8MP_CLK_CAN2_ROOT>;
clock-names = "ipg", "per";
assigned-clocks = <&clk IMX8MP_CLK_CAN2>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
assigned-clock-rates = <40000000>;
fsl,clk-source = /bits/ 8 <0>;
fsl,stop-mode = <&gpr 0x10 5>;
status = "disabled";
};
};
crypto: crypto@30900000 {
@@ -1098,10 +1125,35 @@ aips4: bus@32c00000 {
#size-cells = <1>;
ranges;
lcdif2: display-controller@32e90000 {
compatible = "fsl,imx8mp-lcdif";
reg = <0x32e90000 0x238>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
clock-names = "pix", "axi", "disp_axi";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,
<&clk IMX8MP_VIDEO_PLL1>;
assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>,
<&clk IMX8MP_VIDEO_PLL1_REF_SEL>;
assigned-clock-rates = <0>, <1039500000>;
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_2>;
status = "disabled";
port {
lcdif2_to_ldb: endpoint {
remote-endpoint = <&ldb_from_lcdif2>;
};
};
};
media_blk_ctrl: blk-ctrl@32ec0000 {
compatible = "fsl,imx8mp-media-blk-ctrl",
"syscon";
"simple-bus", "syscon";
reg = <0x32ec0000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
power-domains = <&pgc_mediamix>,
<&pgc_mipi_phy1>,
<&pgc_mipi_phy1>,
@@ -1146,6 +1198,44 @@ media_blk_ctrl: blk-ctrl@32ec0000 {
assigned-clock-rates = <500000000>, <200000000>;
#power-domain-cells = <1>;
lvds_bridge: bridge@5c {
compatible = "fsl,imx8mp-ldb";
clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;
clock-names = "ldb";
reg = <0x5c 0x4>, <0x128 0x4>;
reg-names = "ldb", "lvds";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;
assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
ldb_from_lcdif2: endpoint {
remote-endpoint = <&lcdif2_to_ldb>;
};
};
port@1 {
reg = <1>;
ldb_lvds_ch0: endpoint {
};
};
port@2 {
reg = <2>;
ldb_lvds_ch1: endpoint {
};
};
};
};
};
pcie_phy: pcie-phy@32f00000 {
@@ -1176,6 +1266,7 @@ hsio_blk_ctrl: blk-ctrl@32f10000 {
<&noc IMX8MP_ICM_PCIE &noc IMX8MP_ICN_HSIO>;
interconnect-names = "noc-pcie", "usb1", "usb2", "pcie";
#power-domain-cells = <1>;
#clock-cells = <0>;
};
};
@@ -1183,6 +1274,13 @@ pcie: pcie@33800000 {
compatible = "fsl,imx8mp-pcie";
reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
reg-names = "dbi", "config";
clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
<&clk IMX8MP_CLK_HSIO_AXI>,
<&clk IMX8MP_CLK_PCIE_ROOT>;
clock-names = "pcie", "pcie_bus", "pcie_aux";
assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
assigned-clock-rates = <10000000>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
@@ -1241,6 +1339,28 @@ gpu2d: gpu@38008000 {
power-domains = <&pgc_gpu2d>;
};
vpu_g1: video-codec@38300000 {
compatible = "nxp,imx8mm-vpu-g1";
reg = <0x38300000 0x10000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;
assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>;
assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;
assigned-clock-rates = <600000000>;
power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G1>;
};
vpu_g2: video-codec@38310000 {
compatible = "nxp,imx8mq-vpu-g2";
reg = <0x38310000 0x10000>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;
assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
assigned-clock-rates = <500000000>;
power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G2>;
};
vpumix_blk_ctrl: blk-ctrl@38330000 {
compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon";
reg = <0x38330000 0x100>;
@@ -1252,6 +1372,9 @@ vpumix_blk_ctrl: blk-ctrl@38330000 {
<&clk IMX8MP_CLK_VPU_G2_ROOT>,
<&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
clock-names = "g1", "g2", "vc8000e";
assigned-clocks = <&clk IMX8MP_CLK_VPU_BUS>, <&clk IMX8MP_VPU_PLL>;
assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;
assigned-clock-rates = <600000000>, <600000000>;
interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>,
<&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>,
<&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>;

10
arch/arm64/boot/dts/freescale/imx8mq-evk.dts
View File

@@ -356,10 +356,9 @@ &pcie0 {
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
<&clk IMX8MQ_CLK_PCIE1_AUX>,
<&pcie0_refclk>,
<&clk IMX8MQ_CLK_PCIE1_PHY>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
<&clk IMX8MQ_CLK_PCIE1_AUX>;
vph-supply = <&vgen5_reg>;
status = "okay";
};
@@ -369,10 +368,9 @@ &pcie1 {
pinctrl-0 = <&pinctrl_pcie1>;
reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
<&clk IMX8MQ_CLK_PCIE2_AUX>,
<&pcie0_refclk>,
<&clk IMX8MQ_CLK_PCIE2_PHY>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
<&clk IMX8MQ_CLK_PCIE2_AUX>;
vpcie-supply = <&reg_pcie1>;
vph-supply = <&vgen5_reg>;
status = "okay";

10
arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
View File

@@ -245,20 +245,18 @@ &pcie0 {
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
<&clk IMX8MQ_CLK_PCIE1_AUX>,
<&pcie0_refclk>,
<&clk IMX8MQ_CLK_PCIE1_PHY>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
<&clk IMX8MQ_CLK_PCIE1_AUX>;
status = "okay";
};
/* Intel Ethernet Controller I210/I211 */
&pcie1 {
clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
<&clk IMX8MQ_CLK_PCIE2_AUX>,
<&pcie1_refclk>,
<&clk IMX8MQ_CLK_PCIE2_PHY>,
<&pcie1_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
<&clk IMX8MQ_CLK_PCIE2_AUX>;
fsl,max-link-speed = <1>;
status = "okay";
};

2
arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
View File

@@ -64,7 +64,7 @@ button-3 {
leds {
compatible = "pwm-leds";
led1 {
led-1 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_RED>;
max-brightness = <248>;

32
arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi
View File

@@ -56,27 +56,27 @@ key-vol-up {
};
led-controller {
compatible = "pwm-leds";
compatible = "pwm-leds-multicolor";
led-0 {
multi-led {
color = <LED_COLOR_ID_RGB>;
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_BLUE>;
max-brightness = <248>;
pwms = <&pwm2 0 50000 0>;
};
led-1 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
max-brightness = <248>;
pwms = <&pwm4 0 50000 0>;
};
led-0 {
color = <LED_COLOR_ID_BLUE>;
pwms = <&pwm2 0 50000 0>;
};
led-2 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_RED>;
max-brightness = <248>;
pwms = <&pwm3 0 50000 0>;
led-1 {
color = <LED_COLOR_ID_GREEN>;
pwms = <&pwm4 0 50000 0>;
};
led-2 {
color = <LED_COLOR_ID_RED>;
pwms = <&pwm3 0 50000 0>;
};
};
};

5
arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts
View File

@@ -197,10 +197,9 @@ &pcie1 {
pinctrl-0 = <&pinctrl_pcie1>;
reset-gpio = <&gpio3 23 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
<&clk IMX8MQ_CLK_PCIE2_AUX>,
<&pcie1_refclk>,
<&clk IMX8MQ_CLK_PCIE2_PHY>,
<&pcie1_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
<&clk IMX8MQ_CLK_PCIE2_AUX>;
status = "okay";
};

10
arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts
View File

@@ -105,10 +105,9 @@ &led2 {
&pcie0 {
reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
<&clk IMX8MQ_CLK_PCIE1_AUX>,
<&pcie0_refclk>,
<&clk IMX8MQ_CLK_PCIE1_PHY>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
<&clk IMX8MQ_CLK_PCIE1_AUX>;
epdev_on-supply = <&reg_vcc_3v3>;
hard-wired = <1>;
status = "okay";
@@ -120,10 +119,9 @@ &pcie0 {
*/
&pcie1 {
clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
<&clk IMX8MQ_CLK_PCIE2_AUX>,
<&pcie1_refclk>,
<&clk IMX8MQ_CLK_PCIE2_PHY>,
<&pcie1_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
<&clk IMX8MQ_CLK_PCIE2_AUX>;
epdev_on-supply = <&reg_vcc_3v3>;
hard-wired = <1>;
status = "okay";

4
arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi
View File

@@ -194,8 +194,8 @@ vgen6_reg: vgen6 {
};
};
sensor0: temperature-sensor-eeprom@1b {
compatible = "nxp,se97", "jedec,jc-42.4-temp";
sensor0: temperature-sensor@1b {
compatible = "nxp,se97b", "jedec,jc-42.4-temp";
reg = <0x1b>;
};

12
arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi
View File

@@ -490,7 +490,7 @@ &uart2 {
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
rave-sp {
mcu {
compatible = "zii,rave-sp-rdu2";
current-speed = <1000000>;
#address-cells = <1>;
@@ -551,10 +551,9 @@ &pcie0 {
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
<&clk IMX8MQ_CLK_PCIE1_AUX>,
<&pcie0_refclk>,
<&clk IMX8MQ_CLK_PCIE1_PHY>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
<&clk IMX8MQ_CLK_PCIE1_AUX>;
vph-supply = <&vgen5_reg>;
status = "okay";
};
@@ -564,10 +563,9 @@ &pcie1 {
pinctrl-0 = <&pinctrl_pcie1>;
reset-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
<&clk IMX8MQ_CLK_PCIE2_AUX>,
<&pcie1_refclk>,
<&clk IMX8MQ_CLK_PCIE2_PHY>,
<&pcie1_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
<&clk IMX8MQ_CLK_PCIE2_AUX>;
vph-supply = <&vgen5_reg>;
status = "okay";
};

32
arch/arm64/boot/dts/freescale/imx8mq.dtsi
View File

@@ -575,8 +575,7 @@ iomuxc: pinctrl@30330000 {
};
iomuxc_gpr: syscon@30340000 {
compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr",
"syscon", "simple-mfd";
compatible = "fsl,imx8mq-iomuxc-gpr", "syscon", "simple-mfd";
reg = <0x30340000 0x10000>;
mux: mux-controller {
@@ -593,15 +592,28 @@ ocotp: efuse@30350000 {
#address-cells = <1>;
#size-cells = <1>;
imx8mq_uid: soc-uid@410 {
/*
* The register address below maps to the MX8M
* Fusemap Description Table entries this way.
* Assuming
* reg = <ADDR SIZE>;
* then
* Fuse Address = (ADDR * 4) + 0x400
* Note that if SIZE is greater than 4, then
* each subsequent fuse is located at offset
* +0x10 in Fusemap Description Table (e.g.
* reg = <0x4 0x8> describes fuses 0x410 and
* 0x420).
*/
imx8mq_uid: soc-uid@4 { /* 0x410-0x420 */
reg = <0x4 0x8>;
};
cpu_speed_grade: speed-grade@10 {
cpu_speed_grade: speed-grade@10 { /* 0x440 */
reg = <0x10 4>;
};
fec_mac_address: mac-address@90 {
fec_mac_address: mac-address@90 { /* 0x640 */
reg = <0x90 6>;
};
};
@@ -1530,6 +1542,11 @@ pcie0: pcie@33800000 {
<0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
fsl,max-link-speed = <2>;
linux,pci-domain = <0>;
clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
<&clk IMX8MQ_CLK_PCIE1_PHY>,
<&clk IMX8MQ_CLK_PCIE1_PHY>,
<&clk IMX8MQ_CLK_PCIE1_AUX>;
clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
power-domains = <&pgc_pcie>;
resets = <&src IMX8MQ_RESET_PCIEPHY>,
<&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
@@ -1567,6 +1584,11 @@ pcie1: pcie@33c00000 {
<0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
fsl,max-link-speed = <2>;
linux,pci-domain = <1>;
clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
<&clk IMX8MQ_CLK_PCIE2_PHY>,
<&clk IMX8MQ_CLK_PCIE2_PHY>,
<&clk IMX8MQ_CLK_PCIE2_AUX>;
clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
power-domains = <&pgc_pcie>;
resets = <&src IMX8MQ_RESET_PCIEPHY2>,
<&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,

12
arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
View File

@@ -15,6 +15,13 @@ chosen {
stdout-path = &lpuart1;
};
reg_vref_1v8: regulator-adc-vref {
compatible = "regulator-fixed";
regulator-name = "vref_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
@@ -27,6 +34,11 @@ reg_usdhc2_vmmc: regulator-usdhc2 {
};
};
&adc1 {
vref-supply = <&reg_vref_1v8>;
status = "okay";
};
&mu1 {
status = "okay";
};

41
arch/arm64/boot/dts/freescale/imx93.dtsi
View File

@@ -223,6 +223,20 @@ lpuart2: serial@44390000 {
status = "disabled";
};
flexcan1: can@443a0000 {
compatible = "fsl,imx93-flexcan";
reg = <0x443a0000 0x10000>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_BUS_AON>,
<&clk IMX93_CLK_CAN1_GATE>;
clock-names = "ipg", "per";
assigned-clocks = <&clk IMX93_CLK_CAN1>;
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
assigned-clock-rates = <40000000>;
fsl,clk-source = /bits/ 8 <0>;
status = "disabled";
};
iomuxc: pinctrl@443c0000 {
compatible = "fsl,imx93-iomuxc";
reg = <0x443c0000 0x10000>;
@@ -266,6 +280,19 @@ anatop: anatop@44480000 {
compatible = "fsl,imx93-anatop", "syscon";
reg = <0x44480000 0x10000>;
};
adc1: adc@44530000 {
compatible = "nxp,imx93-adc";
reg = <0x44530000 0x10000>;
interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_ADC1_GATE>;
clock-names = "ipg";
#io-channel-cells = <1>;
status = "disabled";
};
};
aips2: bus@42000000 {
@@ -393,6 +420,20 @@ lpuart6: serial@425a0000 {
status = "disabled";
};
flexcan2: can@425b0000 {
compatible = "fsl,imx93-flexcan";
reg = <0x425b0000 0x10000>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
<&clk IMX93_CLK_CAN2_GATE>;
clock-names = "ipg", "per";
assigned-clocks = <&clk IMX93_CLK_CAN2>;
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
assigned-clock-rates = <40000000>;
fsl,clk-source = /bits/ 8 <0>;
status = "disabled";
};
lpuart7: serial@42690000 {
compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
reg = <0x42690000 0x1000>;

4
arch/arm64/boot/dts/freescale/mba8mx.dtsi
View File

@@ -206,8 +206,8 @@ tlv320aic3x04: audio-codec@18 {
ldoin-supply = <&reg_vcc_3v3>;
};
sensor1: sensor@1f {
compatible = "nxp,se97", "jedec,jc-42.4-temp";
sensor1: temperator-sensor@1f {
compatible = "nxp,se97b", "jedec,jc-42.4-temp";
reg = <0x1f>;
};