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drm/amd/display: Add DCN35 HUBBUB
[Why & How] Add HUBBUB handling for DCN35. Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Qingqing Zhuo
committed by
Alex Deucher
Alex Deucher
parent
74c06a327d
commit
4435fc4240
573
drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hubbub.c
Normal file
573
drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hubbub.c
Normal file
@@ -0,0 +1,573 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright 2023 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "dcn30/dcn30_hubbub.h"
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#include "dcn31/dcn31_hubbub.h"
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#include "dcn32/dcn32_hubbub.h"
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#include "dcn35_hubbub.h"
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#include "dm_services.h"
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#include "reg_helper.h"
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#define CTX \
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hubbub2->base.ctx
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#define DC_LOGGER \
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hubbub2->base.ctx->logger
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#define REG(reg)\
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hubbub2->regs->reg
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#undef FN
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#define FN(reg_name, field_name) \
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hubbub2->shifts->field_name, hubbub2->masks->field_name
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#define DCN35_CRB_SEGMENT_SIZE_KB 64
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static void dcn35_init_crb(struct hubbub *hubbub)
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{
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struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
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REG_GET(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT,
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&hubbub2->det0_size);
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REG_GET(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT,
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&hubbub2->det1_size);
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REG_GET(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT,
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&hubbub2->det2_size);
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REG_GET(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT,
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&hubbub2->det3_size);
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REG_GET(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE_CURRENT,
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&hubbub2->compbuf_size_segments);
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REG_SET_2(COMPBUF_RESERVED_SPACE, 0,
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COMPBUF_RESERVED_SPACE_64B, hubbub2->pixel_chunk_size / 32,
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COMPBUF_RESERVED_SPACE_ZS, hubbub2->pixel_chunk_size / 128);
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REG_UPDATE(DCHUBBUB_DEBUG_CTRL_0, DET_DEPTH, 0x47F);
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}
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static void dcn35_program_compbuf_size(struct hubbub *hubbub, unsigned int compbuf_size_kb, bool safe_to_increase)
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{
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struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
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unsigned int compbuf_size_segments = (compbuf_size_kb + DCN35_CRB_SEGMENT_SIZE_KB - 1) / DCN35_CRB_SEGMENT_SIZE_KB;
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if (safe_to_increase || compbuf_size_segments <= hubbub2->compbuf_size_segments) {
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if (compbuf_size_segments > hubbub2->compbuf_size_segments) {
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REG_WAIT(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, hubbub2->det0_size, 1, 100);
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REG_WAIT(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT, hubbub2->det1_size, 1, 100);
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REG_WAIT(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT, hubbub2->det2_size, 1, 100);
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REG_WAIT(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT, hubbub2->det3_size, 1, 100);
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}
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/* Should never be hit, if it is we have an erroneous hw config*/
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ASSERT(hubbub2->det0_size + hubbub2->det1_size + hubbub2->det2_size
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+ hubbub2->det3_size + compbuf_size_segments <= hubbub2->crb_size_segs);
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REG_UPDATE(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE, compbuf_size_segments);
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hubbub2->compbuf_size_segments = compbuf_size_segments;
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ASSERT(REG_GET(DCHUBBUB_COMPBUF_CTRL, CONFIG_ERROR, &compbuf_size_segments) && !compbuf_size_segments);
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}
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}
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static uint32_t convert_and_clamp(
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uint32_t wm_ns,
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uint32_t refclk_mhz,
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uint32_t clamp_value)
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{
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uint32_t ret_val = 0;
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ret_val = wm_ns * refclk_mhz;
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ret_val /= 1000;
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if (ret_val > clamp_value)
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ret_val = clamp_value;
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return ret_val;
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}
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static bool hubbub35_program_stutter_z8_watermarks(
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struct hubbub *hubbub,
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struct dcn_watermark_set *watermarks,
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unsigned int refclk_mhz,
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bool safe_to_lower)
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{
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struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
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uint32_t prog_wm_value;
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bool wm_pending = false;
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/* clock state A */
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if (watermarks->a.cstate_pstate.cstate_enter_plus_exit_z8_ns
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> hubbub2->watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns) {
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hubbub2->watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns =
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watermarks->a.cstate_pstate.cstate_enter_plus_exit_z8_ns;
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prog_wm_value = convert_and_clamp(
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watermarks->a.cstate_pstate.cstate_enter_plus_exit_z8_ns,
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refclk_mhz, 0xffff);
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REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A, 0,
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DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A, prog_wm_value);
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DC_LOG_BANDWIDTH_CALCS("SR_ENTER_WATERMARK_Z8_A calculated =%d\n"
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"HW register value = 0x%x\n",
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watermarks->a.cstate_pstate.cstate_enter_plus_exit_z8_ns, prog_wm_value);
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} else if (watermarks->a.cstate_pstate.cstate_enter_plus_exit_z8_ns
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< hubbub2->watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns)
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wm_pending = true;
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if (safe_to_lower || watermarks->a.cstate_pstate.cstate_exit_z8_ns
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> hubbub2->watermarks.a.cstate_pstate.cstate_exit_z8_ns) {
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hubbub2->watermarks.a.cstate_pstate.cstate_exit_z8_ns =
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watermarks->a.cstate_pstate.cstate_exit_z8_ns;
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prog_wm_value = convert_and_clamp(
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watermarks->a.cstate_pstate.cstate_exit_z8_ns,
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refclk_mhz, 0xffff);
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REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A, 0,
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DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A, prog_wm_value);
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DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_Z8_A calculated =%d\n"
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"HW register value = 0x%x\n",
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watermarks->a.cstate_pstate.cstate_exit_z8_ns, prog_wm_value);
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} else if (watermarks->a.cstate_pstate.cstate_exit_z8_ns
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< hubbub2->watermarks.a.cstate_pstate.cstate_exit_z8_ns)
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wm_pending = true;
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/* clock state B */
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if (safe_to_lower || watermarks->b.cstate_pstate.cstate_enter_plus_exit_z8_ns
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> hubbub2->watermarks.b.cstate_pstate.cstate_enter_plus_exit_z8_ns) {
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hubbub2->watermarks.b.cstate_pstate.cstate_enter_plus_exit_z8_ns =
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watermarks->b.cstate_pstate.cstate_enter_plus_exit_z8_ns;
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prog_wm_value = convert_and_clamp(
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watermarks->b.cstate_pstate.cstate_enter_plus_exit_z8_ns,
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refclk_mhz, 0xffff);
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REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B, 0,
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DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B, prog_wm_value);
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DC_LOG_BANDWIDTH_CALCS("SR_ENTER_WATERMARK_Z8_B calculated =%d\n"
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"HW register value = 0x%x\n",
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watermarks->b.cstate_pstate.cstate_enter_plus_exit_z8_ns, prog_wm_value);
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} else if (watermarks->b.cstate_pstate.cstate_enter_plus_exit_z8_ns
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< hubbub2->watermarks.b.cstate_pstate.cstate_enter_plus_exit_z8_ns)
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wm_pending = true;
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if (safe_to_lower || watermarks->b.cstate_pstate.cstate_exit_z8_ns
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> hubbub2->watermarks.b.cstate_pstate.cstate_exit_z8_ns) {
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hubbub2->watermarks.b.cstate_pstate.cstate_exit_z8_ns =
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watermarks->b.cstate_pstate.cstate_exit_z8_ns;
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prog_wm_value = convert_and_clamp(
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watermarks->b.cstate_pstate.cstate_exit_z8_ns,
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refclk_mhz, 0xffff);
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REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, 0,
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DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, prog_wm_value);
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DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_Z8_B calculated =%d\n"
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"HW register value = 0x%x\n",
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watermarks->b.cstate_pstate.cstate_exit_z8_ns, prog_wm_value);
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} else if (watermarks->b.cstate_pstate.cstate_exit_z8_ns
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< hubbub2->watermarks.b.cstate_pstate.cstate_exit_z8_ns)
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wm_pending = true;
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/* clock state C */
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if (safe_to_lower || watermarks->c.cstate_pstate.cstate_enter_plus_exit_z8_ns
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> hubbub2->watermarks.c.cstate_pstate.cstate_enter_plus_exit_z8_ns) {
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hubbub2->watermarks.c.cstate_pstate.cstate_enter_plus_exit_z8_ns =
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watermarks->c.cstate_pstate.cstate_enter_plus_exit_z8_ns;
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prog_wm_value = convert_and_clamp(
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watermarks->c.cstate_pstate.cstate_enter_plus_exit_z8_ns,
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refclk_mhz, 0xffff);
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REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C, 0,
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DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C, prog_wm_value);
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DC_LOG_BANDWIDTH_CALCS("SR_ENTER_WATERMARK_Z8_C calculated =%d\n"
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"HW register value = 0x%x\n",
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watermarks->c.cstate_pstate.cstate_enter_plus_exit_z8_ns, prog_wm_value);
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} else if (watermarks->c.cstate_pstate.cstate_enter_plus_exit_z8_ns
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< hubbub2->watermarks.c.cstate_pstate.cstate_enter_plus_exit_z8_ns)
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wm_pending = true;
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if (safe_to_lower || watermarks->c.cstate_pstate.cstate_exit_z8_ns
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> hubbub2->watermarks.c.cstate_pstate.cstate_exit_z8_ns) {
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hubbub2->watermarks.c.cstate_pstate.cstate_exit_z8_ns =
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watermarks->c.cstate_pstate.cstate_exit_z8_ns;
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prog_wm_value = convert_and_clamp(
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watermarks->c.cstate_pstate.cstate_exit_z8_ns,
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refclk_mhz, 0xffff);
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REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, 0,
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DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, prog_wm_value);
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DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_Z8_C calculated =%d\n"
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"HW register value = 0x%x\n",
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watermarks->c.cstate_pstate.cstate_exit_z8_ns, prog_wm_value);
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} else if (watermarks->c.cstate_pstate.cstate_exit_z8_ns
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< hubbub2->watermarks.c.cstate_pstate.cstate_exit_z8_ns)
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wm_pending = true;
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/* clock state D */
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if (safe_to_lower || watermarks->d.cstate_pstate.cstate_enter_plus_exit_z8_ns
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> hubbub2->watermarks.d.cstate_pstate.cstate_enter_plus_exit_z8_ns) {
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hubbub2->watermarks.d.cstate_pstate.cstate_enter_plus_exit_z8_ns =
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watermarks->d.cstate_pstate.cstate_enter_plus_exit_z8_ns;
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prog_wm_value = convert_and_clamp(
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watermarks->d.cstate_pstate.cstate_enter_plus_exit_z8_ns,
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refclk_mhz, 0xffff);
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REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D, 0,
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DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D, prog_wm_value);
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DC_LOG_BANDWIDTH_CALCS("SR_ENTER_WATERMARK_Z8_D calculated =%d\n"
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"HW register value = 0x%x\n",
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watermarks->d.cstate_pstate.cstate_enter_plus_exit_z8_ns, prog_wm_value);
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} else if (watermarks->d.cstate_pstate.cstate_enter_plus_exit_z8_ns
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< hubbub2->watermarks.d.cstate_pstate.cstate_enter_plus_exit_z8_ns)
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wm_pending = true;
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if (safe_to_lower || watermarks->d.cstate_pstate.cstate_exit_z8_ns
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> hubbub2->watermarks.d.cstate_pstate.cstate_exit_z8_ns) {
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hubbub2->watermarks.d.cstate_pstate.cstate_exit_z8_ns =
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watermarks->d.cstate_pstate.cstate_exit_z8_ns;
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prog_wm_value = convert_and_clamp(
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watermarks->d.cstate_pstate.cstate_exit_z8_ns,
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refclk_mhz, 0xffff);
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REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, 0,
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DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, prog_wm_value);
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DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_Z8_D calculated =%d\n"
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"HW register value = 0x%x\n",
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watermarks->d.cstate_pstate.cstate_exit_z8_ns, prog_wm_value);
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} else if (watermarks->d.cstate_pstate.cstate_exit_z8_ns
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< hubbub2->watermarks.d.cstate_pstate.cstate_exit_z8_ns)
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wm_pending = true;
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return wm_pending;
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}
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static void hubbub35_get_dchub_ref_freq(struct hubbub *hubbub,
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unsigned int dccg_ref_freq_inKhz,
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unsigned int *dchub_ref_freq_inKhz)
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{
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struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
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uint32_t ref_div = 0;
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uint32_t ref_en = 0;
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unsigned int dc_refclk_khz = 24000;
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REG_GET_2(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, &ref_div,
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DCHUBBUB_GLOBAL_TIMER_ENABLE, &ref_en);
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if (ref_en) {
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if (ref_div == 2)
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*dchub_ref_freq_inKhz = dc_refclk_khz / 2;
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else
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*dchub_ref_freq_inKhz = dc_refclk_khz;
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/*
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* The external Reference Clock may change based on the board or
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* platform requirements and the programmable integer divide must
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* be programmed to provide a suitable DLG RefClk frequency between
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* a minimum of 20MHz and maximum of 50MHz
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*/
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if (*dchub_ref_freq_inKhz < 20000 || *dchub_ref_freq_inKhz > 50000)
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ASSERT_CRITICAL(false);
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return;
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} else {
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*dchub_ref_freq_inKhz = dc_refclk_khz;
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/*init sequence issue on bringup patch*/
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REG_UPDATE_2(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 1,
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DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
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// HUBBUB global timer must be enabled.
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ASSERT_CRITICAL(false);
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return;
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}
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}
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static bool hubbub35_program_watermarks(
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struct hubbub *hubbub,
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struct dcn_watermark_set *watermarks,
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unsigned int refclk_mhz,
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bool safe_to_lower)
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{
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bool wm_pending = false;
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struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
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if (hubbub32_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))
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wm_pending = true;
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if (hubbub32_program_stutter_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))
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wm_pending = true;
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if (hubbub32_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))
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wm_pending = true;
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if (hubbub32_program_usr_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))
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wm_pending = true;
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if (hubbub35_program_stutter_z8_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))
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wm_pending = true;
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REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0,
|
||||
DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz);
|
||||
REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,
|
||||
DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 0xFF);/*hw delta*/
|
||||
|
||||
hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);
|
||||
|
||||
hubbub32_force_usr_retraining_allow(hubbub, hubbub->ctx->dc->debug.force_usr_allow);
|
||||
|
||||
return wm_pending;
|
||||
}
|
||||
|
||||
/* Copy values from WM set A to all other sets */
|
||||
static void hubbub35_init_watermarks(struct hubbub *hubbub)
|
||||
{
|
||||
struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
|
||||
uint32_t reg;
|
||||
|
||||
reg = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A);
|
||||
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, reg);
|
||||
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, reg);
|
||||
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, reg);
|
||||
|
||||
reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A);
|
||||
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, reg);
|
||||
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, reg);
|
||||
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, reg);
|
||||
|
||||
reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A);
|
||||
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, reg);
|
||||
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, reg);
|
||||
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, reg);
|
||||
|
||||
reg = REG_READ(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A);
|
||||
REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, reg);
|
||||
REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, reg);
|
||||
REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, reg);
|
||||
|
||||
reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);
|
||||
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, reg);
|
||||
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, reg);
|
||||
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, reg);
|
||||
|
||||
reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);
|
||||
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, reg);
|
||||
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, reg);
|
||||
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, reg);
|
||||
|
||||
reg = REG_READ(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A);
|
||||
REG_WRITE(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, reg);
|
||||
REG_WRITE(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C, reg);
|
||||
REG_WRITE(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D, reg);
|
||||
|
||||
reg = REG_READ(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A);
|
||||
REG_WRITE(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, reg);
|
||||
REG_WRITE(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C, reg);
|
||||
REG_WRITE(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D, reg);
|
||||
|
||||
reg = REG_READ(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A);
|
||||
REG_WRITE(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, reg);
|
||||
REG_WRITE(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C, reg);
|
||||
REG_WRITE(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D, reg);
|
||||
}
|
||||
|
||||
static void hubbub35_wm_read_state(struct hubbub *hubbub,
|
||||
struct dcn_hubbub_wm *wm)
|
||||
{
|
||||
struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
|
||||
struct dcn_hubbub_wm_set *s;
|
||||
|
||||
memset(wm, 0, sizeof(struct dcn_hubbub_wm));
|
||||
|
||||
s = &wm->sets[0];
|
||||
s->wm_set = 0;
|
||||
REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A,
|
||||
DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, &s->data_urgent);
|
||||
|
||||
REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A,
|
||||
DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, &s->sr_enter);
|
||||
|
||||
REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A,
|
||||
DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, &s->sr_exit);
|
||||
|
||||
REG_GET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A,
|
||||
DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A, &s->dram_clk_change);
|
||||
|
||||
REG_GET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A,
|
||||
DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A, &s->usr_retrain);
|
||||
|
||||
REG_GET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A,
|
||||
DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A, &s->fclk_pstate_change);
|
||||
|
||||
s = &wm->sets[1];
|
||||
s->wm_set = 1;
|
||||
REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B,
|
||||
DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, &s->data_urgent);
|
||||
|
||||
REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B,
|
||||
DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, &s->sr_enter);
|
||||
|
||||
REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B,
|
||||
DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, &s->sr_exit);
|
||||
|
||||
REG_GET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B,
|
||||
DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, &s->dram_clk_change);
|
||||
|
||||
REG_GET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B,
|
||||
DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, &s->usr_retrain);
|
||||
|
||||
REG_GET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B,
|
||||
DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, &s->fclk_pstate_change);
|
||||
|
||||
s = &wm->sets[2];
|
||||
s->wm_set = 2;
|
||||
REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C,
|
||||
DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, &s->data_urgent);
|
||||
|
||||
REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C,
|
||||
DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, &s->sr_enter);
|
||||
|
||||
REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C,
|
||||
DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, &s->sr_exit);
|
||||
|
||||
REG_GET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C,
|
||||
DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C, &s->dram_clk_change);
|
||||
|
||||
REG_GET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C,
|
||||
DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C, &s->usr_retrain);
|
||||
|
||||
REG_GET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C,
|
||||
DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C, &s->fclk_pstate_change);
|
||||
|
||||
s = &wm->sets[3];
|
||||
s->wm_set = 3;
|
||||
REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D,
|
||||
DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, &s->data_urgent);
|
||||
|
||||
REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D,
|
||||
DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, &s->sr_enter);
|
||||
|
||||
REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D,
|
||||
DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, &s->sr_exit);
|
||||
|
||||
REG_GET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D,
|
||||
DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D, &s->dram_clk_change);
|
||||
|
||||
REG_GET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D,
|
||||
DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D, &s->usr_retrain);
|
||||
|
||||
REG_GET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D,
|
||||
DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D, &s->fclk_pstate_change);
|
||||
}
|
||||
|
||||
static void hubbub35_set_fgcg(struct dcn20_hubbub *hubbub2, bool enable)
|
||||
{
|
||||
REG_UPDATE(DCHUBBUB_CLOCK_CNTL, DCHUBBUB_FGCG_REP_DIS, !enable);
|
||||
}
|
||||
|
||||
static void hubbub35_init(struct hubbub *hubbub)
|
||||
{
|
||||
struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
|
||||
/*Enable clock gaters*/
|
||||
if (hubbub->ctx->dc->debug.disable_clock_gate) {
|
||||
/*done in hwseq*/
|
||||
/*REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);*/
|
||||
|
||||
REG_UPDATE_2(DCHUBBUB_CLOCK_CNTL,
|
||||
DISPCLK_R_DCHUBBUB_GATE_DIS, 0,
|
||||
DCFCLK_R_DCHUBBUB_GATE_DIS, 0);
|
||||
}
|
||||
hubbub35_set_fgcg(hubbub2,
|
||||
hubbub->ctx->dc->debug.enable_fine_grain_clock_gating
|
||||
.bits.dchubbub);
|
||||
/*
|
||||
ignore the "df_pre_cstate_req" from the SDP port control.
|
||||
only the DCN will determine when to connect the SDP port
|
||||
*/
|
||||
REG_UPDATE(DCHUBBUB_SDPIF_CFG0,
|
||||
SDPIF_PORT_CONTROL, 1);
|
||||
/*Set SDP's max outstanding request
|
||||
When set to 1: Max outstanding is 512
|
||||
When set to 0: Max outstanding is 256
|
||||
must set the register back to 0 (max outstanding = 256) in zero frame buffer mode*/
|
||||
REG_UPDATE(DCHUBBUB_SDPIF_CFG1,
|
||||
SDPIF_MAX_NUM_OUTSTANDING, 0);
|
||||
|
||||
REG_UPDATE_2(DCHUBBUB_ARB_DF_REQ_OUTSTAND,
|
||||
DCHUBBUB_ARB_MAX_REQ_OUTSTAND, 256,
|
||||
DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 256);
|
||||
|
||||
}
|
||||
|
||||
/*static void hubbub35_set_request_limit(struct hubbub *hubbub,
|
||||
int memory_channel_count,
|
||||
int words_per_channel)
|
||||
{
|
||||
struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
|
||||
|
||||
uint32_t request_limit = 3 * memory_channel_count * words_per_channel / 4;
|
||||
|
||||
ASSERT((request_limit & (~0xFFF)) == 0); //field is only 24 bits long
|
||||
ASSERT(request_limit > 0); //field is only 24 bits long
|
||||
|
||||
if (request_limit > 0xFFF)
|
||||
request_limit = 0xFFF;
|
||||
|
||||
if (request_limit > 0)
|
||||
REG_UPDATE(SDPIF_REQUEST_RATE_LIMIT, SDPIF_REQUEST_RATE_LIMIT, request_limit);
|
||||
}*/
|
||||
|
||||
static const struct hubbub_funcs hubbub35_funcs = {
|
||||
.update_dchub = hubbub2_update_dchub,
|
||||
.init_dchub_sys_ctx = hubbub31_init_dchub_sys_ctx,
|
||||
.init_vm_ctx = hubbub2_init_vm_ctx,
|
||||
.dcc_support_swizzle = hubbub3_dcc_support_swizzle,
|
||||
.dcc_support_pixel_format = hubbub2_dcc_support_pixel_format,
|
||||
.get_dcc_compression_cap = hubbub3_get_dcc_compression_cap,
|
||||
.wm_read_state = hubbub35_wm_read_state,
|
||||
.get_dchub_ref_freq = hubbub35_get_dchub_ref_freq,
|
||||
.program_watermarks = hubbub35_program_watermarks,
|
||||
.allow_self_refresh_control = hubbub1_allow_self_refresh_control,
|
||||
.is_allow_self_refresh_enabled = hubbub1_is_allow_self_refresh_enabled,
|
||||
.verify_allow_pstate_change_high = hubbub1_verify_allow_pstate_change_high,
|
||||
.force_wm_propagate_to_pipes = hubbub32_force_wm_propagate_to_pipes,
|
||||
.force_pstate_change_control = hubbub3_force_pstate_change_control,
|
||||
.init_watermarks = hubbub35_init_watermarks,
|
||||
.program_det_size = dcn32_program_det_size,
|
||||
.program_compbuf_size = dcn35_program_compbuf_size,
|
||||
.init_crb = dcn35_init_crb,
|
||||
.hubbub_read_state = hubbub2_read_state,
|
||||
.force_usr_retraining_allow = hubbub32_force_usr_retraining_allow,
|
||||
.dchubbub_init = hubbub35_init,
|
||||
};
|
||||
|
||||
void hubbub35_construct(struct dcn20_hubbub *hubbub2,
|
||||
struct dc_context *ctx,
|
||||
const struct dcn_hubbub_registers *hubbub_regs,
|
||||
const struct dcn_hubbub_shift *hubbub_shift,
|
||||
const struct dcn_hubbub_mask *hubbub_mask,
|
||||
int det_size_kb,
|
||||
int pixel_chunk_size_kb,
|
||||
int config_return_buffer_size_kb)
|
||||
{
|
||||
hubbub2->base.ctx = ctx;
|
||||
hubbub2->base.funcs = &hubbub35_funcs;
|
||||
hubbub2->regs = hubbub_regs;
|
||||
hubbub2->shifts = hubbub_shift;
|
||||
hubbub2->masks = hubbub_mask;
|
||||
|
||||
hubbub2->debug_test_index_pstate = 0xB;
|
||||
hubbub2->detile_buf_size = det_size_kb * 1024;
|
||||
hubbub2->pixel_chunk_size = pixel_chunk_size_kb * 1024;
|
||||
hubbub2->crb_size_segs = config_return_buffer_size_kb / DCN35_CRB_SEGMENT_SIZE_KB; /*todo*/
|
||||
}
|
||||
150
drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hubbub.h
Normal file
150
drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hubbub.h
Normal file
@@ -0,0 +1,150 @@
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
/*
|
||||
* Copyright 2023 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __DC_HUBBUB_DCN35_H__
|
||||
#define __DC_HUBBUB_DCN35_H__
|
||||
|
||||
#include "dcn32/dcn32_hubbub.h"
|
||||
|
||||
#define HUBBUB_REG_LIST_DCN35(id)\
|
||||
SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\
|
||||
SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\
|
||||
SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\
|
||||
SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\
|
||||
SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\
|
||||
SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\
|
||||
SR(DCHUBBUB_ARB_SAT_LEVEL),\
|
||||
SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\
|
||||
SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
|
||||
SR(DCHUBBUB_TEST_DEBUG_INDEX), \
|
||||
SR(DCHUBBUB_TEST_DEBUG_DATA),\
|
||||
SR(DCHUBBUB_SOFT_RESET),\
|
||||
SR(DCHUBBUB_CRC_CTRL), \
|
||||
SR(DCN_VM_FB_LOCATION_BASE),\
|
||||
SR(DCN_VM_FB_LOCATION_TOP),\
|
||||
SR(DCN_VM_FB_OFFSET),\
|
||||
SR(DCN_VM_AGP_BOT),\
|
||||
SR(DCN_VM_AGP_TOP),\
|
||||
SR(DCN_VM_AGP_BASE),\
|
||||
HUBBUB_SR_WATERMARK_REG_LIST(), \
|
||||
SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A),\
|
||||
SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B),\
|
||||
SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C),\
|
||||
SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D),\
|
||||
SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A),\
|
||||
SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B),\
|
||||
SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C),\
|
||||
SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D),\
|
||||
SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A),\
|
||||
SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B),\
|
||||
SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C),\
|
||||
SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D),\
|
||||
SR(DCHUBBUB_DET0_CTRL),\
|
||||
SR(DCHUBBUB_DET1_CTRL),\
|
||||
SR(DCHUBBUB_DET2_CTRL),\
|
||||
SR(DCHUBBUB_DET3_CTRL),\
|
||||
SR(DCHUBBUB_COMPBUF_CTRL),\
|
||||
SR(COMPBUF_RESERVED_SPACE),\
|
||||
SR(DCHUBBUB_DEBUG_CTRL_0),\
|
||||
SR(DCHUBBUB_ARB_USR_RETRAINING_CNTL),\
|
||||
SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A),\
|
||||
SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B),\
|
||||
SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C),\
|
||||
SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D),\
|
||||
SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A),\
|
||||
SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B),\
|
||||
SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C),\
|
||||
SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D),\
|
||||
SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A),\
|
||||
SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B),\
|
||||
SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C),\
|
||||
SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D),\
|
||||
SR(DCN_VM_FAULT_ADDR_MSB),\
|
||||
SR(DCN_VM_FAULT_ADDR_LSB),\
|
||||
SR(DCN_VM_FAULT_CNTL),\
|
||||
SR(DCN_VM_FAULT_STATUS),\
|
||||
SR(SDPIF_REQUEST_RATE_LIMIT),\
|
||||
SR(DCHUBBUB_CLOCK_CNTL),\
|
||||
SR(DCHUBBUB_SDPIF_CFG0),\
|
||||
SR(DCHUBBUB_SDPIF_CFG1),\
|
||||
SR(DCHUBBUB_MEM_PWR_MODE_CTRL),\
|
||||
SR(DCHUBBUB_ARB_HOSTVM_CNTL),\
|
||||
SR(DCHVM_CTRL0),\
|
||||
SR(DCHVM_MEM_CTRL),\
|
||||
SR(DCHVM_CLK_CTRL),\
|
||||
SR(DCHVM_RIOMMU_CTRL0),\
|
||||
SR(DCHVM_RIOMMU_STAT0),\
|
||||
SR(DCHUBBUB_COMPBUF_CTRL),\
|
||||
SR(COMPBUF_RESERVED_SPACE),\
|
||||
SR(DCHUBBUB_DEBUG_CTRL_0),\
|
||||
SR(DCHUBBUB_CLOCK_CNTL),\
|
||||
SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A),\
|
||||
SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A),\
|
||||
SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B),\
|
||||
SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B),\
|
||||
SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C),\
|
||||
SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C),\
|
||||
SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D),\
|
||||
SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D)
|
||||
|
||||
#define HUBBUB_MASK_SH_LIST_DCN35(mask_sh)\
|
||||
HUBBUB_MASK_SH_LIST_DCN32(mask_sh), \
|
||||
HUBBUB_SF(DCHVM_CTRL0, HOSTVM_INIT_REQ, mask_sh),\
|
||||
HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_PWR_REQ_DIS, mask_sh),\
|
||||
HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_FORCE_REQ, mask_sh),\
|
||||
HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_POWER_STATUS, mask_sh),\
|
||||
HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DISPCLK_R_GATE_DIS, mask_sh),\
|
||||
HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DISPCLK_G_GATE_DIS, mask_sh),\
|
||||
HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DCFCLK_R_GATE_DIS, mask_sh),\
|
||||
HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DCFCLK_G_GATE_DIS, mask_sh),\
|
||||
HUBBUB_SF(DCHVM_CLK_CTRL, TR_REQ_REQCLKREQ_MODE, mask_sh),\
|
||||
HUBBUB_SF(DCHVM_CLK_CTRL, TW_RSP_COMPCLKREQ_MODE, mask_sh),\
|
||||
HUBBUB_SF(DCHVM_RIOMMU_CTRL0, HOSTVM_PREFETCH_REQ, mask_sh),\
|
||||
HUBBUB_SF(DCHVM_RIOMMU_CTRL0, HOSTVM_POWERSTATUS, mask_sh),\
|
||||
HUBBUB_SF(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, mask_sh),\
|
||||
HUBBUB_SF(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, mask_sh),\
|
||||
HUBBUB_SF(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE, mask_sh),\
|
||||
HUBBUB_SF(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE_CURRENT, mask_sh),\
|
||||
HUBBUB_SF(DCHUBBUB_COMPBUF_CTRL, CONFIG_ERROR, mask_sh),\
|
||||
HUBBUB_SF(COMPBUF_RESERVED_SPACE, COMPBUF_RESERVED_SPACE_64B, mask_sh),\
|
||||
HUBBUB_SF(COMPBUF_RESERVED_SPACE, COMPBUF_RESERVED_SPACE_ZS, mask_sh),\
|
||||
HUBBUB_SF(DCHUBBUB_CLOCK_CNTL, DCHUBBUB_FGCG_REP_DIS, mask_sh),\
|
||||
HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A, mask_sh), \
|
||||
HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B, mask_sh), \
|
||||
HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C, mask_sh), \
|
||||
HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D, mask_sh), \
|
||||
HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A, mask_sh), \
|
||||
HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, mask_sh), \
|
||||
HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, mask_sh), \
|
||||
HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, mask_sh)
|
||||
|
||||
void hubbub35_construct(struct dcn20_hubbub *hubbub2,
|
||||
struct dc_context *ctx,
|
||||
const struct dcn_hubbub_registers *hubbub_regs,
|
||||
const struct dcn_hubbub_shift *hubbub_shift,
|
||||
const struct dcn_hubbub_mask *hubbub_mask,
|
||||
int det_size_kb,
|
||||
int pixel_chunk_size_kb,
|
||||
int config_return_buffer_size_kb);
|
||||
#endif
|
||||
Reference in New Issue
Block a user