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pinctrl: mediatek: mt8167: Fix Schmitt trigger register offset of pins 34-39

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The correct Schmitt trigger register offset for pins 34-39 is 0xA00. Value
was verified with SoC data sheet.

Signed-off-by: Luca Leonardo Scorcia <l.scorcia@gmail.com>
Fixes: 82d70627e9 ("pinctrl: mediatek: Add MT8167 Pinctrl driver")
Signed-off-by: Linus Walleij <linusw@kernel.org>
This commit is contained in:
Luca Leonardo Scorcia
2026-05-31 17:23:32 +01:00
committed by Linus Walleij
parent 1c3044cab2
commit 439bc91d20
1 changed files with 1 additions and 1 deletions
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drivers/pinctrl/mediatek/pinctrl-mt8167.c
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@@ -244,7 +244,7 @@ static const struct mtk_pin_ies_smt_set mt8167_smt_set[] = {
MTK_PIN_IES_SMT_SPEC(24, 25, 0xA00, 12),
MTK_PIN_IES_SMT_SPEC(26, 30, 0xA00, 0),
MTK_PIN_IES_SMT_SPEC(31, 33, 0xA00, 1),
MTK_PIN_IES_SMT_SPEC(34, 39, 0xA900, 2),
MTK_PIN_IES_SMT_SPEC(34, 39, 0xA00, 2),
MTK_PIN_IES_SMT_SPEC(40, 40, 0xA10, 11),
MTK_PIN_IES_SMT_SPEC(41, 43, 0xA00, 10),
MTK_PIN_IES_SMT_SPEC(44, 47, 0xA00, 11),